[people/ms/u-boot.git] / arch / arc / lib / start.S

/*
 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/arcregs.h>

ENTRY(_start)
; ARCompact devices are not supposed to be SMP so master/slave check
; makes no sense.
#ifdef CONFIG_ISA_ARCV2
	; Non-masters will be halted immediately, they might be kicked later
	; by platform code right before passing control to the Linux kernel
	; in bootm.c:boot_jump_linux().
	lr 	r5, [identity]
	lsr	r5, r5, 8
	bmsk	r5, r5, 7
	cmp	r5, 0
	mov.nz	r0, r5
	bz	.Lmaster_proceed
	flag	1
	nop
	nop
	nop

.Lmaster_proceed:
#endif

	/* Setup interrupt vector base that matches "__text_start" */
	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]

	; Disable/enable I-cache according to configuration
	lr	r5, [ARC_BCR_IC_BUILD]
	breq	r5, 0, 1f		; I$ doesn't exist
	lr	r5, [ARC_AUX_IC_CTRL]
#ifndef CONFIG_SYS_ICACHE_OFF
	bclr	r5, r5, 0		; 0 - Enable, 1 is Disable
#else
	bset	r5, r5, 0		; I$ exists, but is not used
#endif
	sr	r5, [ARC_AUX_IC_CTRL]

	mov	r5, 1
	sr	r5, [ARC_AUX_IC_IVIC]
	; As per ARC HS databook (see chapter 5.3.3.2)
	; it is required to add 3 NOPs after each write to IC_IVIC.
	nop
	nop
	nop

1:
	; Disable/enable D-cache according to configuration
	lr	r5, [ARC_BCR_DC_BUILD]
	breq	r5, 0, 1f		; D$ doesn't exist
	lr	r5, [ARC_AUX_DC_CTRL]
	bclr	r5, r5, 6		; Invalidate (discard w/o wback)
#ifndef CONFIG_SYS_DCACHE_OFF
	bclr	r5, r5, 0		; Enable (+Inv)
#else
	bset	r5, r5, 0		; Disable (+Inv)
#endif
	sr	r5, [ARC_AUX_DC_CTRL]

	mov	r5, 1
	sr	r5, [ARC_AUX_DC_IVDC]


1:
#ifdef CONFIG_ISA_ARCV2
	; Disable System-Level Cache (SLC)
	lr	r5, [ARC_BCR_SLC]
	breq	r5, 0, 1f		; SLC doesn't exist
	lr	r5, [ARC_AUX_SLC_CTRL]
	bclr	r5, r5, 6		; Invalidate (discard w/o wback)
	bclr	r5, r5, 0		; Enable (+Inv)
	sr	r5, [ARC_AUX_SLC_CTRL]

1:
#endif

	/* Establish C runtime stack and frame */
	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
	mov	%fp, %sp

	/* Allocate reserved area from current top of stack */
	mov	%r0, %sp
	bl	board_init_f_alloc_reserve
	/* Set stack below reserved area, adjust frame pointer accordingly */
	mov	%sp, %r0
	mov	%fp, %sp

	/* Initialize reserved area - note: r0 already contains address */
	bl	board_init_f_init_reserve

	/* Zero the one and only argument of "board_init_f" */
	mov_s	%r0, 0
	j	board_init_f
ENDPROC(_start)

/*
 * void board_init_f_r_trampoline(stack-pointer address)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r0 = new stack-pointer
 */
ENTRY(board_init_f_r_trampoline)
	/* Set up the stack- and frame-pointers */
	mov	%sp, %r0
	mov	%fp, %sp

	/* Update position of intterupt vector table */
	lr	%r0, [ARC_AUX_INTR_VEC_BASE]
	ld	%r1, [%r25, GD_RELOC_OFF]
	add	%r0, %r0, %r1
	sr	%r0, [ARC_AUX_INTR_VEC_BASE]

	/* Re-enter U-Boot by calling board_init_f_r */
	j	board_init_f_r
ENDPROC(board_init_f_r_trampoline)
Commit	Line	Data
2f16ac9d AB	1	/*
	2	* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <asm-offsets.h>
	8	#include <config.h>
4d93617d	9	#include <linux/linkage.h>
2f16ac9d AB	10	#include <asm/arcregs.h>
2f16ac9d AB	11
4d93617d	12	ENTRY(_start)
cf628f77 AB	13	; ARCompact devices are not supposed to be SMP so master/slave check
	14	; makes no sense.
	15	#ifdef CONFIG_ISA_ARCV2
6cba327b AB	16	; Non-masters will be halted immediately, they might be kicked later
	17	; by platform code right before passing control to the Linux kernel
	18	; in bootm.c:boot_jump_linux().
	19	lr r5, [identity]
	20	lsr r5, r5, 8
	21	bmsk r5, r5, 7
	22	cmp r5, 0
	23	mov.nz r0, r5
	24	bz .Lmaster_proceed
	25	flag 1
	26	nop
	27	nop
	28	nop
	29
	30	.Lmaster_proceed:
cf628f77	31	#endif
6cba327b	32
20a58ac0 IG	33	/* Setup interrupt vector base that matches "__text_start" */
	34	sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
	35
ef639e6f AB	36	; Disable/enable I-cache according to configuration
	37	lr r5, [ARC_BCR_IC_BUILD]
	38	breq r5, 0, 1f ; I$ doesn't exist
	39	lr r5, [ARC_AUX_IC_CTRL]
	40	#ifndef CONFIG_SYS_ICACHE_OFF
	41	bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
	42	#else
	43	bset r5, r5, 0 ; I$ exists, but is not used
	44	#endif
	45	sr r5, [ARC_AUX_IC_CTRL]
	46
c0e6769a EP	47	mov r5, 1
	48	sr r5, [ARC_AUX_IC_IVIC]
	49	; As per ARC HS databook (see chapter 5.3.3.2)
	50	; it is required to add 3 NOPs after each write to IC_IVIC.
	51	nop
	52	nop
	53	nop
	54
ef639e6f AB	55	1:
	56	; Disable/enable D-cache according to configuration
	57	lr r5, [ARC_BCR_DC_BUILD]
	58	breq r5, 0, 1f ; D$ doesn't exist
	59	lr r5, [ARC_AUX_DC_CTRL]
	60	bclr r5, r5, 6 ; Invalidate (discard w/o wback)
	61	#ifndef CONFIG_SYS_DCACHE_OFF
	62	bclr r5, r5, 0 ; Enable (+Inv)
	63	#else
	64	bset r5, r5, 0 ; Disable (+Inv)
	65	#endif
	66	sr r5, [ARC_AUX_DC_CTRL]
20a58ac0	67
c0e6769a EP	68	mov r5, 1
	69	sr r5, [ARC_AUX_DC_IVDC]
	70
	71
ef639e6f	72	1:
6eb15e50	73	#ifdef CONFIG_ISA_ARCV2
ef639e6f AB	74	; Disable System-Level Cache (SLC)
	75	lr r5, [ARC_BCR_SLC]
	76	breq r5, 0, 1f ; SLC doesn't exist
	77	lr r5, [ARC_AUX_SLC_CTRL]
	78	bclr r5, r5, 6 ; Invalidate (discard w/o wback)
	79	bclr r5, r5, 0 ; Enable (+Inv)
	80	sr r5, [ARC_AUX_SLC_CTRL]
	81
	82	1:
6eb15e50	83	#endif
ef639e6f	84
ecc30663	85	/* Establish C runtime stack and frame */
ef639e6f AB	86	mov %sp, CONFIG_SYS_INIT_SP_ADDR
ef639e6f AB	87	mov %fp, %sp
20a58ac0	88
ecc30663	89	/* Allocate reserved area from current top of stack */
f56d625e	90	mov %r0, %sp
ecc30663 AA	91	bl board_init_f_alloc_reserve
ecc30663 AA	92	/* Set stack below reserved area, adjust frame pointer accordingly */
f56d625e AB	93	mov %sp, %r0
	94	mov %fp, %sp
	95
ecc30663 AA	96	/* Initialize reserved area - note: r0 already contains address */
	97	bl board_init_f_init_reserve
	98
20a58ac0 IG	99	/* Zero the one and only argument of "board_init_f" */
	100	mov_s %r0, 0
	101	j board_init_f
4d93617d	102	ENDPROC(_start)
20a58ac0	103
2f16ac9d	104	/*
3fb80163	105	* void board_init_f_r_trampoline(stack-pointer address)
2f16ac9d AB	106	*
	107	* This "function" does not return, instead it continues in RAM
	108	* after relocating the monitor code.
	109	*
3fb80163	110	* r0 = new stack-pointer
2f16ac9d	111	*/
3fb80163 AB	112	ENTRY(board_init_f_r_trampoline)
	113	/* Set up the stack- and frame-pointers */
	114	mov %sp, %r0
2f16ac9d AB	115	mov %fp, %sp
2f16ac9d AB	116
3fb80163 AB	117	/* Update position of intterupt vector table */
	118	lr %r0, [ARC_AUX_INTR_VEC_BASE]
	119	ld %r1, [%r25, GD_RELOC_OFF]
	120	add %r0, %r0, %r1
	121	sr %r0, [ARC_AUX_INTR_VEC_BASE]
2f16ac9d	122
3fb80163 AB	123	/* Re-enter U-Boot by calling board_init_f_r */
	124	j board_init_f_r
	125	ENDPROC(board_init_f_r_trampoline)