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9b56f4f0 SH |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Sascha Hauer, Pengutronix | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
86271115 | 25 | #include <asm/arch/imx-regs.h> |
26eecd24 | 26 | #include <div64.h> |
2cf36ae7 SB |
27 | #include <watchdog.h> |
28 | #include <asm/io.h> | |
9b56f4f0 SH |
29 | |
30 | #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ | |
31 | ||
32 | /* General purpose timers registers */ | |
1ed7a7f0 GL |
33 | #define GPTCR __REG(TIMER_BASE) /* Control register */ |
34 | #define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ | |
35 | #define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ | |
36 | #define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ | |
9b56f4f0 SH |
37 | |
38 | /* General purpose timers bitfields */ | |
1ed7a7f0 GL |
39 | #define GPTCR_SWR (1 << 15) /* Software reset */ |
40 | #define GPTCR_FRR (1 << 9) /* Freerun / restart */ | |
41 | #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ | |
42 | #define GPTCR_TEN 1 /* Timer enable */ | |
43 | ||
c44bf4e8 | 44 | DECLARE_GLOBAL_DATA_PTR; |
26eecd24 | 45 | |
6d0f6bcf | 46 | /* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */ |
1ed7a7f0 GL |
47 | #ifdef CONFIG_MX31_TIMER_HIGH_PRECISION |
48 | /* ~0.4% error - measured with stop-watch on 100s boot-delay */ | |
26eecd24 TM |
49 | static inline unsigned long long tick_to_time(unsigned long long tick) |
50 | { | |
51 | tick *= CONFIG_SYS_HZ; | |
52 | do_div(tick, CONFIG_MX31_CLK32); | |
53 | return tick; | |
54 | } | |
55 | ||
56 | static inline unsigned long long time_to_tick(unsigned long long time) | |
57 | { | |
58 | time *= CONFIG_MX31_CLK32; | |
59 | do_div(time, CONFIG_SYS_HZ); | |
60 | return time; | |
61 | } | |
62 | ||
63 | static inline unsigned long long us_to_tick(unsigned long long us) | |
64 | { | |
65 | us = us * CONFIG_MX31_CLK32 + 999999; | |
66 | do_div(us, 1000000); | |
67 | return us; | |
68 | } | |
1ed7a7f0 GL |
69 | #else |
70 | /* ~2% error */ | |
6d0f6bcf | 71 | #define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) |
1ed7a7f0 | 72 | #define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) |
9b56f4f0 | 73 | |
26eecd24 TM |
74 | static inline unsigned long long tick_to_time(unsigned long long tick) |
75 | { | |
76 | do_div(tick, TICK_PER_TIME); | |
77 | return tick; | |
78 | } | |
79 | ||
80 | static inline unsigned long long time_to_tick(unsigned long long time) | |
81 | { | |
82 | return time * TICK_PER_TIME; | |
83 | } | |
84 | ||
85 | static inline unsigned long long us_to_tick(unsigned long long us) | |
86 | { | |
87 | us += US_PER_TICK - 1; | |
88 | do_div(us, US_PER_TICK); | |
89 | return us; | |
90 | } | |
91 | #endif | |
8c4ebec2 | 92 | |
1ed7a7f0 | 93 | /* The 32768Hz 32-bit timer overruns in 131072 seconds */ |
b54384e3 | 94 | int timer_init (void) |
9b56f4f0 SH |
95 | { |
96 | int i; | |
97 | ||
98 | /* setup GP Timer 1 */ | |
99 | GPTCR = GPTCR_SWR; | |
1ed7a7f0 GL |
100 | for (i = 0; i < 100; i++) |
101 | GPTCR = 0; /* We have no udelay by now */ | |
9b56f4f0 | 102 | GPTPR = 0; /* 32Khz */ |
1ed7a7f0 GL |
103 | /* Freerun Mode, PERCLK1 input */ |
104 | GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; | |
9b56f4f0 SH |
105 | |
106 | return 0; | |
107 | } | |
108 | ||
109 | void reset_timer_masked (void) | |
110 | { | |
8c4ebec2 | 111 | /* reset time */ |
c44bf4e8 HS |
112 | gd->lastinc = GPTCNT; /* capture current incrementer value time */ |
113 | gd->tbl = 0; /* start "advancing" time stamp from 0 */ | |
8c4ebec2 ML |
114 | } |
115 | ||
1ed7a7f0 | 116 | unsigned long long get_ticks (void) |
9b56f4f0 | 117 | { |
8c4ebec2 ML |
118 | ulong now = GPTCNT; /* current tick value */ |
119 | ||
c44bf4e8 | 120 | if (now >= gd->lastinc) /* normal mode (non roll) */ |
8c4ebec2 | 121 | /* move stamp forward with absolut diff ticks */ |
c44bf4e8 | 122 | gd->tbl += (now - gd->lastinc); |
8c4ebec2 | 123 | else /* we have rollover of incrementer */ |
c44bf4e8 HS |
124 | gd->tbl += (0xFFFFFFFF - gd->lastinc) + now; |
125 | gd->lastinc = now; | |
126 | return gd->tbl; | |
9b56f4f0 SH |
127 | } |
128 | ||
1ed7a7f0 GL |
129 | ulong get_timer_masked (void) |
130 | { | |
131 | /* | |
132 | * get_ticks() returns a long long (64 bit), it wraps in | |
133 | * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ | |
6d0f6bcf | 134 | * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in |
1ed7a7f0 GL |
135 | * 5 * 10^6 days - long enough. |
136 | */ | |
26eecd24 | 137 | return tick_to_time(get_ticks()); |
1ed7a7f0 GL |
138 | } |
139 | ||
9b56f4f0 SH |
140 | ulong get_timer (ulong base) |
141 | { | |
142 | return get_timer_masked () - base; | |
143 | } | |
144 | ||
92381c41 | 145 | /* delay x useconds AND preserve advance timestamp value */ |
3eb90bad | 146 | void __udelay (unsigned long usec) |
9b56f4f0 | 147 | { |
1ed7a7f0 GL |
148 | unsigned long long tmp; |
149 | ulong tmo; | |
150 | ||
26eecd24 | 151 | tmo = us_to_tick(usec); |
1ed7a7f0 GL |
152 | tmp = get_ticks() + tmo; /* get current timestamp */ |
153 | ||
154 | while (get_ticks() < tmp) /* loop till event */ | |
155 | /*NOP*/; | |
9b56f4f0 SH |
156 | } |
157 | ||
158 | void reset_cpu (ulong addr) | |
159 | { | |
2cf36ae7 SB |
160 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; |
161 | wdog->wcr = WDOG_ENABLE; | |
162 | while (1) | |
163 | ; | |
9b56f4f0 | 164 | } |
2cf36ae7 SB |
165 | |
166 | #ifdef CONFIG_HW_WATCHDOG | |
167 | void mxc_hw_watchdog_enable(void) | |
168 | { | |
169 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; | |
170 | u16 secs; | |
171 | ||
172 | /* | |
173 | * The timer watchdog can be set between | |
174 | * 0.5 and 128 Seconds. If not defined | |
175 | * in configuration file, sets 64 Seconds | |
176 | */ | |
177 | #ifdef CONFIG_SYS_WD_TIMER_SECS | |
178 | secs = (CONFIG_SYS_WD_TIMER_SECS << 1) & 0xFF; | |
179 | if (!secs) secs = 1; | |
180 | #else | |
181 | secs = 64; | |
182 | #endif | |
183 | writew(readw(&wdog->wcr) | (secs << WDOG_WT_SHIFT) | WDOG_ENABLE, | |
184 | &wdog->wcr); | |
185 | } | |
186 | ||
187 | ||
188 | void mxc_hw_watchdog_reset(void) | |
189 | { | |
190 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; | |
191 | ||
192 | writew(0x5555, &wdog->wsr); | |
193 | writew(0xAAAA, &wdog->wsr); | |
194 | } | |
195 | #endif |