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9b56f4f0 SH |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Sascha Hauer, Pengutronix | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/arch/mx31-regs.h> | |
26eecd24 | 26 | #include <div64.h> |
9b56f4f0 SH |
27 | |
28 | #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ | |
29 | ||
30 | /* General purpose timers registers */ | |
1ed7a7f0 GL |
31 | #define GPTCR __REG(TIMER_BASE) /* Control register */ |
32 | #define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ | |
33 | #define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ | |
34 | #define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ | |
9b56f4f0 SH |
35 | |
36 | /* General purpose timers bitfields */ | |
1ed7a7f0 GL |
37 | #define GPTCR_SWR (1 << 15) /* Software reset */ |
38 | #define GPTCR_FRR (1 << 9) /* Freerun / restart */ | |
39 | #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ | |
40 | #define GPTCR_TEN 1 /* Timer enable */ | |
41 | ||
c44bf4e8 | 42 | DECLARE_GLOBAL_DATA_PTR; |
26eecd24 | 43 | |
6d0f6bcf | 44 | /* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */ |
1ed7a7f0 GL |
45 | #ifdef CONFIG_MX31_TIMER_HIGH_PRECISION |
46 | /* ~0.4% error - measured with stop-watch on 100s boot-delay */ | |
26eecd24 TM |
47 | static inline unsigned long long tick_to_time(unsigned long long tick) |
48 | { | |
49 | tick *= CONFIG_SYS_HZ; | |
50 | do_div(tick, CONFIG_MX31_CLK32); | |
51 | return tick; | |
52 | } | |
53 | ||
54 | static inline unsigned long long time_to_tick(unsigned long long time) | |
55 | { | |
56 | time *= CONFIG_MX31_CLK32; | |
57 | do_div(time, CONFIG_SYS_HZ); | |
58 | return time; | |
59 | } | |
60 | ||
61 | static inline unsigned long long us_to_tick(unsigned long long us) | |
62 | { | |
63 | us = us * CONFIG_MX31_CLK32 + 999999; | |
64 | do_div(us, 1000000); | |
65 | return us; | |
66 | } | |
1ed7a7f0 GL |
67 | #else |
68 | /* ~2% error */ | |
6d0f6bcf | 69 | #define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) |
1ed7a7f0 | 70 | #define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) |
9b56f4f0 | 71 | |
26eecd24 TM |
72 | static inline unsigned long long tick_to_time(unsigned long long tick) |
73 | { | |
74 | do_div(tick, TICK_PER_TIME); | |
75 | return tick; | |
76 | } | |
77 | ||
78 | static inline unsigned long long time_to_tick(unsigned long long time) | |
79 | { | |
80 | return time * TICK_PER_TIME; | |
81 | } | |
82 | ||
83 | static inline unsigned long long us_to_tick(unsigned long long us) | |
84 | { | |
85 | us += US_PER_TICK - 1; | |
86 | do_div(us, US_PER_TICK); | |
87 | return us; | |
88 | } | |
89 | #endif | |
8c4ebec2 | 90 | |
1ed7a7f0 | 91 | /* The 32768Hz 32-bit timer overruns in 131072 seconds */ |
b54384e3 | 92 | int timer_init (void) |
9b56f4f0 SH |
93 | { |
94 | int i; | |
95 | ||
96 | /* setup GP Timer 1 */ | |
97 | GPTCR = GPTCR_SWR; | |
1ed7a7f0 GL |
98 | for (i = 0; i < 100; i++) |
99 | GPTCR = 0; /* We have no udelay by now */ | |
9b56f4f0 | 100 | GPTPR = 0; /* 32Khz */ |
1ed7a7f0 GL |
101 | /* Freerun Mode, PERCLK1 input */ |
102 | GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; | |
9b56f4f0 SH |
103 | |
104 | return 0; | |
105 | } | |
106 | ||
107 | void reset_timer_masked (void) | |
108 | { | |
8c4ebec2 | 109 | /* reset time */ |
c44bf4e8 HS |
110 | gd->lastinc = GPTCNT; /* capture current incrementer value time */ |
111 | gd->tbl = 0; /* start "advancing" time stamp from 0 */ | |
8c4ebec2 ML |
112 | } |
113 | ||
114 | void reset_timer(void) | |
115 | { | |
116 | reset_timer_masked(); | |
9b56f4f0 SH |
117 | } |
118 | ||
1ed7a7f0 | 119 | unsigned long long get_ticks (void) |
9b56f4f0 | 120 | { |
8c4ebec2 ML |
121 | ulong now = GPTCNT; /* current tick value */ |
122 | ||
c44bf4e8 | 123 | if (now >= gd->lastinc) /* normal mode (non roll) */ |
8c4ebec2 | 124 | /* move stamp forward with absolut diff ticks */ |
c44bf4e8 | 125 | gd->tbl += (now - gd->lastinc); |
8c4ebec2 | 126 | else /* we have rollover of incrementer */ |
c44bf4e8 HS |
127 | gd->tbl += (0xFFFFFFFF - gd->lastinc) + now; |
128 | gd->lastinc = now; | |
129 | return gd->tbl; | |
9b56f4f0 SH |
130 | } |
131 | ||
1ed7a7f0 GL |
132 | ulong get_timer_masked (void) |
133 | { | |
134 | /* | |
135 | * get_ticks() returns a long long (64 bit), it wraps in | |
136 | * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ | |
6d0f6bcf | 137 | * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in |
1ed7a7f0 GL |
138 | * 5 * 10^6 days - long enough. |
139 | */ | |
26eecd24 | 140 | return tick_to_time(get_ticks()); |
1ed7a7f0 GL |
141 | } |
142 | ||
9b56f4f0 SH |
143 | ulong get_timer (ulong base) |
144 | { | |
145 | return get_timer_masked () - base; | |
146 | } | |
147 | ||
148 | void set_timer (ulong t) | |
149 | { | |
c44bf4e8 | 150 | gd->tbl = time_to_tick(t); |
9b56f4f0 SH |
151 | } |
152 | ||
92381c41 | 153 | /* delay x useconds AND preserve advance timestamp value */ |
3eb90bad | 154 | void __udelay (unsigned long usec) |
9b56f4f0 | 155 | { |
1ed7a7f0 GL |
156 | unsigned long long tmp; |
157 | ulong tmo; | |
158 | ||
26eecd24 | 159 | tmo = us_to_tick(usec); |
1ed7a7f0 GL |
160 | tmp = get_ticks() + tmo; /* get current timestamp */ |
161 | ||
162 | while (get_ticks() < tmp) /* loop till event */ | |
163 | /*NOP*/; | |
9b56f4f0 SH |
164 | } |
165 | ||
166 | void reset_cpu (ulong addr) | |
167 | { | |
168 | __REG16(WDOG_BASE) = 4; | |
169 | } |