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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
9b56f4f0 SH |
2 | /* |
3 | * (C) Copyright 2007 | |
4 | * Sascha Hauer, Pengutronix | |
9b56f4f0 SH |
5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
691d719d | 8 | #include <init.h> |
86271115 | 9 | #include <asm/arch/imx-regs.h> |
2cf36ae7 | 10 | #include <asm/io.h> |
9b56f4f0 SH |
11 | |
12 | #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ | |
13 | ||
14 | /* General purpose timers registers */ | |
1ed7a7f0 GL |
15 | #define GPTCR __REG(TIMER_BASE) /* Control register */ |
16 | #define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ | |
17 | #define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ | |
18 | #define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ | |
9b56f4f0 SH |
19 | |
20 | /* General purpose timers bitfields */ | |
1ed7a7f0 GL |
21 | #define GPTCR_SWR (1 << 15) /* Software reset */ |
22 | #define GPTCR_FRR (1 << 9) /* Freerun / restart */ | |
23 | #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ | |
24 | #define GPTCR_TEN 1 /* Timer enable */ | |
25 | ||
1ed7a7f0 | 26 | /* The 32768Hz 32-bit timer overruns in 131072 seconds */ |
77f11a99 | 27 | int timer_init(void) |
9b56f4f0 SH |
28 | { |
29 | int i; | |
30 | ||
31 | /* setup GP Timer 1 */ | |
32 | GPTCR = GPTCR_SWR; | |
1ed7a7f0 GL |
33 | for (i = 0; i < 100; i++) |
34 | GPTCR = 0; /* We have no udelay by now */ | |
9b56f4f0 | 35 | GPTPR = 0; /* 32Khz */ |
1ed7a7f0 GL |
36 | /* Freerun Mode, PERCLK1 input */ |
37 | GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; | |
9b56f4f0 SH |
38 | |
39 | return 0; | |
40 | } | |
41 | ||
93a0ea50 | 42 | unsigned long timer_read_counter(void) |
60ebcffb | 43 | { |
93a0ea50 | 44 | return GPTCNT; |
60ebcffb | 45 | } |