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Commit | Line | Data |
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c609719b | 1 | /* |
281e00a3 | 2 | * (C) Copyright 2001-2004 |
c609719b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * David Mueller, ELSOFT AG, d.mueller@elsoft.ch | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
9 | */ |
10 | ||
11 | /* This code should work for both the S3C2400 and the S3C2410 | |
12 | * as they seem to have the same PLL and clock machinery inside. | |
13 | * The different address mapping is handled by the s3c24xx.h files below. | |
14 | */ | |
15 | ||
16 | #include <common.h> | |
ac67804f | 17 | #ifdef CONFIG_S3C24X0 |
281e00a3 | 18 | |
d67cce2d | 19 | #include <asm/io.h> |
ac67804f | 20 | #include <asm/arch/s3c24x0_cpu.h> |
c609719b WD |
21 | |
22 | #define MPLL 0 | |
23 | #define UPLL 1 | |
24 | ||
25 | /* ------------------------------------------------------------------------- */ | |
26 | /* NOTE: This describes the proper use of this file. | |
27 | * | |
7f6c2cbc | 28 | * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. |
c609719b WD |
29 | * |
30 | * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of | |
31 | * the specified bus in HZ. | |
32 | */ | |
33 | /* ------------------------------------------------------------------------- */ | |
34 | ||
35 | static ulong get_PLLCLK(int pllreg) | |
36 | { | |
d67cce2d | 37 | struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); |
38 | ulong r, m, p, s; | |
c609719b | 39 | |
d67cce2d | 40 | if (pllreg == MPLL) |
d9abba82 | 41 | r = readl(&clk_power->mpllcon); |
d67cce2d | 42 | else if (pllreg == UPLL) |
d9abba82 | 43 | r = readl(&clk_power->upllcon); |
d67cce2d | 44 | else |
45 | hang(); | |
c609719b | 46 | |
d67cce2d | 47 | m = ((r & 0xFF000) >> 12) + 8; |
48 | p = ((r & 0x003F0) >> 4) + 2; | |
49 | s = r & 0x3; | |
c609719b | 50 | |
d9abba82 N |
51 | #if defined(CONFIG_S3C2440) |
52 | if (pllreg == MPLL) | |
53 | return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s)); | |
54 | #endif | |
d67cce2d | 55 | return (CONFIG_SYS_CLK_FREQ * m) / (p << s); |
d9abba82 | 56 | |
c609719b WD |
57 | } |
58 | ||
59 | /* return FCLK frequency */ | |
60 | ulong get_FCLK(void) | |
61 | { | |
d67cce2d | 62 | return get_PLLCLK(MPLL); |
c609719b WD |
63 | } |
64 | ||
65 | /* return HCLK frequency */ | |
66 | ulong get_HCLK(void) | |
67 | { | |
d67cce2d | 68 | struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); |
d9abba82 N |
69 | #ifdef CONFIG_S3C2440 |
70 | switch (readl(&clk_power->clkdivn) & 0x6) { | |
71 | default: | |
72 | case 0: | |
73 | return get_FCLK(); | |
74 | case 2: | |
75 | return get_FCLK() / 2; | |
76 | case 4: | |
77 | return (readl(&clk_power->camdivn) & (1 << 9)) ? | |
78 | get_FCLK() / 8 : get_FCLK() / 4; | |
79 | case 6: | |
80 | return (readl(&clk_power->camdivn) & (1 << 8)) ? | |
81 | get_FCLK() / 6 : get_FCLK() / 3; | |
82 | } | |
83 | #else | |
84 | return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK(); | |
85 | #endif | |
c609719b WD |
86 | } |
87 | ||
88 | /* return PCLK frequency */ | |
89 | ulong get_PCLK(void) | |
90 | { | |
d67cce2d | 91 | struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); |
c609719b | 92 | |
d9abba82 | 93 | return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK(); |
c609719b WD |
94 | } |
95 | ||
96 | /* return UCLK frequency */ | |
97 | ulong get_UCLK(void) | |
98 | { | |
d67cce2d | 99 | return get_PLLCLK(UPLL); |
c609719b | 100 | } |
281e00a3 | 101 | |
ac67804f | 102 | #endif /* CONFIG_S3C24X0 */ |