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Commit | Line | Data |
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fe8c2806 WD |
1 | /* |
2 | * armboot - Startup Code for ARM920 CPU-core | |
3 | * | |
fa82f871 AA |
4 | * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> |
5 | * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> | |
792a09eb | 6 | * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> |
fe8c2806 WD |
7 | * |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
25ddd1fb | 27 | #include <asm-offsets.h> |
9689ddcc | 28 | #include <common.h> |
fe8c2806 | 29 | #include <config.h> |
fe8c2806 WD |
30 | |
31 | /* | |
32 | ************************************************************************* | |
33 | * | |
34 | * Jump vector table as in table 3.1 in [1] | |
35 | * | |
36 | ************************************************************************* | |
37 | */ | |
38 | ||
39 | ||
40 | .globl _start | |
d67cce2d | 41 | _start: b start_code |
fe8c2806 WD |
42 | ldr pc, _undefined_instruction |
43 | ldr pc, _software_interrupt | |
44 | ldr pc, _prefetch_abort | |
45 | ldr pc, _data_abort | |
46 | ldr pc, _not_used | |
47 | ldr pc, _irq | |
48 | ldr pc, _fiq | |
49 | ||
50 | _undefined_instruction: .word undefined_instruction | |
51 | _software_interrupt: .word software_interrupt | |
52 | _prefetch_abort: .word prefetch_abort | |
53 | _data_abort: .word data_abort | |
54 | _not_used: .word not_used | |
55 | _irq: .word irq | |
56 | _fiq: .word fiq | |
57 | ||
58 | .balignl 16,0xdeadbeef | |
59 | ||
60 | ||
61 | /* | |
62 | ************************************************************************* | |
63 | * | |
80767a6c | 64 | * Startup Code (called from the ARM reset exception vector) |
fe8c2806 WD |
65 | * |
66 | * do important init only if we don't start from memory! | |
67 | * relocate armboot to ram | |
68 | * setup stack | |
69 | * jump to second stage | |
70 | * | |
71 | ************************************************************************* | |
72 | */ | |
73 | ||
cc7cdcbd | 74 | .globl _TEXT_BASE |
fe8c2806 | 75 | _TEXT_BASE: |
14d0a02a | 76 | .word CONFIG_SYS_TEXT_BASE |
fe8c2806 | 77 | |
fe8c2806 | 78 | /* |
f6e20fc6 | 79 | * These are defined in the board-specific linker script. |
3336ca60 AA |
80 | * Subtracting _start from them lets the linker put their |
81 | * relative position in the executable instead of leaving | |
82 | * them null. | |
fe8c2806 | 83 | */ |
3336ca60 AA |
84 | .globl _bss_start_ofs |
85 | _bss_start_ofs: | |
86 | .word __bss_start - _start | |
f6e20fc6 | 87 | |
3336ca60 AA |
88 | .globl _bss_end_ofs |
89 | _bss_end_ofs: | |
44c6e659 | 90 | .word __bss_end__ - _start |
fe8c2806 | 91 | |
f326cbba PYC |
92 | .globl _end_ofs |
93 | _end_ofs: | |
94 | .word _end - _start | |
95 | ||
fe8c2806 WD |
96 | #ifdef CONFIG_USE_IRQ |
97 | /* IRQ stack memory (calculated at run-time) */ | |
98 | .globl IRQ_STACK_START | |
99 | IRQ_STACK_START: | |
100 | .word 0x0badc0de | |
101 | ||
102 | /* IRQ stack memory (calculated at run-time) */ | |
103 | .globl FIQ_STACK_START | |
104 | FIQ_STACK_START: | |
105 | .word 0x0badc0de | |
106 | #endif | |
107 | ||
cc7cdcbd HS |
108 | /* IRQ stack memory (calculated at run-time) + 8 bytes */ |
109 | .globl IRQ_STACK_START_IN | |
110 | IRQ_STACK_START_IN: | |
111 | .word 0x0badc0de | |
112 | ||
fe8c2806 | 113 | /* |
80767a6c | 114 | * the actual start code |
fe8c2806 WD |
115 | */ |
116 | ||
80767a6c | 117 | start_code: |
fe8c2806 WD |
118 | /* |
119 | * set the cpu to SVC32 mode | |
120 | */ | |
d67cce2d | 121 | mrs r0, cpsr |
122 | bic r0, r0, #0x1f | |
123 | orr r0, r0, #0xd3 | |
124 | msr cpsr, r0 | |
80767a6c | 125 | |
ed3b18e0 | 126 | #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) |
d4fc6012 | 127 | /* |
80767a6c | 128 | * relocate exception table |
d4fc6012 PP |
129 | */ |
130 | ldr r0, =_start | |
131 | ldr r1, =0x0 | |
132 | mov r2, #16 | |
133 | copyex: | |
134 | subs r2, r2, #1 | |
135 | ldr r3, [r0], #4 | |
136 | str r3, [r1], #4 | |
137 | bne copyex | |
138 | #endif | |
139 | ||
ac67804f | 140 | #ifdef CONFIG_S3C24X0 |
80767a6c PP |
141 | /* turn off the watchdog */ |
142 | ||
143 | # if defined(CONFIG_S3C2400) | |
d67cce2d | 144 | # define pWTCON 0x15300000 |
16263087 | 145 | # define INTMSK 0x14400008 /* Interrupt-Controller base addresses */ |
80767a6c PP |
146 | # define CLKDIVN 0x14800014 /* clock divisor register */ |
147 | #else | |
d67cce2d | 148 | # define pWTCON 0x53000000 |
16263087 | 149 | # define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */ |
80767a6c PP |
150 | # define INTSUBMSK 0x4A00001C |
151 | # define CLKDIVN 0x4C000014 /* clock divisor register */ | |
152 | # endif | |
153 | ||
d67cce2d | 154 | ldr r0, =pWTCON |
155 | mov r1, #0x0 | |
156 | str r1, [r0] | |
fe8c2806 WD |
157 | |
158 | /* | |
159 | * mask all IRQs by setting all bits in the INTMR - default | |
160 | */ | |
161 | mov r1, #0xffffffff | |
162 | ldr r0, =INTMSK | |
163 | str r1, [r0] | |
281e00a3 | 164 | # if defined(CONFIG_S3C2410) |
fe8c2806 WD |
165 | ldr r1, =0x3ff |
166 | ldr r0, =INTSUBMSK | |
167 | str r1, [r0] | |
281e00a3 | 168 | # endif |
fe8c2806 WD |
169 | |
170 | /* FCLK:HCLK:PCLK = 1:2:4 */ | |
171 | /* default FCLK is 120 MHz ! */ | |
172 | ldr r0, =CLKDIVN | |
173 | mov r1, #3 | |
174 | str r1, [r0] | |
ac67804f | 175 | #endif /* CONFIG_S3C24X0 */ |
fe8c2806 WD |
176 | |
177 | /* | |
178 | * we do sys-critical inits only at reboot, | |
179 | * not when booting from ram! | |
180 | */ | |
8aa1a2d1 | 181 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
fe8c2806 WD |
182 | bl cpu_init_crit |
183 | #endif | |
184 | ||
cc7cdcbd HS |
185 | /* Set stackpointer in internal RAM to call board_init_f */ |
186 | call_board_init_f: | |
187 | ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) | |
296cae73 | 188 | bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ |
cc7cdcbd HS |
189 | ldr r0,=0x00000000 |
190 | bl board_init_f | |
191 | ||
192 | /*------------------------------------------------------------------------------*/ | |
193 | ||
194 | /* | |
195 | * void relocate_code (addr_sp, gd, addr_moni) | |
196 | * | |
197 | * This "function" does not return, instead it continues in RAM | |
198 | * after relocating the monitor code. | |
199 | * | |
200 | */ | |
201 | .globl relocate_code | |
202 | relocate_code: | |
203 | mov r4, r0 /* save addr_sp */ | |
204 | mov r5, r1 /* save addr of gd */ | |
205 | mov r6, r2 /* save addr of destination */ | |
cc7cdcbd HS |
206 | |
207 | /* Set up the stack */ | |
208 | stack_setup: | |
209 | mov sp, r4 | |
210 | ||
211 | adr r0, _start | |
a1a47d3c | 212 | cmp r0, r6 |
76abfa57 | 213 | moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ |
a1a47d3c | 214 | beq clear_bss /* skip relocation */ |
a78fb68f | 215 | mov r1, r6 /* r1 <- scratch for copy_loop */ |
3336ca60 AA |
216 | ldr r3, _bss_start_ofs |
217 | add r2, r0, r3 /* r2 <- source end address */ | |
cc7cdcbd | 218 | |
cc7cdcbd HS |
219 | copy_loop: |
220 | ldmia r0!, {r9-r10} /* copy from source address [r0] */ | |
a78fb68f | 221 | stmia r1!, {r9-r10} /* copy to target address [r1] */ |
da90d4ce AA |
222 | cmp r0, r2 /* until source end address [r2] */ |
223 | blo copy_loop | |
cc7cdcbd | 224 | |
401bb30b | 225 | #ifndef CONFIG_SPL_BUILD |
3336ca60 AA |
226 | /* |
227 | * fix .rel.dyn relocations | |
228 | */ | |
229 | ldr r0, _TEXT_BASE /* r0 <- Text base */ | |
a78fb68f | 230 | sub r9, r6, r0 /* r9 <- relocation offset */ |
3336ca60 AA |
231 | ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ |
232 | add r10, r10, r0 /* r10 <- sym table in FLASH */ | |
233 | ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ | |
234 | add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ | |
235 | ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ | |
236 | add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ | |
cc7cdcbd | 237 | fixloop: |
3336ca60 AA |
238 | ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ |
239 | add r0, r0, r9 /* r0 <- location to fix up in RAM */ | |
240 | ldr r1, [r2, #4] | |
1f52d89f AB |
241 | and r7, r1, #0xff |
242 | cmp r7, #23 /* relative fixup? */ | |
3336ca60 | 243 | beq fixrel |
1f52d89f | 244 | cmp r7, #2 /* absolute fixup? */ |
3336ca60 AA |
245 | beq fixabs |
246 | /* ignore unknown type of fixup */ | |
247 | b fixnext | |
248 | fixabs: | |
249 | /* absolute fix: set location to (offset) symbol value */ | |
250 | mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ | |
251 | add r1, r10, r1 /* r1 <- address of symbol in table */ | |
252 | ldr r1, [r1, #4] /* r1 <- symbol value */ | |
3600945b | 253 | add r1, r1, r9 /* r1 <- relocated sym addr */ |
3336ca60 AA |
254 | b fixnext |
255 | fixrel: | |
256 | /* relative fix: increase location by offset */ | |
257 | ldr r1, [r0] | |
258 | add r1, r1, r9 | |
259 | fixnext: | |
260 | str r1, [r0] | |
261 | add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ | |
cc7cdcbd | 262 | cmp r2, r3 |
79e63139 | 263 | blo fixloop |
cc7cdcbd | 264 | #endif |
cc7cdcbd HS |
265 | |
266 | clear_bss: | |
401bb30b | 267 | #ifndef CONFIG_SPL_BUILD |
3336ca60 AA |
268 | ldr r0, _bss_start_ofs |
269 | ldr r1, _bss_end_ofs | |
a78fb68f | 270 | mov r4, r6 /* reloc addr */ |
cc7cdcbd | 271 | add r0, r0, r4 |
cc7cdcbd HS |
272 | add r1, r1, r4 |
273 | mov r2, #0x00000000 /* clear */ | |
274 | ||
448217d4 ZH |
275 | clbss_l:cmp r0, r1 /* clear loop... */ |
276 | bhs clbss_e /* if reached end of bss, exit */ | |
277 | str r2, [r0] | |
cc7cdcbd | 278 | add r0, r0, #4 |
448217d4 ZH |
279 | b clbss_l |
280 | clbss_e: | |
cc7cdcbd HS |
281 | |
282 | bl coloured_LED_init | |
2d3be7c4 | 283 | bl red_led_on |
cc7cdcbd HS |
284 | #endif |
285 | ||
286 | /* | |
287 | * We are done. Do not return, instead branch to second part of board | |
288 | * initialization, now running from RAM. | |
289 | */ | |
290 | #ifdef CONFIG_NAND_SPL | |
3336ca60 AA |
291 | ldr r0, _nand_boot_ofs |
292 | mov pc, r0 | |
cc7cdcbd | 293 | |
3336ca60 AA |
294 | _nand_boot_ofs: |
295 | .word nand_boot | |
cc7cdcbd | 296 | #else |
3336ca60 AA |
297 | ldr r0, _board_init_r_ofs |
298 | adr r1, _start | |
299 | add lr, r0, r1 | |
300 | add lr, lr, r9 | |
cc7cdcbd HS |
301 | /* setup parameters for board_init_r */ |
302 | mov r0, r5 /* gd_t */ | |
a78fb68f | 303 | mov r1, r6 /* dest_addr */ |
cc7cdcbd | 304 | /* jump to it ... */ |
cc7cdcbd HS |
305 | mov pc, lr |
306 | ||
3336ca60 AA |
307 | _board_init_r_ofs: |
308 | .word board_init_r - _start | |
cc7cdcbd HS |
309 | #endif |
310 | ||
3336ca60 AA |
311 | _rel_dyn_start_ofs: |
312 | .word __rel_dyn_start - _start | |
313 | _rel_dyn_end_ofs: | |
314 | .word __rel_dyn_end - _start | |
315 | _dynsym_start_ofs: | |
316 | .word __dynsym_start - _start | |
317 | ||
fe8c2806 WD |
318 | /* |
319 | ************************************************************************* | |
320 | * | |
321 | * CPU_init_critical registers | |
322 | * | |
323 | * setup important registers | |
324 | * setup memory timing | |
325 | * | |
326 | ************************************************************************* | |
327 | */ | |
328 | ||
329 | ||
db28ddb4 | 330 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
fe8c2806 WD |
331 | cpu_init_crit: |
332 | /* | |
333 | * flush v4 I/D caches | |
334 | */ | |
335 | mov r0, #0 | |
336 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ | |
337 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ | |
338 | ||
339 | /* | |
340 | * disable MMU stuff and caches | |
341 | */ | |
342 | mrc p15, 0, r0, c1, c0, 0 | |
343 | bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) | |
344 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) | |
345 | orr r0, r0, #0x00000002 @ set bit 2 (A) Align | |
346 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache | |
347 | mcr p15, 0, r0, c1, c0, 0 | |
348 | ||
fe8c2806 WD |
349 | /* |
350 | * before relocating, we have to setup RAM timing | |
351 | * because memory timing is board-dependend, you will | |
400558b5 | 352 | * find a lowlevel_init.S in your board directory. |
fe8c2806 WD |
353 | */ |
354 | mov ip, lr | |
d4fc6012 | 355 | |
400558b5 | 356 | bl lowlevel_init |
cb82a532 | 357 | |
fe8c2806 | 358 | mov lr, ip |
fe8c2806 | 359 | mov pc, lr |
db28ddb4 | 360 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
fe8c2806 | 361 | |
fe8c2806 WD |
362 | /* |
363 | ************************************************************************* | |
364 | * | |
365 | * Interrupt handling | |
366 | * | |
367 | ************************************************************************* | |
368 | */ | |
369 | ||
370 | @ | |
371 | @ IRQ stack frame. | |
372 | @ | |
373 | #define S_FRAME_SIZE 72 | |
374 | ||
375 | #define S_OLD_R0 68 | |
376 | #define S_PSR 64 | |
377 | #define S_PC 60 | |
378 | #define S_LR 56 | |
379 | #define S_SP 52 | |
380 | ||
381 | #define S_IP 48 | |
382 | #define S_FP 44 | |
383 | #define S_R10 40 | |
384 | #define S_R9 36 | |
385 | #define S_R8 32 | |
386 | #define S_R7 28 | |
387 | #define S_R6 24 | |
388 | #define S_R5 20 | |
389 | #define S_R4 16 | |
390 | #define S_R3 12 | |
391 | #define S_R2 8 | |
392 | #define S_R1 4 | |
393 | #define S_R0 0 | |
394 | ||
d67cce2d | 395 | #define MODE_SVC 0x13 |
396 | #define I_BIT 0x80 | |
fe8c2806 WD |
397 | |
398 | /* | |
399 | * use bad_save_user_regs for abort/prefetch/undef/swi ... | |
400 | * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling | |
401 | */ | |
402 | ||
403 | .macro bad_save_user_regs | |
404 | sub sp, sp, #S_FRAME_SIZE | |
405 | stmia sp, {r0 - r12} @ Calling r0-r12 | |
cc7cdcbd | 406 | ldr r2, IRQ_STACK_START_IN |
f07771cc | 407 | ldmia r2, {r2 - r3} @ get pc, cpsr |
fe8c2806 WD |
408 | add r0, sp, #S_FRAME_SIZE @ restore sp_SVC |
409 | ||
410 | add r5, sp, #S_SP | |
411 | mov r1, lr | |
f07771cc | 412 | stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr |
fe8c2806 WD |
413 | mov r0, sp |
414 | .endm | |
415 | ||
416 | .macro irq_save_user_regs | |
417 | sub sp, sp, #S_FRAME_SIZE | |
418 | stmia sp, {r0 - r12} @ Calling r0-r12 | |
d67cce2d | 419 | add r7, sp, #S_PC |
420 | stmdb r7, {sp, lr}^ @ Calling SP, LR | |
421 | str lr, [r7, #0] @ Save calling PC | |
422 | mrs r6, spsr | |
423 | str r6, [r7, #4] @ Save CPSR | |
424 | str r0, [r7, #8] @ Save OLD_R0 | |
fe8c2806 WD |
425 | mov r0, sp |
426 | .endm | |
427 | ||
428 | .macro irq_restore_user_regs | |
429 | ldmia sp, {r0 - lr}^ @ Calling r0 - lr | |
430 | mov r0, r0 | |
431 | ldr lr, [sp, #S_PC] @ Get PC | |
432 | add sp, sp, #S_FRAME_SIZE | |
d67cce2d | 433 | /* return & move spsr_svc into cpsr */ |
434 | subs pc, lr, #4 | |
fe8c2806 WD |
435 | .endm |
436 | ||
437 | .macro get_bad_stack | |
cc7cdcbd | 438 | ldr r13, IRQ_STACK_START_IN @ setup our mode stack |
fe8c2806 WD |
439 | |
440 | str lr, [r13] @ save caller lr / spsr | |
441 | mrs lr, spsr | |
d67cce2d | 442 | str lr, [r13, #4] |
fe8c2806 WD |
443 | |
444 | mov r13, #MODE_SVC @ prepare SVC-Mode | |
445 | @ msr spsr_c, r13 | |
446 | msr spsr, r13 | |
447 | mov lr, pc | |
448 | movs pc, lr | |
449 | .endm | |
450 | ||
451 | .macro get_irq_stack @ setup IRQ stack | |
452 | ldr sp, IRQ_STACK_START | |
453 | .endm | |
454 | ||
455 | .macro get_fiq_stack @ setup FIQ stack | |
456 | ldr sp, FIQ_STACK_START | |
457 | .endm | |
458 | ||
459 | /* | |
460 | * exception handlers | |
461 | */ | |
462 | .align 5 | |
463 | undefined_instruction: | |
464 | get_bad_stack | |
465 | bad_save_user_regs | |
53677ef1 | 466 | bl do_undefined_instruction |
fe8c2806 WD |
467 | |
468 | .align 5 | |
469 | software_interrupt: | |
470 | get_bad_stack | |
471 | bad_save_user_regs | |
53677ef1 | 472 | bl do_software_interrupt |
fe8c2806 WD |
473 | |
474 | .align 5 | |
475 | prefetch_abort: | |
476 | get_bad_stack | |
477 | bad_save_user_regs | |
53677ef1 | 478 | bl do_prefetch_abort |
fe8c2806 WD |
479 | |
480 | .align 5 | |
481 | data_abort: | |
482 | get_bad_stack | |
483 | bad_save_user_regs | |
53677ef1 | 484 | bl do_data_abort |
fe8c2806 WD |
485 | |
486 | .align 5 | |
487 | not_used: | |
488 | get_bad_stack | |
489 | bad_save_user_regs | |
53677ef1 | 490 | bl do_not_used |
fe8c2806 WD |
491 | |
492 | #ifdef CONFIG_USE_IRQ | |
493 | ||
494 | .align 5 | |
495 | irq: | |
496 | get_irq_stack | |
497 | irq_save_user_regs | |
53677ef1 | 498 | bl do_irq |
fe8c2806 WD |
499 | irq_restore_user_regs |
500 | ||
501 | .align 5 | |
502 | fiq: | |
503 | get_fiq_stack | |
504 | /* someone ought to write a more effiction fiq_save_user_regs */ | |
505 | irq_save_user_regs | |
53677ef1 | 506 | bl do_fiq |
fe8c2806 WD |
507 | irq_restore_user_regs |
508 | ||
509 | #else | |
510 | ||
511 | .align 5 | |
512 | irq: | |
513 | get_bad_stack | |
514 | bad_save_user_regs | |
53677ef1 | 515 | bl do_irq |
fe8c2806 WD |
516 | |
517 | .align 5 | |
518 | fiq: | |
519 | get_bad_stack | |
520 | bad_save_user_regs | |
53677ef1 | 521 | bl do_fiq |
fe8c2806 WD |
522 | |
523 | #endif |