projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| fe8c2806 WD |
2 | /* |
| 3 | * armboot - Startup Code for ARM920 CPU-core | |
| 4 | * | |
| fa82f871 AA |
5 | * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> |
| 6 | * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> | |
| 792a09eb | 7 | * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> |
| fe8c2806 WD |
8 | */ |
| 9 | ||
| 25ddd1fb | 10 | #include <asm-offsets.h> |
| d678a59d | 11 | #include <common.h> |
| fe8c2806 | 12 | #include <config.h> |
| fe8c2806 | 13 | |
| fe8c2806 WD |
14 | /* |
| 15 | ************************************************************************* | |
| 16 | * | |
| 80767a6c | 17 | * Startup Code (called from the ARM reset exception vector) |
| fe8c2806 WD |
18 | * |
| 19 | * do important init only if we don't start from memory! | |
| 20 | * relocate armboot to ram | |
| 21 | * setup stack | |
| 22 | * jump to second stage | |
| 23 | * | |
| 24 | ************************************************************************* | |
| 25 | */ | |
| 26 | ||
| 41623c91 | 27 | .globl reset |
| cc7cdcbd | 28 | |
| 41623c91 | 29 | reset: |
| fe8c2806 WD |
30 | /* |
| 31 | * set the cpu to SVC32 mode | |
| 32 | */ | |
| d67cce2d | 33 | mrs r0, cpsr |
| 34 | bic r0, r0, #0x1f | |
| 35 | orr r0, r0, #0xd3 | |
| 36 | msr cpsr, r0 | |
| 80767a6c | 37 | |
| fe8c2806 WD |
38 | /* |
| 39 | * we do sys-critical inits only at reboot, | |
| 40 | * not when booting from ram! | |
| 41 | */ | |
| a2ac2b96 | 42 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) |
| fe8c2806 WD |
43 | bl cpu_init_crit |
| 44 | #endif | |
| 45 | ||
| e05e5de7 | 46 | bl _main |
| cc7cdcbd HS |
47 | |
| 48 | /*------------------------------------------------------------------------------*/ | |
| 49 | ||
| e05e5de7 AA |
50 | .globl c_runtime_cpu_setup |
| 51 | c_runtime_cpu_setup: | |
| 52 | ||
| 53 | mov pc, lr | |
| 54 | ||
| fe8c2806 WD |
55 | /* |
| 56 | ************************************************************************* | |
| 57 | * | |
| 58 | * CPU_init_critical registers | |
| 59 | * | |
| 60 | * setup important registers | |
| 61 | * setup memory timing | |
| 62 | * | |
| 63 | ************************************************************************* | |
| 64 | */ | |
| 65 | ||
| 66 | ||
| a2ac2b96 | 67 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) |
| fe8c2806 WD |
68 | cpu_init_crit: |
| 69 | /* | |
| 70 | * flush v4 I/D caches | |
| 71 | */ | |
| 72 | mov r0, #0 | |
| 73 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ | |
| 74 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ | |
| 75 | ||
| 76 | /* | |
| 77 | * disable MMU stuff and caches | |
| 78 | */ | |
| 79 | mrc p15, 0, r0, c1, c0, 0 | |
| 80 | bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) | |
| 81 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) | |
| ba10b852 | 82 | orr r0, r0, #0x00000002 @ set bit 1 (A) Align |
| fe8c2806 WD |
83 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache |
| 84 | mcr p15, 0, r0, c1, c0, 0 | |
| 85 | ||
| a2ac2b96 | 86 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) |
| fe8c2806 WD |
87 | /* |
| 88 | * before relocating, we have to setup RAM timing | |
| 89 | * because memory timing is board-dependend, you will | |
| 400558b5 | 90 | * find a lowlevel_init.S in your board directory. |
| fe8c2806 WD |
91 | */ |
| 92 | mov ip, lr | |
| d4fc6012 | 93 | |
| 400558b5 | 94 | bl lowlevel_init |
| fe8c2806 | 95 | mov lr, ip |
| b5bd0982 | 96 | #endif |
| fe8c2806 | 97 | mov pc, lr |
| a2ac2b96 | 98 | #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ |