[people/ms/u-boot.git] / arch / arm / cpu / arm926ejs / at91 / at91sam9m10g45_devices.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian.pop@leadtechdesign.com>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>

void at91_serial0_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;

	at91_set_a_periph(AT91_PIO_PORTB, 19, 1);	/* TXD0 */
	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* RXD0 */
	writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
}

void at91_serial1_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;

	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD1 */
	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);		/* RXD1 */
	writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
}

void at91_serial2_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;

	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);		/* TXD2 */
	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);		/* RXD2 */
	writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
}

void at91_serial3_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;

	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* DRXD */
	at91_set_a_periph(AT91_PIO_PORTB, 13, 1);	/* DTXD */
	writel(1 << AT91_ID_SYS, &pmc->pcer);
}

void at91_serial_hw_init(void)
{
#ifdef CONFIG_USART0
	at91_serial0_hw_init();
#endif

#ifdef CONFIG_USART1
	at91_serial1_hw_init();
#endif

#ifdef CONFIG_USART2
	at91_serial2_hw_init();
#endif

#ifdef CONFIG_USART3	/* DBGU */
	at91_serial3_hw_init();
#endif
}

#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;

	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* SPI0_MISO */
	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* SPI0_MOSI */
	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* SPI0_SPCK */

	/* Enable clock */
	writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_b_periph(AT91_PIO_PORTB, 18, 0);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_b_periph(AT91_PIO_PORTB, 19, 0);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_b_periph(AT91_PIO_PORTD, 27, 0);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTB, 18, 0);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTB, 19, 0);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
	}
}

void at91_spi1_hw_init(unsigned long cs_mask)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;

	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_MISO */
	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* SPI1_MOSI */
	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* SPI1_SPCK */

	/* Enable clock */
	writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_b_periph(AT91_PIO_PORTD, 28, 0);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_a_periph(AT91_PIO_PORTD, 18, 0);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_a_periph(AT91_PIO_PORTD, 19, 0);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTB, 17, 0);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTD, 18, 0);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTD, 19, 0);
	}

}
#endif

#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ETXCK_EREFCK */
	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERXDV */
	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ERX0 */
	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ERX1 */
	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ERXER */
	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ETXEN */
	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* ETX0 */
	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* ETX1 */
	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* EMDIO */
	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* EMDC */
#ifndef CONFIG_RMII
	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECRS */
	at91_set_b_periph(AT91_PIO_PORTA, 30, 0);	/* ECOL */
	at91_set_b_periph(AT91_PIO_PORTA, 8,  0);	/* ERX2 */
	at91_set_b_periph(AT91_PIO_PORTA, 9,  0);	/* ERX3 */
	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ERXCK */
	at91_set_b_periph(AT91_PIO_PORTA, 6,  0);	/* ETX2 */
	at91_set_b_periph(AT91_PIO_PORTA, 7,  0);	/* ETX3 */
	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ETXER */
#endif
}
#endif
Commit	Line	Data
22ee6473 SG	1	/*
	2	* (C) Copyright 2007-2008
	3	* Stelian Pop <stelian.pop@leadtechdesign.com>
	4	* Lead Tech Design <www.leadtechdesign.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <asm/arch/at91_common.h>
	27	#include <asm/arch/at91_pmc.h>
	28	#include <asm/arch/gpio.h>
	29	#include <asm/arch/io.h>
	30
	31	void at91_serial0_hw_init(void)
	32	{
0cf0b931 JS	33	at91_pmc_t pmc = (at91_pmc_t ) AT91_PMC_BASE;
0cf0b931 JS	34
7f9e8633 JS	35	at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
7f9e8633 JS	36	at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */
0cf0b931	37	writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
22ee6473 SG	38	}
	39
	40	void at91_serial1_hw_init(void)
	41	{
0cf0b931 JS	42	at91_pmc_t pmc = (at91_pmc_t ) AT91_PMC_BASE;
0cf0b931 JS	43
7f9e8633 JS	44	at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
7f9e8633 JS	45	at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */
0cf0b931	46	writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
22ee6473 SG	47	}
	48
	49	void at91_serial2_hw_init(void)
	50	{
0cf0b931 JS	51	at91_pmc_t pmc = (at91_pmc_t ) AT91_PMC_BASE;
0cf0b931 JS	52
7f9e8633 JS	53	at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
7f9e8633 JS	54	at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */
0cf0b931	55	writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
22ee6473 SG	56	}
	57
	58	void at91_serial3_hw_init(void)
	59	{
0cf0b931 JS	60	at91_pmc_t pmc = (at91_pmc_t ) AT91_PMC_BASE;
0cf0b931 JS	61
7f9e8633 JS	62	at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
7f9e8633 JS	63	at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
0cf0b931	64	writel(1 << AT91_ID_SYS, &pmc->pcer);
22ee6473 SG	65	}
	66
	67	void at91_serial_hw_init(void)
	68	{
	69	#ifdef CONFIG_USART0
	70	at91_serial0_hw_init();
	71	#endif
	72
	73	#ifdef CONFIG_USART1
	74	at91_serial1_hw_init();
	75	#endif
	76
	77	#ifdef CONFIG_USART2
	78	at91_serial2_hw_init();
	79	#endif
	80
	81	#ifdef CONFIG_USART3 /* DBGU */
	82	at91_serial3_hw_init();
	83	#endif
	84	}
	85
	86	#ifdef CONFIG_ATMEL_SPI
	87	void at91_spi0_hw_init(unsigned long cs_mask)
	88	{
0cf0b931 JS	89	at91_pmc_t pmc = (at91_pmc_t ) AT91_PMC_BASE;
0cf0b931 JS	90
7f9e8633 JS	91	at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */
	92	at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */
	93	at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */
22ee6473 SG	94
22ee6473 SG	95	/* Enable clock */
0cf0b931	96	writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
22ee6473 SG	97
22ee6473 SG	98	if (cs_mask & (1 << 0)) {
7f9e8633	99	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
22ee6473 SG	100	}
22ee6473 SG	101	if (cs_mask & (1 << 1)) {
7f9e8633	102	at91_set_b_periph(AT91_PIO_PORTB, 18, 0);
22ee6473 SG	103	}
22ee6473 SG	104	if (cs_mask & (1 << 2)) {
7f9e8633	105	at91_set_b_periph(AT91_PIO_PORTB, 19, 0);
22ee6473 SG	106	}
22ee6473 SG	107	if (cs_mask & (1 << 3)) {
7f9e8633	108	at91_set_b_periph(AT91_PIO_PORTD, 27, 0);
22ee6473 SG	109	}
22ee6473 SG	110	if (cs_mask & (1 << 4)) {
7f9e8633	111	at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
22ee6473 SG	112	}
22ee6473 SG	113	if (cs_mask & (1 << 5)) {
7f9e8633	114	at91_set_pio_output(AT91_PIO_PORTB, 18, 0);
22ee6473 SG	115	}
22ee6473 SG	116	if (cs_mask & (1 << 6)) {
7f9e8633	117	at91_set_pio_output(AT91_PIO_PORTB, 19, 0);
22ee6473 SG	118	}
22ee6473 SG	119	if (cs_mask & (1 << 7)) {
7f9e8633	120	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
22ee6473 SG	121	}
	122	}
	123
	124	void at91_spi1_hw_init(unsigned long cs_mask)
	125	{
0cf0b931 JS	126	at91_pmc_t pmc = (at91_pmc_t ) AT91_PMC_BASE;
0cf0b931 JS	127
7f9e8633 JS	128	at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */
	129	at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */
	130	at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */
22ee6473 SG	131
22ee6473 SG	132	/* Enable clock */
0cf0b931	133	writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
22ee6473 SG	134
22ee6473 SG	135	if (cs_mask & (1 << 0)) {
7f9e8633	136	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
22ee6473 SG	137	}
22ee6473 SG	138	if (cs_mask & (1 << 1)) {
7f9e8633	139	at91_set_b_periph(AT91_PIO_PORTD, 28, 0);
22ee6473 SG	140	}
22ee6473 SG	141	if (cs_mask & (1 << 2)) {
7f9e8633	142	at91_set_a_periph(AT91_PIO_PORTD, 18, 0);
22ee6473 SG	143	}
22ee6473 SG	144	if (cs_mask & (1 << 3)) {
7f9e8633	145	at91_set_a_periph(AT91_PIO_PORTD, 19, 0);
22ee6473 SG	146	}
22ee6473 SG	147	if (cs_mask & (1 << 4)) {
7f9e8633	148	at91_set_pio_output(AT91_PIO_PORTB, 17, 0);
22ee6473 SG	149	}
22ee6473 SG	150	if (cs_mask & (1 << 5)) {
7f9e8633	151	at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
22ee6473 SG	152	}
22ee6473 SG	153	if (cs_mask & (1 << 6)) {
7f9e8633	154	at91_set_pio_output(AT91_PIO_PORTD, 18, 0);
22ee6473 SG	155	}
22ee6473 SG	156	if (cs_mask & (1 << 7)) {
7f9e8633	157	at91_set_pio_output(AT91_PIO_PORTD, 19, 0);
22ee6473 SG	158	}
	159
	160	}
	161	#endif
	162
	163	#ifdef CONFIG_MACB
	164	void at91_macb_hw_init(void)
	165	{
7f9e8633 JS	166	at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */
	167	at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */
	168	at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */
	169	at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */
	170	at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */
	171	at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */
	172	at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */
	173	at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */
	174	at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */
	175	at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */
22ee6473	176	#ifndef CONFIG_RMII
7f9e8633 JS	177	at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */
	178	at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */
	179	at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */
	180	at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */
	181	at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */
	182	at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */
	183	at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */
	184	at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */
22ee6473 SG	185	#endif
	186	}
	187	#endif