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Commit | Line | Data |
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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
2f3427cc IY |
2 | /* |
3 | * (C) Copyright 2011 | |
4 | * Ilya Yanok, EmCraft Systems | |
2f3427cc | 5 | */ |
9edefc27 | 6 | #include <cpu_func.h> |
90526e9f | 7 | #include <asm/cache.h> |
2f3427cc | 8 | #include <linux/types.h> |
d678a59d | 9 | #include <common.h> |
2f3427cc | 10 | |
10015025 | 11 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
a4aaad70 | 12 | void invalidate_dcache_all(void) |
2f3427cc | 13 | { |
2694bb9b | 14 | asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); |
2f3427cc IY |
15 | } |
16 | ||
a4aaad70 | 17 | void flush_dcache_all(void) |
2f3427cc | 18 | { |
a4aaad70 MV |
19 | asm volatile( |
20 | "0:" | |
21 | "mrc p15, 0, r15, c7, c14, 3\n" | |
22 | "bne 0b\n" | |
23 | "mcr p15, 0, %0, c7, c10, 4\n" | |
2694bb9b | 24 | : : "r"(0) : "memory" |
a4aaad70 MV |
25 | ); |
26 | } | |
27 | ||
2f3427cc IY |
28 | void invalidate_dcache_range(unsigned long start, unsigned long stop) |
29 | { | |
a4aaad70 MV |
30 | if (!check_cache_range(start, stop)) |
31 | return; | |
32 | ||
33 | while (start < stop) { | |
2694bb9b | 34 | asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start)); |
a4aaad70 MV |
35 | start += CONFIG_SYS_CACHELINE_SIZE; |
36 | } | |
2f3427cc IY |
37 | } |
38 | ||
39 | void flush_dcache_range(unsigned long start, unsigned long stop) | |
40 | { | |
a4aaad70 MV |
41 | if (!check_cache_range(start, stop)) |
42 | return; | |
43 | ||
44 | while (start < stop) { | |
2694bb9b | 45 | asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start)); |
a4aaad70 MV |
46 | start += CONFIG_SYS_CACHELINE_SIZE; |
47 | } | |
48 | ||
2694bb9b | 49 | asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0)); |
a4aaad70 | 50 | } |
10015025 | 51 | #else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ |
2f3427cc IY |
52 | void invalidate_dcache_all(void) |
53 | { | |
54 | } | |
55 | ||
56 | void flush_dcache_all(void) | |
57 | { | |
58 | } | |
10015025 | 59 | #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ |
67953027 MW |
60 | |
61 | /* | |
62 | * Stub implementations for l2 cache operations | |
63 | */ | |
62e92077 | 64 | |
09e6e0b7 | 65 | __weak void l2_cache_disable(void) {} |
62e92077 | 66 | |
3a649407 | 67 | #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) |
62e92077 AA |
68 | __weak void invalidate_l2_cache(void) {} |
69 | #endif | |
93b283d4 | 70 | |
10015025 | 71 | #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) |
93b283d4 AF |
72 | /* Invalidate entire I-cache and branch predictor array */ |
73 | void invalidate_icache_all(void) | |
74 | { | |
75 | unsigned long i = 0; | |
76 | ||
77 | asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i)); | |
78 | } | |
79 | #else | |
80 | void invalidate_icache_all(void) {} | |
81 | #endif | |
82 | ||
83 | void enable_caches(void) | |
84 | { | |
10015025 | 85 | #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) |
93b283d4 AF |
86 | icache_enable(); |
87 | #endif | |
10015025 | 88 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
93b283d4 AF |
89 | dcache_enable(); |
90 | #endif | |
91 | } |