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mxs: prefix register structs with 'mxs' prefix
[people/ms/u-boot.git] / arch / arm / cpu / arm926ejs / mxs / spl_power_init.c
CommitLineData
04fe4273
MV		 1/*
2 * Freescale i.MX28 Boot PMIC init
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <config.h>
28#include <asm/io.h>
29#include <asm/arch/imx-regs.h>
30
c944a3ef 31#include "mx28_init.h"
04fe4273
MV		 32
33void mx28_power_clock2xtal(void)
34{
9c471142
OS		 35 struct mxs_clkctrl_regs *clkctrl_regs =
36 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
04fe4273
MV		 37
38 /* Set XTAL as CPU reference clock */
39 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
40 &clkctrl_regs->hw_clkctrl_clkseq_set);
41}
42
43void mx28_power_clock2pll(void)
44{
9c471142
OS		 45 struct mxs_clkctrl_regs *clkctrl_regs =
46 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
04fe4273 47
7dec1bd1
MV		 48 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
49 CLKCTRL_PLL0CTRL0_POWER);
04fe4273 50 early_delay(100);
7dec1bd1
MV		 51 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
52 CLKCTRL_CLKSEQ_BYPASS_CPU);
04fe4273
MV		 53}
54
55void mx28_power_clear_auto_restart(void)
56{
9c471142
OS		 57 struct mxs_rtc_regs *rtc_regs =
58 (struct mxs_rtc_regs *)MXS_RTC_BASE;
04fe4273
MV		 59
60 writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
61 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
62 ;
63
64 writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
65 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
66 ;
67
68 /*
69 * Due to the hardware design bug of mx28 EVK-A
70 * we need to set the AUTO_RESTART bit.
71 */
72 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
73 return;
74
75 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
76 ;
77
78 setbits_le32(&rtc_regs->hw_rtc_persistent0,
79 RTC_PERSISTENT0_AUTO_RESTART);
80 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
81 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
82 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
83 ;
84 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
85 ;
86}
87
88void mx28_power_set_linreg(void)
89{
9c471142
OS		 90 struct mxs_power_regs *power_regs =
91 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 92
93 /* Set linear regulator 25mV below switching converter */
94 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
95 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
96 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
97
98 clrsetbits_le32(&power_regs->hw_power_vddactrl,
99 POWER_VDDACTRL_LINREG_OFFSET_MASK,
100 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
101
102 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
103 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
104 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
105}
106
399d9dab
MV		 107int mx28_get_batt_volt(void)
108{
9c471142
OS		 109 struct mxs_power_regs *power_regs =
110 (struct mxs_power_regs *)MXS_POWER_BASE;
399d9dab
MV		 111 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
112 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
113 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
114 volt *= 8;
115 return volt;
116}
117
118int mx28_is_batt_ready(void)
119{
120 return (mx28_get_batt_volt() >= 3600);
121}
122
123int mx28_is_batt_good(void)
124{
9c471142
OS		 125 struct mxs_power_regs *power_regs =
126 (struct mxs_power_regs *)MXS_POWER_BASE;
399d9dab
MV		 127 uint32_t volt = mx28_get_batt_volt();
128
129 if ((volt >= 2400) && (volt <= 4300))
130 return 1;
131
132 clrsetbits_le32(&power_regs->hw_power_5vctrl,
133 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
134 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
135 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
136 &power_regs->hw_power_5vctrl_clr);
137
138 clrsetbits_le32(&power_regs->hw_power_charge,
139 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
140 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
141
142 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
143 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
144 &power_regs->hw_power_5vctrl_clr);
145
146 early_delay(500000);
147
148 volt = mx28_get_batt_volt();
149
150 if (volt >= 3500)
151 return 0;
152
153 if (volt >= 2400)
154 return 1;
155
156 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
157 &power_regs->hw_power_charge_clr);
158 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
159
160 return 0;
161}
162
04fe4273
MV		 163void mx28_power_setup_5v_detect(void)
164{
9c471142
OS		 165 struct mxs_power_regs *power_regs =
166 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 167
168 /* Start 5V detection */
169 clrsetbits_le32(&power_regs->hw_power_5vctrl,
170 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
171 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
172 POWER_5VCTRL_PWRUP_VBUS_CMPS);
173}
174
175void mx28_src_power_init(void)
176{
9c471142
OS		 177 struct mxs_power_regs *power_regs =
178 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 179
180 /* Improve efficieny and reduce transient ripple */
181 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
182 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
183
184 clrsetbits_le32(&power_regs->hw_power_dclimits,
185 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
186 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
187
188 setbits_le32(&power_regs->hw_power_battmonitor,
189 POWER_BATTMONITOR_EN_BATADJ);
190
191 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
192 clrsetbits_le32(&power_regs->hw_power_loopctrl,
193 POWER_LOOPCTRL_EN_RCSCALE_MASK,
194 POWER_LOOPCTRL_RCSCALE_THRESH |
195 POWER_LOOPCTRL_EN_RCSCALE_8X);
196
197 clrsetbits_le32(&power_regs->hw_power_minpwr,
198 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
199
200 /* 5V to battery handoff ... FIXME */
201 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
202 early_delay(30);
203 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
204}
205
206void mx28_power_init_4p2_params(void)
207{
9c471142
OS		 208 struct mxs_power_regs *power_regs =
209 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 210
211 /* Setup 4P2 parameters */
212 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
213 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
214 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
215
216 clrsetbits_le32(&power_regs->hw_power_5vctrl,
217 POWER_5VCTRL_HEADROOM_ADJ_MASK,
218 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
219
220 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
221 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
222 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
223 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
224
225 clrsetbits_le32(&power_regs->hw_power_5vctrl,
226 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
227 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
228}
229
230void mx28_enable_4p2_dcdc_input(int xfer)
231{
9c471142
OS		 232 struct mxs_power_regs *power_regs =
233 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 234 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
235 uint32_t prev_5v_brnout, prev_5v_droop;
236
237 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
238 POWER_5VCTRL_PWDN_5VBRNOUT;
239 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
240 POWER_CTRL_ENIRQ_VDD5V_DROOP;
241
242 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
243 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
244 &power_regs->hw_power_reset);
245
246 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
247
248 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
249 POWER_5VCTRL_ENABLE_DCDC)) {
250 return;
251 }
252
253 /*
254 * Recording orignal values that will be modified temporarlily
255 * to handle a chip bug. See chip errata for CQ ENGR00115837
256 */
257 tmp = readl(&power_regs->hw_power_5vctrl);
258 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
259 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
260
261 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
262
263 /*
264 * Disable mechanisms that get erroneously tripped by when setting
265 * the DCDC4P2 EN_DCDC
266 */
267 clrbits_le32(&power_regs->hw_power_5vctrl,
268 POWER_5VCTRL_VBUSVALID_5VDETECT |
269 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
270
271 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
272
273 if (xfer) {
274 setbits_le32(&power_regs->hw_power_5vctrl,
275 POWER_5VCTRL_DCDC_XFER);
276 early_delay(20);
277 clrbits_le32(&power_regs->hw_power_5vctrl,
278 POWER_5VCTRL_DCDC_XFER);
279
280 setbits_le32(&power_regs->hw_power_5vctrl,
281 POWER_5VCTRL_ENABLE_DCDC);
282 } else {
283 setbits_le32(&power_regs->hw_power_dcdc4p2,
284 POWER_DCDC4P2_ENABLE_DCDC);
285 }
286
287 early_delay(25);
288
289 clrsetbits_le32(&power_regs->hw_power_5vctrl,
290 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
291
292 if (vbus_5vdetect)
293 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
294
295 if (!pwd_bo)
296 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
297
298 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
8db9eff6
ZS		 299 writel(POWER_CTRL_VBUS_VALID_IRQ,
300 &power_regs->hw_power_ctrl_clr);
04fe4273
MV		 301
302 if (prev_5v_brnout) {
303 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
304 &power_regs->hw_power_5vctrl_set);
305 writel(POWER_RESET_UNLOCK_KEY,
306 &power_regs->hw_power_reset);
307 } else {
308 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
309 &power_regs->hw_power_5vctrl_clr);
310 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
311 &power_regs->hw_power_reset);
312 }
313
314 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
8db9eff6
ZS		 315 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
316 &power_regs->hw_power_ctrl_clr);
04fe4273
MV		 317
318 if (prev_5v_droop)
319 clrbits_le32(&power_regs->hw_power_ctrl,
320 POWER_CTRL_ENIRQ_VDD5V_DROOP);
321 else
322 setbits_le32(&power_regs->hw_power_ctrl,
323 POWER_CTRL_ENIRQ_VDD5V_DROOP);
324}
325
326void mx28_power_init_4p2_regulator(void)
327{
9c471142
OS		 328 struct mxs_power_regs *power_regs =
329 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 330 uint32_t tmp, tmp2;
331
332 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
333
334 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
335
336 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
337 &power_regs->hw_power_5vctrl_clr);
338 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
339
340 /* Power up the 4p2 rail and logic/control */
341 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
342 &power_regs->hw_power_5vctrl_clr);
343
344 /*
345 * Start charging up the 4p2 capacitor. We ramp of this charge
346 * gradually to avoid large inrush current from the 5V cable which can
347 * cause transients/problems
348 */
349 mx28_enable_4p2_dcdc_input(0);
350
351 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
352 /*
353 * If we arrived here, we were unable to recover from mx23 chip
354 * errata 5837. 4P2 is disabled and sufficient battery power is
355 * not present. Exiting to not enable DCDC power during 5V
356 * connected state.
357 */
358 clrbits_le32(&power_regs->hw_power_dcdc4p2,
359 POWER_DCDC4P2_ENABLE_DCDC);
360 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
361 &power_regs->hw_power_5vctrl_set);
362 hang();
363 }
364
365 /*
366 * Here we set the 4p2 brownout level to something very close to 4.2V.
367 * We then check the brownout status. If the brownout status is false,
368 * the voltage is already close to the target voltage of 4.2V so we
369 * can go ahead and set the 4P2 current limit to our max target limit.
370 * If the brownout status is true, we need to ramp us the current limit
371 * so that we don't cause large inrush current issues. We step up the
372 * current limit until the brownout status is false or until we've
373 * reached our maximum defined 4p2 current limit.
374 */
375 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
376 POWER_DCDC4P2_BO_MASK,
377 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
378
379 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
380 setbits_le32(&power_regs->hw_power_5vctrl,
381 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
382 } else {
383 tmp = (readl(&power_regs->hw_power_5vctrl) &
384 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
385 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
386 while (tmp < 0x3f) {
387 if (!(readl(&power_regs->hw_power_sts) &
388 POWER_STS_DCDC_4P2_BO)) {
389 tmp = readl(&power_regs->hw_power_5vctrl);
390 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
391 early_delay(100);
392 writel(tmp, &power_regs->hw_power_5vctrl);
393 break;
394 } else {
395 tmp++;
396 tmp2 = readl(&power_regs->hw_power_5vctrl);
397 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
398 tmp2 |= tmp <<
399 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
400 writel(tmp2, &power_regs->hw_power_5vctrl);
401 early_delay(100);
402 }
403 }
404 }
405
406 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
407 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
408}
409
410void mx28_power_init_dcdc_4p2_source(void)
411{
9c471142
OS		 412 struct mxs_power_regs *power_regs =
413 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 414
415 if (!(readl(&power_regs->hw_power_dcdc4p2) &
416 POWER_DCDC4P2_ENABLE_DCDC)) {
417 hang();
418 }
419
420 mx28_enable_4p2_dcdc_input(1);
421
422 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
423 clrbits_le32(&power_regs->hw_power_dcdc4p2,
424 POWER_DCDC4P2_ENABLE_DCDC);
425 writel(POWER_5VCTRL_ENABLE_DCDC,
426 &power_regs->hw_power_5vctrl_clr);
427 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
428 &power_regs->hw_power_5vctrl_set);
429 }
430}
431
432void mx28_power_enable_4p2(void)
433{
9c471142
OS		 434 struct mxs_power_regs *power_regs =
435 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 436 uint32_t vdddctrl, vddactrl, vddioctrl;
437 uint32_t tmp;
438
439 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
440 vddactrl = readl(&power_regs->hw_power_vddactrl);
441 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
442
443 setbits_le32(&power_regs->hw_power_vdddctrl,
444 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
445 POWER_VDDDCTRL_PWDN_BRNOUT);
446
447 setbits_le32(&power_regs->hw_power_vddactrl,
448 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
449 POWER_VDDACTRL_PWDN_BRNOUT);
450
451 setbits_le32(&power_regs->hw_power_vddioctrl,
452 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
453
454 mx28_power_init_4p2_params();
455 mx28_power_init_4p2_regulator();
456
457 /* Shutdown battery (none present) */
7dec1bd1
MV		 458 if (!mx28_is_batt_ready()) {
459 clrbits_le32(&power_regs->hw_power_dcdc4p2,
460 POWER_DCDC4P2_BO_MASK);
461 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
462 &power_regs->hw_power_ctrl_clr);
463 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
464 &power_regs->hw_power_ctrl_clr);
465 }
04fe4273
MV		 466
467 mx28_power_init_dcdc_4p2_source();
468
469 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
470 early_delay(20);
471 writel(vddactrl, &power_regs->hw_power_vddactrl);
472 early_delay(20);
473 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
474
475 /*
476 * Check if FET is enabled on either powerout and if so,
477 * disable load.
478 */
479 tmp = 0;
480 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
481 POWER_VDDDCTRL_DISABLE_FET);
482 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
483 POWER_VDDACTRL_DISABLE_FET);
484 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
485 POWER_VDDIOCTRL_DISABLE_FET);
486 if (tmp)
487 writel(POWER_CHARGE_ENABLE_LOAD,
488 &power_regs->hw_power_charge_clr);
489}
490
491void mx28_boot_valid_5v(void)
492{
9c471142
OS		 493 struct mxs_power_regs *power_regs =
494 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 495
496 /*
497 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
498 * disconnect event. FIXME
499 */
500 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
501 &power_regs->hw_power_5vctrl_set);
502
503 /* Configure polarity to check for 5V disconnection. */
504 writel(POWER_CTRL_POLARITY_VBUSVALID |
505 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
506 &power_regs->hw_power_ctrl_clr);
507
508 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
509 &power_regs->hw_power_ctrl_clr);
510
511 mx28_power_enable_4p2();
512}
513
514void mx28_powerdown(void)
515{
9c471142
OS		 516 struct mxs_power_regs *power_regs =
517 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 518 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
519 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
520 &power_regs->hw_power_reset);
521}
522
7dec1bd1
MV		 523void mx28_batt_boot(void)
524{
9c471142
OS		 525 struct mxs_power_regs *power_regs =
526 (struct mxs_power_regs *)MXS_POWER_BASE;
7dec1bd1
MV		 527
528 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
529 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
530
531 clrbits_le32(&power_regs->hw_power_dcdc4p2,
532 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
533 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
534
535 /* 5V to battery handoff. */
536 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
537 early_delay(30);
538 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
539
540 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
541
542 clrsetbits_le32(&power_regs->hw_power_minpwr,
543 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
544
545 mx28_power_set_linreg();
546
547 clrbits_le32(&power_regs->hw_power_vdddctrl,
548 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
549
550 clrbits_le32(&power_regs->hw_power_vddactrl,
551 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
552
553 clrbits_le32(&power_regs->hw_power_vddioctrl,
554 POWER_VDDIOCTRL_DISABLE_FET);
555
556 setbits_le32(&power_regs->hw_power_5vctrl,
557 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
558
559 setbits_le32(&power_regs->hw_power_5vctrl,
560 POWER_5VCTRL_ENABLE_DCDC);
561
562 clrsetbits_le32(&power_regs->hw_power_5vctrl,
563 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
564 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
565}
566
04fe4273
MV		 567void mx28_handle_5v_conflict(void)
568{
9c471142
OS		 569 struct mxs_power_regs *power_regs =
570 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 571 uint32_t tmp;
572
573 setbits_le32(&power_regs->hw_power_vddioctrl,
574 POWER_VDDIOCTRL_BO_OFFSET_MASK);
575
576 for (;;) {
577 tmp = readl(&power_regs->hw_power_sts);
578
579 if (tmp & POWER_STS_VDDIO_BO) {
580 mx28_powerdown();
581 break;
582 }
583
584 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
585 mx28_boot_valid_5v();
586 break;
587 } else {
588 mx28_powerdown();
589 break;
590 }
7dec1bd1
MV		 591
592 if (tmp & POWER_STS_PSWITCH_MASK) {
593 mx28_batt_boot();
594 break;
595 }
04fe4273
MV		 596 }
597}
598
04fe4273
MV		 599void mx28_5v_boot(void)
600{
9c471142
OS		 601 struct mxs_power_regs *power_regs =
602 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 603
604 /*
605 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
606 * but their implementation always returns 1 so we omit it here.
607 */
608 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
609 mx28_boot_valid_5v();
610 return;
611 }
612
613 early_delay(1000);
614 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
615 mx28_boot_valid_5v();
616 return;
617 }
618
619 mx28_handle_5v_conflict();
620}
621
622void mx28_init_batt_bo(void)
623{
9c471142
OS		 624 struct mxs_power_regs *power_regs =
625 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 626
627 /* Brownout at 3V */
628 clrsetbits_le32(&power_regs->hw_power_battmonitor,
629 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
630 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
631
632 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
633 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
634}
635
636void mx28_switch_vddd_to_dcdc_source(void)
637{
9c471142
OS		 638 struct mxs_power_regs *power_regs =
639 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 640
641 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
642 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
643 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
644
645 clrbits_le32(&power_regs->hw_power_vdddctrl,
646 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
647 POWER_VDDDCTRL_DISABLE_STEPPING);
648}
649
04fe4273
MV		 650void mx28_power_configure_power_source(void)
651{
7dec1bd1 652 int batt_ready, batt_good;
9c471142
OS		 653 struct mxs_power_regs *power_regs =
654 (struct mxs_power_regs *)MXS_POWER_BASE;
655 struct mxs_lradc_regs *lradc_regs =
656 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
7dec1bd1 657
04fe4273
MV		 658 mx28_src_power_init();
659
7dec1bd1
MV		 660 batt_ready = mx28_is_batt_ready();
661
662 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
663 batt_good = mx28_is_batt_good();
664 if (batt_ready) {
665 /* 5V source detected, good battery detected. */
666 mx28_batt_boot();
667 } else {
668 if (batt_good) {
669 /* 5V source detected, low battery detceted. */
670 } else {
671 /* 5V source detected, bad battery detected. */
672 writel(LRADC_CONVERSION_AUTOMATIC,
673 &lradc_regs->hw_lradc_conversion_clr);
674 clrbits_le32(&power_regs->hw_power_battmonitor,
675 POWER_BATTMONITOR_BATT_VAL_MASK);
676 }
677 mx28_5v_boot();
678 }
679 } else {
680 /* 5V not detected, booting from battery. */
681 mx28_batt_boot();
682 }
683
04fe4273
MV		 684 mx28_power_clock2pll();
685
686 mx28_init_batt_bo();
7dec1bd1 687
04fe4273
MV		 688 mx28_switch_vddd_to_dcdc_source();
689}
690
691void mx28_enable_output_rail_protection(void)
692{
9c471142
OS		 693 struct mxs_power_regs *power_regs =
694 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 695
696 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
697 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
698
699 setbits_le32(&power_regs->hw_power_vdddctrl,
700 POWER_VDDDCTRL_PWDN_BRNOUT);
701
702 setbits_le32(&power_regs->hw_power_vddactrl,
703 POWER_VDDACTRL_PWDN_BRNOUT);
704
705 setbits_le32(&power_regs->hw_power_vddioctrl,
706 POWER_VDDIOCTRL_PWDN_BRNOUT);
707}
708
709int mx28_get_vddio_power_source_off(void)
710{
9c471142
OS		 711 struct mxs_power_regs *power_regs =
712 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 713 uint32_t tmp;
714
715 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
716 tmp = readl(&power_regs->hw_power_vddioctrl);
717 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
718 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
719 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
720 return 1;
721 }
722 }
723
724 if (!(readl(&power_regs->hw_power_5vctrl) &
725 POWER_5VCTRL_ENABLE_DCDC)) {
726 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
727 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
728 return 1;
729 }
730 }
731 }
732
733 return 0;
734
735}
736
737int mx28_get_vddd_power_source_off(void)
738{
9c471142
OS		 739 struct mxs_power_regs *power_regs =
740 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 741 uint32_t tmp;
742
743 tmp = readl(&power_regs->hw_power_vdddctrl);
744 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
745 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
746 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
747 return 1;
748 }
749 }
750
751 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
752 if (!(readl(&power_regs->hw_power_5vctrl) &
753 POWER_5VCTRL_ENABLE_DCDC)) {
754 return 1;
755 }
756 }
757
758 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
759 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
760 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
761 return 1;
762 }
763 }
764
765 return 0;
766}
767
768void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
769{
9c471142
OS		 770 struct mxs_power_regs *power_regs =
771 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 772 uint32_t cur_target, diff, bo_int = 0;
773 uint32_t powered_by_linreg = 0;
774
775 new_brownout = new_target - new_brownout;
776
777 cur_target = readl(&power_regs->hw_power_vddioctrl);
778 cur_target &= POWER_VDDIOCTRL_TRG_MASK;
779 cur_target *= 50; /* 50 mV step*/
780 cur_target += 2800; /* 2800 mV lowest */
781
782 powered_by_linreg = mx28_get_vddio_power_source_off();
783 if (new_target > cur_target) {
784
785 if (powered_by_linreg) {
786 bo_int = readl(&power_regs->hw_power_vddioctrl);
787 clrbits_le32(&power_regs->hw_power_vddioctrl,
788 POWER_CTRL_ENIRQ_VDDIO_BO);
789 }
790
791 setbits_le32(&power_regs->hw_power_vddioctrl,
792 POWER_VDDIOCTRL_BO_OFFSET_MASK);
793 do {
794 if (new_target - cur_target > 100)
795 diff = cur_target + 100;
796 else
797 diff = new_target;
798
799 diff -= 2800;
800 diff /= 50;
801
802 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
803 POWER_VDDIOCTRL_TRG_MASK, diff);
804
534dbd12
MV		 805 if (powered_by_linreg ||
806 (readl(&power_regs->hw_power_sts) &
807 POWER_STS_VDD5V_GT_VDDIO))
a8930033 808 early_delay(500);
04fe4273
MV		 809 else {
810 while (!(readl(&power_regs->hw_power_sts) &
811 POWER_STS_DC_OK))
812 ;
813
814 }
815
816 cur_target = readl(&power_regs->hw_power_vddioctrl);
817 cur_target &= POWER_VDDIOCTRL_TRG_MASK;
818 cur_target *= 50; /* 50 mV step*/
819 cur_target += 2800; /* 2800 mV lowest */
820 } while (new_target > cur_target);
821
822 if (powered_by_linreg) {
823 writel(POWER_CTRL_VDDIO_BO_IRQ,
824 &power_regs->hw_power_ctrl_clr);
825 if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
826 setbits_le32(&power_regs->hw_power_vddioctrl,
827 POWER_CTRL_ENIRQ_VDDIO_BO);
828 }
829 } else {
830 do {
831 if (cur_target - new_target > 100)
832 diff = cur_target - 100;
833 else
834 diff = new_target;
835
836 diff -= 2800;
837 diff /= 50;
838
839 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
840 POWER_VDDIOCTRL_TRG_MASK, diff);
841
534dbd12
MV		 842 if (powered_by_linreg ||
843 (readl(&power_regs->hw_power_sts) &
844 POWER_STS_VDD5V_GT_VDDIO))
a8930033 845 early_delay(500);
04fe4273
MV		 846 else {
847 while (!(readl(&power_regs->hw_power_sts) &
848 POWER_STS_DC_OK))
849 ;
850
851 }
852
853 cur_target = readl(&power_regs->hw_power_vddioctrl);
854 cur_target &= POWER_VDDIOCTRL_TRG_MASK;
855 cur_target *= 50; /* 50 mV step*/
856 cur_target += 2800; /* 2800 mV lowest */
857 } while (new_target < cur_target);
858 }
859
860 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
861 POWER_VDDDCTRL_BO_OFFSET_MASK,
862 new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
863}
864
865void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
866{
9c471142
OS		 867 struct mxs_power_regs *power_regs =
868 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 869 uint32_t cur_target, diff, bo_int = 0;
870 uint32_t powered_by_linreg = 0;
871
872 new_brownout = new_target - new_brownout;
873
874 cur_target = readl(&power_regs->hw_power_vdddctrl);
875 cur_target &= POWER_VDDDCTRL_TRG_MASK;
876 cur_target *= 25; /* 25 mV step*/
877 cur_target += 800; /* 800 mV lowest */
878
879 powered_by_linreg = mx28_get_vddd_power_source_off();
880 if (new_target > cur_target) {
881 if (powered_by_linreg) {
882 bo_int = readl(&power_regs->hw_power_vdddctrl);
883 clrbits_le32(&power_regs->hw_power_vdddctrl,
884 POWER_CTRL_ENIRQ_VDDD_BO);
885 }
886
887 setbits_le32(&power_regs->hw_power_vdddctrl,
888 POWER_VDDDCTRL_BO_OFFSET_MASK);
889
890 do {
891 if (new_target - cur_target > 100)
892 diff = cur_target + 100;
893 else
894 diff = new_target;
895
896 diff -= 800;
897 diff /= 25;
898
899 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
900 POWER_VDDDCTRL_TRG_MASK, diff);
901
534dbd12
MV		 902 if (powered_by_linreg ||
903 (readl(&power_regs->hw_power_sts) &
904 POWER_STS_VDD5V_GT_VDDIO))
a8930033 905 early_delay(500);
04fe4273
MV		 906 else {
907 while (!(readl(&power_regs->hw_power_sts) &
908 POWER_STS_DC_OK))
909 ;
910
911 }
912
913 cur_target = readl(&power_regs->hw_power_vdddctrl);
914 cur_target &= POWER_VDDDCTRL_TRG_MASK;
915 cur_target *= 25; /* 25 mV step*/
916 cur_target += 800; /* 800 mV lowest */
917 } while (new_target > cur_target);
918
919 if (powered_by_linreg) {
920 writel(POWER_CTRL_VDDD_BO_IRQ,
921 &power_regs->hw_power_ctrl_clr);
922 if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
923 setbits_le32(&power_regs->hw_power_vdddctrl,
924 POWER_CTRL_ENIRQ_VDDD_BO);
925 }
926 } else {
927 do {
928 if (cur_target - new_target > 100)
929 diff = cur_target - 100;
930 else
931 diff = new_target;
932
933 diff -= 800;
934 diff /= 25;
935
936 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
937 POWER_VDDDCTRL_TRG_MASK, diff);
938
534dbd12
MV		 939 if (powered_by_linreg ||
940 (readl(&power_regs->hw_power_sts) &
941 POWER_STS_VDD5V_GT_VDDIO))
a8930033 942 early_delay(500);
04fe4273
MV		 943 else {
944 while (!(readl(&power_regs->hw_power_sts) &
945 POWER_STS_DC_OK))
946 ;
947
948 }
949
950 cur_target = readl(&power_regs->hw_power_vdddctrl);
951 cur_target &= POWER_VDDDCTRL_TRG_MASK;
952 cur_target *= 25; /* 25 mV step*/
953 cur_target += 800; /* 800 mV lowest */
954 } while (new_target < cur_target);
955 }
956
957 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
958 POWER_VDDDCTRL_BO_OFFSET_MASK,
959 new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
960}
961
3f3255c3
MV		 962void mx28_setup_batt_detect(void)
963{
964 mx28_lradc_init();
965 mx28_lradc_enable_batt_measurement();
966 early_delay(10);
967}
968
04fe4273
MV		 969void mx28_power_init(void)
970{
9c471142
OS		 971 struct mxs_power_regs *power_regs =
972 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 973
974 mx28_power_clock2xtal();
975 mx28_power_clear_auto_restart();
976 mx28_power_set_linreg();
977 mx28_power_setup_5v_detect();
3f3255c3
MV		 978
979 mx28_setup_batt_detect();
980
04fe4273
MV		 981 mx28_power_configure_power_source();
982 mx28_enable_output_rail_protection();
983
984 mx28_power_set_vddio(3300, 3150);
985
986 mx28_power_set_vddd(1350, 1200);
987
988 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
989 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
990 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
991 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
992
993 writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
994
995 early_delay(1000);
996}
997
998#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
999void mx28_power_wait_pswitch(void)
1000{
9c471142
OS		 1001 struct mxs_power_regs *power_regs =
1002 (struct mxs_power_regs *)MXS_POWER_BASE;
04fe4273
MV		 1003
1004 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1005 ;
1006}
1007#endif
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