[people/ms/u-boot.git] / arch / arm / cpu / arm926ejs / orion5x / lowlevel_init.S

/*
 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
 *
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include "asm/arch/orion5x.h"

/*
 * Configuration values for SDRAM access setup
 */

#define SDRAM_CONFIG			0x3148400
#define SDRAM_MODE			0x62
#define SDRAM_CONTROL			0x4041000
#define SDRAM_TIME_CTRL_LOW		0x11602220
#define SDRAM_TIME_CTRL_HI		0x40c
#define SDRAM_OPEN_PAGE_EN		0x0
/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
#define SDRAM_BANK0_SIZE		0x3ff0001
#define SDRAM_ADDR_CTRL			0x10

#define SDRAM_OP_NOP			0x05
#define SDRAM_OP_SETMODE		0x03

#define SDRAM_PAD_CTRL_WR_EN		0x80000000
#define SDRAM_PAD_CTRL_TUNE_EN		0x00010000
#define SDRAM_PAD_CTRL_DRVN_MASK	0x0000003f
#define SDRAM_PAD_CTRL_DRVP_MASK	0x00000fc0

/*
 * For Guideline MEM-3 - Drive Strength value
 */

#define DDR1_PAD_STRENGTH_DEFAULT	0x00001000
#define SDRAM_PAD_CTRL_DRV_STR_MASK	0x00003000

/*
 * For Guideline MEM-4 - DQS Reference Delay Tuning
 */

#define MSAR_ARMDDRCLCK_MASK		0x000000f0
#define MSAR_ARMDDRCLCK_H_MASK		0x00000100

#define MSAR_ARMDDRCLCK_333_167		0x00000000
#define MSAR_ARMDDRCLCK_500_167		0x00000030
#define MSAR_ARMDDRCLCK_667_167		0x00000060
#define MSAR_ARMDDRCLCK_400_200_1	0x000001E0
#define MSAR_ARMDDRCLCK_400_200		0x00000010
#define MSAR_ARMDDRCLCK_600_200		0x00000050
#define MSAR_ARMDDRCLCK_800_200		0x00000070

#define FTDLL_DDR1_166MHZ		0x0047F001

#define FTDLL_DDR1_200MHZ		0x0044D001

/*
 * Low-level init happens right after start.S has switched to SVC32,
 * flushed and disabled caches and disabled MMU. We're still running
 * from the boot chip select, so the first thing we should do is set
 * up RAM for us to relocate into.
 */

.globl lowlevel_init

lowlevel_init:

	/* Use 'r4 as the base for internal register accesses */
	ldr	r4, =ORION5X_REGS_PHY_BASE

	/* move internal registers from the default 0xD0000000
	 * to their intended location, defined by SoC */
	ldr	r3, =0xD0000000
	add	r3, r3, #0x20000
	str	r4, [r3, #0x80]

	/* Use R3 as the base for DRAM registers */
	add	r3, r4, #0x01000

	/*DDR SDRAM Initialization Control */
	ldr	r6, =0x00000001
	str	r6, [r3, #0x480]

	/* Use R3 as the base for PCI registers */
	add	r3, r4, #0x31000

	/* Disable arbiter */
	ldr	r6, =0x00000030
	str	r6, [r3, #0xd00]

	/* Use R3 as the base for DRAM registers */
	add	r3, r4, #0x01000

	/* set all dram windows to 0 */
	mov	r6, #0
	str	r6, [r3, #0x504]
	str	r6, [r3, #0x50C]
	str	r6, [r3, #0x514]
	str	r6, [r3, #0x51C]

	/* 1) Configure SDRAM  */
	ldr	r6, =SDRAM_CONFIG
	str	r6, [r3, #0x400]

	/* 2) Set SDRAM Control reg */
	ldr	r6, =SDRAM_CONTROL
	str	r6, [r3, #0x404]

	/* 3) Write SDRAM address control register */
	ldr	r6, =SDRAM_ADDR_CTRL
	str	r6, [r3, #0x410]

	/* 4) Write SDRAM bank 0 size register */
	ldr	r6, =SDRAM_BANK0_SIZE
	str	r6, [r3, #0x504]
	/* keep other banks disabled */

	/* 5) Write SDRAM open pages control register */
	ldr	r6, =SDRAM_OPEN_PAGE_EN
	str	r6, [r3, #0x414]

	/* 6) Write SDRAM timing Low register */
	ldr	r6, =SDRAM_TIME_CTRL_LOW
	str	r6, [r3, #0x408]

	/* 7) Write SDRAM timing High register */
	ldr	r6, =SDRAM_TIME_CTRL_HI
	str	r6, [r3, #0x40C]

	/* 8) Write SDRAM mode register */
	/* The CPU must not attempt to change the SDRAM Mode register setting */
	/* prior to DRAM controller completion of the DRAM initialization     */
	/* sequence. To guarantee this restriction, it is recommended that    */
	/* the CPU sets the SDRAM Operation register to NOP command, performs */
	/* read polling until the register is back in Normal operation value, */
	/* and then sets SDRAM Mode register to its new value.		      */

	/* 8.1 write 'nop' to SDRAM operation */
	ldr	r6, =SDRAM_OP_NOP
	str	r6, [r3, #0x418]

	/* 8.2 poll SDRAM operation until back in 'normal' mode.  */
1:
	ldr	r6, [r3, #0x418]
	cmp	r6, #0
	bne	1b

	/* 8.3 Now its safe to write new value to SDRAM Mode register	      */
	ldr	r6, =SDRAM_MODE
	str	r6, [r3, #0x41C]

	/* 8.4 Set new mode */
	ldr	r6, =SDRAM_OP_SETMODE
	str	r6, [r3, #0x418]

	/* 8.5 poll SDRAM operation until back in 'normal' mode.  */
2:
	ldr	r6, [r3, #0x418]
	cmp	r6, #0
	bne	2b

	/* DDR SDRAM Address/Control Pads Calibration */
	ldr	r6, [r3, #0x4C0]

	/* Set Bit [31] to make the register writable			*/
	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
	str	r6, [r3, #0x4C0]

	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK

	/* Get the final N locked value of driving strength [22:17]	*/
	mov	r1, r6
	mov	r1, r1, LSL #9
	mov	r1, r1, LSR #26	 /* r1[5:0]<DrvN>  = r3[22:17]<LockN>	*/
	orr	r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN>	*/

	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
	orr	r6, r6, r1
	str	r6, [r3, #0x4C0]

	/* DDR SDRAM Data Pads Calibration				*/
	ldr	r6, [r3, #0x4C4]

	/* Set Bit [31] to make the register writable			*/
	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
	str	r6, [r3, #0x4C4]

	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK

	/* Get the final N locked value of driving strength [22:17]	*/
	mov	r1, r6
	mov	r1, r1, LSL #9
	mov	r1, r1, LSR #26
	orr	r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>	*/

	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
	orr	r6, r6, r1

	str	r6, [r3, #0x4C4]

	/* Implement Guideline (GL# MEM-3) Drive Strength Value		*/
	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/

	ldr	r1, =DDR1_PAD_STRENGTH_DEFAULT

	/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
	ldr	r6, [r3, #0x4C0]
	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
	str	r6, [r3, #0x4C0]

	/* Correct strength and disable writes again */
	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
	orr	r6, r6, r1
	str	r6, [r3, #0x4C0]

	/* Enable writes to DDR SDRAM Data Pads Calibration register */
	ldr	r6, [r3, #0x4C4]
	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
	str	r6, [r3, #0x4C4]

	/* Correct strength and disable writes again */
	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
	orr	r6, r6, r1
	str	r6, [r3, #0x4C4]

	/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning	*/
	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/

	/* Get the "sample on reset" register for the DDR frequancy	*/
	ldr	r3, =0x10000
	ldr	r6, [r3, #0x010]
	ldr	r1, =MSAR_ARMDDRCLCK_MASK
	and	r1, r6, r1

	ldr	r6, =FTDLL_DDR1_166MHZ
	cmp	r1, #MSAR_ARMDDRCLCK_333_167
	beq	3f
	cmp	r1, #MSAR_ARMDDRCLCK_500_167
	beq	3f
	cmp	r1, #MSAR_ARMDDRCLCK_667_167
	beq	3f

	ldr	r6, =FTDLL_DDR1_200MHZ
	cmp	r1, #MSAR_ARMDDRCLCK_400_200_1
	beq	3f
	cmp	r1, #MSAR_ARMDDRCLCK_400_200
	beq	3f
	cmp	r1, #MSAR_ARMDDRCLCK_600_200
	beq	3f
	cmp	r1, #MSAR_ARMDDRCLCK_800_200
	beq	3f

	ldr	r6, =0

3:
	/* Use R3 as the base for DRAM registers */
	add	r3, r4, #0x01000

	ldr	r2, [r3, #0x484]
	orr	r2, r2, r6
	str	r2, [r3, #0x484]

	/* Return to U-boot via saved link register */
	mov	pc, lr
Commit	Line	Data
0c61e6f9	1	/*
57b4bce9	2	* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
0c61e6f9 AA	3	*
	4	* (C) Copyright 2009
	5	* Marvell Semiconductor <www.marvell.com>
	6	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
0c61e6f9 AA	9	*/
	10
	11	#include <config.h>
	12	#include "asm/arch/orion5x.h"
	13
	14	/*
	15	* Configuration values for SDRAM access setup
	16	*/
	17
	18	#define SDRAM_CONFIG 0x3148400
	19	#define SDRAM_MODE 0x62
	20	#define SDRAM_CONTROL 0x4041000
	21	#define SDRAM_TIME_CTRL_LOW 0x11602220
	22	#define SDRAM_TIME_CTRL_HI 0x40c
	23	#define SDRAM_OPEN_PAGE_EN 0x0
	24	/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
	25	#define SDRAM_BANK0_SIZE 0x3ff0001
	26	#define SDRAM_ADDR_CTRL 0x10
	27
	28	#define SDRAM_OP_NOP 0x05
	29	#define SDRAM_OP_SETMODE 0x03
	30
	31	#define SDRAM_PAD_CTRL_WR_EN 0x80000000
	32	#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
	33	#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
	34	#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
	35
	36	/*
	37	* For Guideline MEM-3 - Drive Strength value
	38	*/
	39
	40	#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
	41	#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
	42
	43	/*
	44	* For Guideline MEM-4 - DQS Reference Delay Tuning
	45	*/
	46
	47	#define MSAR_ARMDDRCLCK_MASK 0x000000f0
	48	#define MSAR_ARMDDRCLCK_H_MASK 0x00000100
	49
	50	#define MSAR_ARMDDRCLCK_333_167 0x00000000
	51	#define MSAR_ARMDDRCLCK_500_167 0x00000030
	52	#define MSAR_ARMDDRCLCK_667_167 0x00000060
	53	#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
	54	#define MSAR_ARMDDRCLCK_400_200 0x00000010
	55	#define MSAR_ARMDDRCLCK_600_200 0x00000050
	56	#define MSAR_ARMDDRCLCK_800_200 0x00000070
	57
	58	#define FTDLL_DDR1_166MHZ 0x0047F001
	59
	60	#define FTDLL_DDR1_200MHZ 0x0044D001
	61
	62	/*
	63	* Low-level init happens right after start.S has switched to SVC32,
	64	* flushed and disabled caches and disabled MMU. We're still running
	65	* from the boot chip select, so the first thing we should do is set
	66	* up RAM for us to relocate into.
	67	*/
	68
	69	.globl lowlevel_init
	70
	71	lowlevel_init:
	72
73	/* Use 'r4 as the base for internal register accesses */
482126e2	74	ldr r4, =ORION5X_REGS_PHY_BASE
0c61e6f9 AA	75
	76	/* move internal registers from the default 0xD0000000
	77	* to their intended location, defined by SoC */
	78	ldr r3, =0xD0000000
	79	add r3, r3, #0x20000
482126e2	80	str r4, [r3, #0x80]
0c61e6f9 AA	81
0c61e6f9 AA	82	/* Use R3 as the base for DRAM registers */
482126e2	83	add r3, r4, #0x01000
0c61e6f9 AA	84
	85	/DDR SDRAM Initialization Control /
	86	ldr r6, =0x00000001
	87	str r6, [r3, #0x480]
	88
	89	/* Use R3 as the base for PCI registers */
482126e2	90	add r3, r4, #0x31000
0c61e6f9 AA	91
	92	/* Disable arbiter */
	93	ldr r6, =0x00000030
	94	str r6, [r3, #0xd00]
	95
	96	/* Use R3 as the base for DRAM registers */
482126e2	97	add r3, r4, #0x01000
0c61e6f9 AA	98
	99	/* set all dram windows to 0 */
	100	mov r6, #0
	101	str r6, [r3, #0x504]
	102	str r6, [r3, #0x50C]
	103	str r6, [r3, #0x514]
	104	str r6, [r3, #0x51C]
	105
	106	/* 1) Configure SDRAM */
	107	ldr r6, =SDRAM_CONFIG
	108	str r6, [r3, #0x400]
	109
	110	/* 2) Set SDRAM Control reg */
	111	ldr r6, =SDRAM_CONTROL
	112	str r6, [r3, #0x404]
	113
482126e2	114	/* 3) Write SDRAM address control register */
0c61e6f9 AA	115	ldr r6, =SDRAM_ADDR_CTRL
	116	str r6, [r3, #0x410]
	117
482126e2	118	/* 4) Write SDRAM bank 0 size register */
0c61e6f9 AA	119	ldr r6, =SDRAM_BANK0_SIZE
	120	str r6, [r3, #0x504]
	121	/* keep other banks disabled */
	122
482126e2	123	/* 5) Write SDRAM open pages control register */
0c61e6f9 AA	124	ldr r6, =SDRAM_OPEN_PAGE_EN
	125	str r6, [r3, #0x414]
	126
482126e2	127	/* 6) Write SDRAM timing Low register */
0c61e6f9 AA	128	ldr r6, =SDRAM_TIME_CTRL_LOW
	129	str r6, [r3, #0x408]
	130
482126e2	131	/* 7) Write SDRAM timing High register */
0c61e6f9 AA	132	ldr r6, =SDRAM_TIME_CTRL_HI
	133	str r6, [r3, #0x40C]
	134
482126e2 WD	135	/* 8) Write SDRAM mode register */
	136	/* The CPU must not attempt to change the SDRAM Mode register setting */
	137	/* prior to DRAM controller completion of the DRAM initialization */
	138	/* sequence. To guarantee this restriction, it is recommended that */
	139	/* the CPU sets the SDRAM Operation register to NOP command, performs */
	140	/* read polling until the register is back in Normal operation value, */
	141	/* and then sets SDRAM Mode register to its new value. */
0c61e6f9 AA	142
0c61e6f9 AA	143	/* 8.1 write 'nop' to SDRAM operation */
482126e2	144	ldr r6, =SDRAM_OP_NOP
0c61e6f9 AA	145	str r6, [r3, #0x418]
0c61e6f9 AA	146
482126e2	147	/* 8.2 poll SDRAM operation until back in 'normal' mode. */
0c61e6f9 AA	148	1:
	149	ldr r6, [r3, #0x418]
	150	cmp r6, #0
	151	bne 1b
	152
482126e2	153	/* 8.3 Now its safe to write new value to SDRAM Mode register */
0c61e6f9 AA	154	ldr r6, =SDRAM_MODE
	155	str r6, [r3, #0x41C]
	156
482126e2 WD	157	/* 8.4 Set new mode */
482126e2 WD	158	ldr r6, =SDRAM_OP_SETMODE
0c61e6f9 AA	159	str r6, [r3, #0x418]
0c61e6f9 AA	160
482126e2	161	/* 8.5 poll SDRAM operation until back in 'normal' mode. */
0c61e6f9 AA	162	2:
	163	ldr r6, [r3, #0x418]
	164	cmp r6, #0
	165	bne 2b
	166
482126e2	167	/* DDR SDRAM Address/Control Pads Calibration */
0c61e6f9 AA	168	ldr r6, [r3, #0x4C0]
0c61e6f9 AA	169
482126e2	170	/* Set Bit [31] to make the register writable */
0c61e6f9 AA	171	orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
	172	str r6, [r3, #0x4C0]
	173
	174	bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
	175	bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
	176	bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
	177	bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
	178
482126e2 WD	179	/* Get the final N locked value of driving strength [22:17] */
	180	mov r1, r6
	181	mov r1, r1, LSL #9
	182	mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
	183	orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
0c61e6f9	184
482126e2	185	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
0c61e6f9 AA	186	orr r6, r6, r1
	187	str r6, [r3, #0x4C0]
	188
482126e2	189	/* DDR SDRAM Data Pads Calibration */
0c61e6f9 AA	190	ldr r6, [r3, #0x4C4]
0c61e6f9 AA	191
482126e2	192	/* Set Bit [31] to make the register writable */
0c61e6f9 AA	193	orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
	194	str r6, [r3, #0x4C4]
	195
	196	bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
	197	bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
	198	bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
	199	bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
	200
482126e2 WD	201	/* Get the final N locked value of driving strength [22:17] */
	202	mov r1, r6
	203	mov r1, r1, LSL #9
	204	mov r1, r1, LSR #26
	205	orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
0c61e6f9	206
482126e2	207	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
0c61e6f9 AA	208	orr r6, r6, r1
	209
	210	str r6, [r3, #0x4C4]
	211
482126e2 WD	212	/* Implement Guideline (GL# MEM-3) Drive Strength Value */
482126e2 WD	213	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
0c61e6f9	214
482126e2	215	ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
0c61e6f9 AA	216
	217	/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
	218	ldr r6, [r3, #0x4C0]
	219	orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
	220	str r6, [r3, #0x4C0]
	221
	222	/* Correct strength and disable writes again */
	223	bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
	224	bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
	225	orr r6, r6, r1
	226	str r6, [r3, #0x4C0]
	227
	228	/* Enable writes to DDR SDRAM Data Pads Calibration register */
	229	ldr r6, [r3, #0x4C4]
	230	orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
	231	str r6, [r3, #0x4C4]
	232
	233	/* Correct strength and disable writes again */
	234	bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
	235	bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
	236	orr r6, r6, r1
	237	str r6, [r3, #0x4C4]
	238
482126e2 WD	239	/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
482126e2 WD	240	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
0c61e6f9	241
482126e2	242	/* Get the "sample on reset" register for the DDR frequancy */
0c61e6f9	243	ldr r3, =0x10000
482126e2 WD	244	ldr r6, [r3, #0x010]
	245	ldr r1, =MSAR_ARMDDRCLCK_MASK
	246	and r1, r6, r1
	247
	248	ldr r6, =FTDLL_DDR1_166MHZ
	249	cmp r1, #MSAR_ARMDDRCLCK_333_167
	250	beq 3f
	251	cmp r1, #MSAR_ARMDDRCLCK_500_167
	252	beq 3f
	253	cmp r1, #MSAR_ARMDDRCLCK_667_167
	254	beq 3f
	255
	256	ldr r6, =FTDLL_DDR1_200MHZ
	257	cmp r1, #MSAR_ARMDDRCLCK_400_200_1
	258	beq 3f
	259	cmp r1, #MSAR_ARMDDRCLCK_400_200
	260	beq 3f
	261	cmp r1, #MSAR_ARMDDRCLCK_600_200
	262	beq 3f
	263	cmp r1, #MSAR_ARMDDRCLCK_800_200
	264	beq 3f
	265
	266	ldr r6, =0
0c61e6f9 AA	267
	268	3:
	269	/* Use R3 as the base for DRAM registers */
482126e2	270	add r3, r4, #0x01000
0c61e6f9 AA	271
	272	ldr r2, [r3, #0x484]
	273	orr r2, r2, r6
	274	str r2, [r3, #0x484]
	275
	276	/* Return to U-boot via saved link register */
482126e2	277	mov pc, lr