[people/ms/u-boot.git] / arch / arm / cpu / armv7 / am33xx / ddr.c

/*
 * DDR Configuration for AM33xx devices.
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>

/**
 * Base address for EMIF instances
 */
static struct emif_reg_struct *emif_reg[2] = {
				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};

/**
 * Base addresses for DDR PHY cmd/data regs
 */
static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};

static struct ddr_data_regs *ddr_data_reg[2] = {
				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};

/**
 * Base address for ddr io control instances
 */
static struct ddr_cmdtctrl *ioctrl_reg = {
			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};

static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
{
	u32 mr;

	mr_addr |= cs << EMIF_REG_CS_SHIFT;
	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);

	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
	if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
	    ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
	    ((mr & 0xff000000) >> 24) == (mr & 0xff))
		return mr & 0xff;
	else
		return mr;
}

static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
{
	mr_addr |= cs << EMIF_REG_CS_SHIFT;
	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
}

static void configure_mr(int nr, u32 cs)
{
	u32 mr_addr;

	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
		;
	set_mr(nr, cs, LPDDR2_MR10, 0x56);

	set_mr(nr, cs, LPDDR2_MR1, 0x43);
	set_mr(nr, cs, LPDDR2_MR2, 0x2);

	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
	set_mr(nr, cs, mr_addr, 0x2);
}

/*
 * Configure EMIF4D5 registers and MR registers For details about these magic
 * values please see the EMIF registers section of the TRM.
 */
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);

	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
	writel(regs->emif_rd_wr_lvl_rmp_win,
	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
	writel(regs->emif_rd_wr_lvl_rmp_ctl,
	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
	writel(regs->emif_rd_wr_exec_thresh,
	       &emif_reg[nr]->emif_rd_wr_exec_thresh);

	/*
	 * for most SOCs these registers won't need to be changed so only
	 * write to these registers if someone explicitly has set the
	 * register's value.
	 */
	if(regs->emif_cos_config) {
		writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
		writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
		writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
		writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
	}

	/*
	 * Sequence to ensure that the PHY is in a known state prior to
	 * startting hardware leveling.  Also acts as to latch some state from
	 * the EMIF into the PHY.
	 */
	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);

	clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
			EMIF_REG_INITREF_DIS_MASK);

	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);

	/* Perform hardware leveling for DDR3 */
	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
		udelay(1000);
		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);

		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);

		/* Enable read leveling */
		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);

		/*
		 * Enable full read and write leveling.  Wait for read and write
		 * leveling bit to clear RDWRLVLFULL_START bit 31
		 */
		while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
		      != 0)
			;

		/* Check the timeout register to see if leveling is complete */
		if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
			puts("DDR3 H/W leveling incomplete with errors\n");

	} else {
		/* DDR2 */
		configure_mr(nr, 0);
		configure_mr(nr, 1);
	}
}

/**
 * Configure SDRAM
 */
void config_sdram(const struct emif_regs *regs, int nr)
{
	if (regs->zq_config) {
		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);

		/* Trigger initialization */
		writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
		/* Wait 1ms because of L3 timeout error */
		udelay(1000);

		/* Write proper sdram_ref_cref_ctrl value */
		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	}
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
}

/**
 * Set SDRAM timings
 */
void set_sdram_timings(const struct emif_regs *regs, int nr)
{
	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}

/*
 * Configure EXT PHY registers for software leveling
 */
static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
{
	u32 *ext_phy_ctrl_base = 0;
	u32 *emif_ext_phy_ctrl_base = 0;
	__maybe_unused const u32 *ext_phy_ctrl_const_regs;
	u32 i = 0;
	__maybe_unused u32 size;

	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
	emif_ext_phy_ctrl_base =
			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);

	/* Configure external phy control timing registers */
	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
		/* Update shadow registers */
		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
	}

#ifdef CONFIG_AM43XX
	/*
	 * External phy 6-24 registers do not change with ddr frequency.
	 * These only need to be set on DDR2 on AM43xx.
	 */
	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);

	if (!size)
		return;

	for (i = 0; i < size; i++) {
		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
		/* Update shadow registers */
		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
	}
#endif
}

/*
 * Configure EXT PHY registers for hardware leveling
 */
static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
{
	/*
	 * Enable hardware leveling on the EMIF.  For details about these
	 * magic values please see the EMIF registers section of the TRM.
	 */
	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);

	/*
	 * Sequence to ensure that the PHY is again in a known state after
	 * hardware leveling.
	 */
	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
}

/**
 * Configure DDR PHY
 */
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
	/*
	 * Disable initialization and refreshes for now until we
	 * finish programming EMIF regs.
	 * Also set time between rising edge of DDR_RESET to rising
	 * edge of DDR_CKE to > 500us per memory spec.
	 */
#ifndef CONFIG_AM43XX
	setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
		     EMIF_REG_INITREF_DIS_MASK);
#endif
	if (regs->zq_config)
		/* Set time between rising edge of DDR_RESET to rising
		 * edge of DDR_CKE to > 500us per memory spec. */
		writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);

	writel(regs->emif_ddr_phy_ctlr_1,
		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
	writel(regs->emif_ddr_phy_ctlr_1,
		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);

	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
		if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
			ext_phy_settings_hwlvl(regs, nr);
		else
			ext_phy_settings_swlvl(regs, nr);
	}
}

/**
 * Configure DDR CMD control registers
 */
void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
{
	if (!cmd)
		return;

	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);

	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);

	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
}

/**
 * Configure DDR DATA registers
 */
void config_ddr_data(const struct ddr_data *data, int nr)
{
	int i;

	if (!data)
		return;

	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
		writel(data->datardsratio0,
			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
		writel(data->datawdsratio0,
			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
		writel(data->datawiratio0,
			&(ddr_data_reg[nr]+i)->dt0wiratio0);
		writel(data->datagiratio0,
			&(ddr_data_reg[nr]+i)->dt0giratio0);
		writel(data->datafwsratio0,
			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
		writel(data->datawrsratio0,
			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
	}
}

void config_io_ctrl(const struct ctrl_ioregs *ioregs)
{
	if (!ioregs)
		return;

	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
#ifdef CONFIG_AM43XX
	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
	writel(ioregs->emif_sdram_config_ext,
	       &ioctrl_reg->emif_sdram_config_ext);
#endif
}
Commit	Line	Data
62d7fe7c CN	1	/*
	2	* DDR Configuration for AM33xx devices.
	3	*
1a459660	4	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
62d7fe7c	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
62d7fe7c CN	7	*/
	8
	9	#include <asm/arch/cpu.h>
	10	#include <asm/arch/ddr_defs.h>
6995a289	11	#include <asm/arch/sys_proto.h>
62d7fe7c	12	#include <asm/io.h>
7d5eb349	13	#include <asm/emif.h>
62d7fe7c CN	14
	15	/**
	16	* Base address for EMIF instances
	17	*/
3ba65f97 MP	18	static struct emif_reg_struct *emif_reg[2] = {
	19	(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
	20	(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
62d7fe7c CN	21
62d7fe7c CN	22	/**
3ba65f97	23	* Base addresses for DDR PHY cmd/data regs
62d7fe7c	24	*/
3ba65f97 MP	25	static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
	26	(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
	27	(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
	28
	29	static struct ddr_data_regs *ddr_data_reg[2] = {
	30	(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
	31	(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
62d7fe7c CN	32
	33	/**
	34	* Base address for ddr io control instances
	35	*/
	36	static struct ddr_cmdtctrl *ioctrl_reg = {
	37	(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
	38
d3daba10 LV	39	static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
	40	{
	41	u32 mr;
	42
	43	mr_addr \|= cs << EMIF_REG_CS_SHIFT;
	44	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
	45
	46	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
	47	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
	48	if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
	49	((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
	50	((mr & 0xff000000) >> 24) == (mr & 0xff))
	51	return mr & 0xff;
	52	else
	53	return mr;
	54	}
	55
	56	static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
	57	{
	58	mr_addr \|= cs << EMIF_REG_CS_SHIFT;
	59	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
	60	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
	61	}
	62
	63	static void configure_mr(int nr, u32 cs)
	64	{
	65	u32 mr_addr;
	66
	67	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
	68	;
	69	set_mr(nr, cs, LPDDR2_MR10, 0x56);
	70
	71	set_mr(nr, cs, LPDDR2_MR1, 0x43);
	72	set_mr(nr, cs, LPDDR2_MR2, 0x2);
	73
	74	mr_addr = LPDDR2_MR2 \| EMIF_REG_REFRESH_EN_MASK;
	75	set_mr(nr, cs, mr_addr, 0x2);
	76	}
	77
	78	/*
fc46bae2 JD	79	* Configure EMIF4D5 registers and MR registers For details about these magic
fc46bae2 JD	80	* values please see the EMIF registers section of the TRM.
d3daba10 LV	81	*/
	82	void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
	83	{
4800be4a DG	84	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
4800be4a DG	85	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
d3daba10 LV	86	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
	87
	88	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
	89	writel(regs->emif_rd_wr_lvl_rmp_win,
	90	&emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
	91	writel(regs->emif_rd_wr_lvl_rmp_ctl,
	92	&emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
	93	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
	94	writel(regs->emif_rd_wr_exec_thresh,
	95	&emif_reg[nr]->emif_rd_wr_exec_thresh);
	96
8038b497 CJF	97	/*
	98	* for most SOCs these registers won't need to be changed so only
	99	* write to these registers if someone explicitly has set the
	100	* register's value.
	101	*/
	102	if(regs->emif_cos_config) {
	103	writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
	104	writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
	105	writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
	106	writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
	107	}
	108
fc46bae2 JD	109	/*
	110	* Sequence to ensure that the PHY is in a known state prior to
	111	* startting hardware leveling. Also acts as to latch some state from
	112	* the EMIF into the PHY.
	113	*/
	114	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
	115	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
	116	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
	117
	118	clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
	119	EMIF_REG_INITREF_DIS_MASK);
	120
d3daba10	121	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
f84880f0	122	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
fc46bae2 JD	123	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	124	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	125
7c352cd3 TR	126	/* Perform hardware leveling for DDR3 */
	127	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
	128	udelay(1000);
	129	writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) \|
	130	0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
	131	writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) \|
	132	0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
	133
	134	writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
	135
	136	/* Enable read leveling */
	137	writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
	138
	139	/*
	140	* Enable full read and write leveling. Wait for read and write
	141	* leveling bit to clear RDWRLVLFULL_START bit 31
	142	*/
	143	while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
	144	!= 0)
	145	;
	146
	147	/* Check the timeout register to see if leveling is complete */
	148	if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
	149	puts("DDR3 H/W leveling incomplete with errors\n");
	150
	151	} else {
	152	/* DDR2 */
b5e01eec LV	153	configure_mr(nr, 0);
	154	configure_mr(nr, 1);
	155	}
d3daba10 LV	156	}
d3daba10 LV	157
62d7fe7c CN	158	/**
	159	* Configure SDRAM
	160	*/
3ba65f97	161	void config_sdram(const struct emif_regs *regs, int nr)
62d7fe7c	162	{
1c382ead	163	if (regs->zq_config) {
3ba65f97	164	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
6995a289	165	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
3ba65f97	166	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
69b918b6 ES	167
	168	/* Trigger initialization */
	169	writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
	170	/* Wait 1ms because of L3 timeout error */
	171	udelay(1000);
	172
	173	/* Write proper sdram_ref_cref_ctrl value */
3ba65f97 MP	174	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
3ba65f97 MP	175	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
6995a289	176	}
3ba65f97 MP	177	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
3ba65f97 MP	178	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
e049b772	179	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
62d7fe7c CN	180	}
	181
	182	/**
	183	* Set SDRAM timings
	184	*/
3ba65f97	185	void set_sdram_timings(const struct emif_regs *regs, int nr)
62d7fe7c	186	{
3ba65f97 MP	187	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
	188	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
	189	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
	190	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
	191	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
	192	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
62d7fe7c CN	193	}
62d7fe7c CN	194
7c352cd3 TR	195	/*
	196	* Configure EXT PHY registers for software leveling
	197	*/
	198	static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
	199	{
	200	u32 *ext_phy_ctrl_base = 0;
	201	u32 *emif_ext_phy_ctrl_base = 0;
	202	__maybe_unused const u32 *ext_phy_ctrl_const_regs;
	203	u32 i = 0;
	204	__maybe_unused u32 size;
	205
	206	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
	207	emif_ext_phy_ctrl_base =
	208	(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
	209
	210	/* Configure external phy control timing registers */
	211	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
	212	writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
	213	/* Update shadow registers */
	214	writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
	215	}
	216
	217	#ifdef CONFIG_AM43XX
	218	/*
	219	* External phy 6-24 registers do not change with ddr frequency.
	220	* These only need to be set on DDR2 on AM43xx.
	221	*/
	222	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
	223
	224	if (!size)
	225	return;
	226
	227	for (i = 0; i < size; i++) {
	228	writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
	229	/* Update shadow registers */
	230	writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
	231	}
	232	#endif
	233	}
	234
d3daba10	235	/*
fc46bae2	236	* Configure EXT PHY registers for hardware leveling
d3daba10	237	*/
7c352cd3	238	static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
d3daba10	239	{
d3daba10	240	/*
fc46bae2 JD	241	* Enable hardware leveling on the EMIF. For details about these
fc46bae2 JD	242	* magic values please see the EMIF registers section of the TRM.
d3daba10	243	*/
fc46bae2 JD	244	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
	245	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
	246	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
	247	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
	248	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
	249	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
	250	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
	251	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
	252	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
	253	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
	254	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
	255	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
	256	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
	257	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
	258	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
	259	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
	260	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
	261	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
	262	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
	263	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
	264	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
	265	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
	266	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
	267	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
	268	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
	269	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
	270	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
	271	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
	272	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
	273	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
	274	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
	275	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
d3daba10	276
fc46bae2 JD	277	/*
	278	* Sequence to ensure that the PHY is again in a known state after
	279	* hardware leveling.
	280	*/
	281	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
	282	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
	283	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
d3daba10 LV	284	}
d3daba10 LV	285
62d7fe7c CN	286	/**
	287	* Configure DDR PHY
	288	*/
3ba65f97	289	void config_ddr_phy(const struct emif_regs *regs, int nr)
62d7fe7c	290	{
d3daba10	291	/*
fc46bae2	292	* Disable initialization and refreshes for now until we
d3daba10	293	* finish programming EMIF regs.
fc46bae2 JD	294	* Also set time between rising edge of DDR_RESET to rising
fc46bae2 JD	295	* edge of DDR_CKE to > 500us per memory spec.
d3daba10	296	*/
fc46bae2	297	#ifndef CONFIG_AM43XX
d3daba10 LV	298	setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
d3daba10 LV	299	EMIF_REG_INITREF_DIS_MASK);
fc46bae2 JD	300	#endif
fc46bae2 JD	301	if (regs->zq_config)
69b918b6 ES	302	/* Set time between rising edge of DDR_RESET to rising
	303	* edge of DDR_CKE to > 500us per memory spec. */
	304	writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
d3daba10	305
3ba65f97 MP	306	writel(regs->emif_ddr_phy_ctlr_1,
	307	&emif_reg[nr]->emif_ddr_phy_ctrl_1);
	308	writel(regs->emif_ddr_phy_ctlr_1,
	309	&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
d3daba10	310
7c352cd3 TR	311	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
	312	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
	313	ext_phy_settings_hwlvl(regs, nr);
	314	else
	315	ext_phy_settings_swlvl(regs, nr);
	316	}
62d7fe7c CN	317	}
	318
	319	/**
	320	* Configure DDR CMD control registers
	321	*/
3ba65f97	322	void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
62d7fe7c	323	{
965de8b9 LV	324	if (!cmd)
	325	return;
	326
3ba65f97	327	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
3ba65f97	328	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
62d7fe7c	329
3ba65f97	330	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
3ba65f97	331	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
62d7fe7c	332
3ba65f97	333	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
3ba65f97	334	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
62d7fe7c CN	335	}
	336
	337	/**
	338	* Configure DDR DATA registers
	339	*/
3ba65f97	340	void config_ddr_data(const struct ddr_data *data, int nr)
62d7fe7c	341	{
3ba65f97 MP	342	int i;
3ba65f97 MP	343
965de8b9 LV	344	if (!data)
	345	return;
	346
3ba65f97 MP	347	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
	348	writel(data->datardsratio0,
	349	&(ddr_data_reg[nr]+i)->dt0rdsratio0);
	350	writel(data->datawdsratio0,
	351	&(ddr_data_reg[nr]+i)->dt0wdsratio0);
	352	writel(data->datawiratio0,
	353	&(ddr_data_reg[nr]+i)->dt0wiratio0);
	354	writel(data->datagiratio0,
	355	&(ddr_data_reg[nr]+i)->dt0giratio0);
	356	writel(data->datafwsratio0,
	357	&(ddr_data_reg[nr]+i)->dt0fwsratio0);
	358	writel(data->datawrsratio0,
	359	&(ddr_data_reg[nr]+i)->dt0wrsratio0);
3ba65f97	360	}
62d7fe7c CN	361	}
62d7fe7c CN	362
965de8b9	363	void config_io_ctrl(const struct ctrl_ioregs *ioregs)
62d7fe7c	364	{
965de8b9 LV	365	if (!ioregs)
	366	return;
	367
	368	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
	369	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
	370	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
	371	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
	372	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
	373	#ifdef CONFIG_AM43XX
	374	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
	375	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
	376	writel(ioregs->emif_sdram_config_ext,
	377	&ioctrl_reg->emif_sdram_config_ext);
	378	#endif
62d7fe7c	379	}