[people/ms/u-boot.git] / arch / arm / cpu / armv7 / am33xx / ddr.c

/*
 * DDR Configuration for AM33xx devices.
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>

/**
 * Base address for EMIF instances
 */
static struct emif_reg_struct *emif_reg[2] = {
				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};

/**
 * Base addresses for DDR PHY cmd/data regs
 */
static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};

static struct ddr_data_regs *ddr_data_reg[2] = {
				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};

/**
 * Base address for ddr io control instances
 */
static struct ddr_cmdtctrl *ioctrl_reg = {
			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};

static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
{
	u32 mr;

	mr_addr |= cs << EMIF_REG_CS_SHIFT;
	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);

	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
	if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
	    ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
	    ((mr & 0xff000000) >> 24) == (mr & 0xff))
		return mr & 0xff;
	else
		return mr;
}

static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
{
	mr_addr |= cs << EMIF_REG_CS_SHIFT;
	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
}

static void configure_mr(int nr, u32 cs)
{
	u32 mr_addr;

	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
		;
	set_mr(nr, cs, LPDDR2_MR10, 0x56);

	set_mr(nr, cs, LPDDR2_MR1, 0x43);
	set_mr(nr, cs, LPDDR2_MR2, 0x2);

	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
	set_mr(nr, cs, mr_addr, 0x2);
}

/*
 * Configure EMIF4D5 registers and MR registers
 */
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
	writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
	writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
	writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);

	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
	writel(regs->emif_rd_wr_lvl_rmp_win,
	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
	writel(regs->emif_rd_wr_lvl_rmp_ctl,
	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
	writel(regs->emif_rd_wr_exec_thresh,
	       &emif_reg[nr]->emif_rd_wr_exec_thresh);

	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);

	configure_mr(nr, 0);
	configure_mr(nr, 1);
}

/**
 * Configure SDRAM
 */
void config_sdram(const struct emif_regs *regs, int nr)
{
	if (regs->zq_config) {
		/*
		 * A value of 0x2800 for the REF CTRL will give us
		 * about 570us for a delay, which will be long enough
		 * to configure things.
		 */
		writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	}
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
}

/**
 * Set SDRAM timings
 */
void set_sdram_timings(const struct emif_regs *regs, int nr)
{
	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}

void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
{
}

/*
 * Configure EXT PHY registers
 */
static void ext_phy_settings(const struct emif_regs *regs, int nr)
{
	u32 *ext_phy_ctrl_base = 0;
	u32 *emif_ext_phy_ctrl_base = 0;
	const u32 *ext_phy_ctrl_const_regs;
	u32 i = 0;
	u32 size;

	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
	emif_ext_phy_ctrl_base =
			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);

	/* Configure external phy control timing registers */
	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
		/* Update shadow registers */
		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
	}

	/*
	 * external phy 6-24 registers do not change with
	 * ddr frequency
	 */
	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);

	if (!size)
		return;

	for (i = 0; i < size; i++) {
		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
		/* Update shadow registers */
		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
	}
}

/**
 * Configure DDR PHY
 */
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
	/*
	 * disable initialization and refreshes for now until we
	 * finish programming EMIF regs.
	 */
	setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
		     EMIF_REG_INITREF_DIS_MASK);

	writel(regs->emif_ddr_phy_ctlr_1,
		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
	writel(regs->emif_ddr_phy_ctlr_1,
		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);

	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
		ext_phy_settings(regs, nr);
}

/**
 * Configure DDR CMD control registers
 */
void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
{
	if (!cmd)
		return;

	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);

	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);

	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
}

/**
 * Configure DDR DATA registers
 */
void config_ddr_data(const struct ddr_data *data, int nr)
{
	int i;

	if (!data)
		return;

	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
		writel(data->datardsratio0,
			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
		writel(data->datawdsratio0,
			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
		writel(data->datawiratio0,
			&(ddr_data_reg[nr]+i)->dt0wiratio0);
		writel(data->datagiratio0,
			&(ddr_data_reg[nr]+i)->dt0giratio0);
		writel(data->datafwsratio0,
			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
		writel(data->datawrsratio0,
			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
	}
}

void config_io_ctrl(const struct ctrl_ioregs *ioregs)
{
	if (!ioregs)
		return;

	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
#ifdef CONFIG_AM43XX
	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
	writel(ioregs->emif_sdram_config_ext,
	       &ioctrl_reg->emif_sdram_config_ext);
#endif
}
Commit	Line	Data
62d7fe7c CN	1	/*
	2	* DDR Configuration for AM33xx devices.
	3	*
1a459660	4	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
62d7fe7c	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
62d7fe7c CN	7	*/
	8
	9	#include <asm/arch/cpu.h>
	10	#include <asm/arch/ddr_defs.h>
6995a289	11	#include <asm/arch/sys_proto.h>
62d7fe7c	12	#include <asm/io.h>
7d5eb349	13	#include <asm/emif.h>
62d7fe7c CN	14
	15	/**
	16	* Base address for EMIF instances
	17	*/
3ba65f97 MP	18	static struct emif_reg_struct *emif_reg[2] = {
	19	(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
	20	(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
62d7fe7c CN	21
62d7fe7c CN	22	/**
3ba65f97	23	* Base addresses for DDR PHY cmd/data regs
62d7fe7c	24	*/
3ba65f97 MP	25	static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
	26	(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
	27	(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
	28
	29	static struct ddr_data_regs *ddr_data_reg[2] = {
	30	(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
	31	(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
62d7fe7c CN	32
	33	/**
	34	* Base address for ddr io control instances
	35	*/
	36	static struct ddr_cmdtctrl *ioctrl_reg = {
	37	(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
	38
d3daba10 LV	39	static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
	40	{
	41	u32 mr;
	42
	43	mr_addr \|= cs << EMIF_REG_CS_SHIFT;
	44	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
	45
	46	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
	47	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
	48	if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
	49	((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
	50	((mr & 0xff000000) >> 24) == (mr & 0xff))
	51	return mr & 0xff;
	52	else
	53	return mr;
	54	}
	55
	56	static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
	57	{
	58	mr_addr \|= cs << EMIF_REG_CS_SHIFT;
	59	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
	60	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
	61	}
	62
	63	static void configure_mr(int nr, u32 cs)
	64	{
	65	u32 mr_addr;
	66
	67	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
	68	;
	69	set_mr(nr, cs, LPDDR2_MR10, 0x56);
	70
	71	set_mr(nr, cs, LPDDR2_MR1, 0x43);
	72	set_mr(nr, cs, LPDDR2_MR2, 0x2);
	73
	74	mr_addr = LPDDR2_MR2 \| EMIF_REG_REFRESH_EN_MASK;
	75	set_mr(nr, cs, mr_addr, 0x2);
	76	}
	77
	78	/*
	79	* Configure EMIF4D5 registers and MR registers
	80	*/
	81	void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
	82	{
	83	writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
	84	writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
	85	writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
	86	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
	87
	88	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
	89	writel(regs->emif_rd_wr_lvl_rmp_win,
	90	&emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
	91	writel(regs->emif_rd_wr_lvl_rmp_ctl,
	92	&emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
	93	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
	94	writel(regs->emif_rd_wr_exec_thresh,
	95	&emif_reg[nr]->emif_rd_wr_exec_thresh);
	96
	97	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	98	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
	99
	100	configure_mr(nr, 0);
	101	configure_mr(nr, 1);
	102	}
103
62d7fe7c CN	104	/**
	105	* Configure SDRAM
	106	*/
3ba65f97	107	void config_sdram(const struct emif_regs *regs, int nr)
62d7fe7c	108	{
1c382ead TR	109	if (regs->zq_config) {
	110	/*
	111	* A value of 0x2800 for the REF CTRL will give us
	112	* about 570us for a delay, which will be long enough
	113	* to configure things.
	114	*/
3ba65f97 MP	115	writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
3ba65f97 MP	116	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
6995a289	117	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
3ba65f97 MP	118	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
	119	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	120	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
6995a289	121	}
3ba65f97 MP	122	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	123	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	124	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
62d7fe7c CN	125	}
	126
	127	/**
	128	* Set SDRAM timings
	129	*/
3ba65f97	130	void set_sdram_timings(const struct emif_regs *regs, int nr)
62d7fe7c	131	{
3ba65f97 MP	132	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
	133	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
	134	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
	135	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
	136	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
	137	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
62d7fe7c CN	138	}
62d7fe7c CN	139
d3daba10 LV	140	void __weak emif_get_ext_phy_ctrl_const_regs(const u32 *regs, u32 size)
	141	{
	142	}
	143
	144	/*
	145	* Configure EXT PHY registers
	146	*/
	147	static void ext_phy_settings(const struct emif_regs *regs, int nr)
	148	{
	149	u32 *ext_phy_ctrl_base = 0;
	150	u32 *emif_ext_phy_ctrl_base = 0;
	151	const u32 *ext_phy_ctrl_const_regs;
	152	u32 i = 0;
	153	u32 size;
	154
	155	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
	156	emif_ext_phy_ctrl_base =
	157	(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
	158
	159	/* Configure external phy control timing registers */
	160	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
	161	writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
	162	/* Update shadow registers */
	163	writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
	164	}
	165
	166	/*
	167	* external phy 6-24 registers do not change with
	168	* ddr frequency
	169	*/
	170	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
	171
	172	if (!size)
	173	return;
	174
	175	for (i = 0; i < size; i++) {
	176	writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
	177	/* Update shadow registers */
	178	writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
	179	}
	180	}
	181
62d7fe7c CN	182	/**
	183	* Configure DDR PHY
	184	*/
3ba65f97	185	void config_ddr_phy(const struct emif_regs *regs, int nr)
62d7fe7c	186	{
d3daba10 LV	187	/*
	188	* disable initialization and refreshes for now until we
	189	* finish programming EMIF regs.
	190	*/
	191	setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
	192	EMIF_REG_INITREF_DIS_MASK);
	193
3ba65f97 MP	194	writel(regs->emif_ddr_phy_ctlr_1,
	195	&emif_reg[nr]->emif_ddr_phy_ctrl_1);
	196	writel(regs->emif_ddr_phy_ctlr_1,
	197	&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
d3daba10 LV	198
	199	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
	200	ext_phy_settings(regs, nr);
62d7fe7c CN	201	}
	202
	203	/**
	204	* Configure DDR CMD control registers
	205	*/
3ba65f97	206	void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
62d7fe7c	207	{
965de8b9 LV	208	if (!cmd)
	209	return;
	210
3ba65f97	211	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
3ba65f97	212	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
62d7fe7c	213
3ba65f97	214	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
3ba65f97	215	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
62d7fe7c	216
3ba65f97	217	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
3ba65f97	218	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
62d7fe7c CN	219	}
	220
	221	/**
	222	* Configure DDR DATA registers
	223	*/
3ba65f97	224	void config_ddr_data(const struct ddr_data *data, int nr)
62d7fe7c	225	{
3ba65f97 MP	226	int i;
3ba65f97 MP	227
965de8b9 LV	228	if (!data)
	229	return;
	230
3ba65f97 MP	231	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
	232	writel(data->datardsratio0,
	233	&(ddr_data_reg[nr]+i)->dt0rdsratio0);
	234	writel(data->datawdsratio0,
	235	&(ddr_data_reg[nr]+i)->dt0wdsratio0);
	236	writel(data->datawiratio0,
	237	&(ddr_data_reg[nr]+i)->dt0wiratio0);
	238	writel(data->datagiratio0,
	239	&(ddr_data_reg[nr]+i)->dt0giratio0);
	240	writel(data->datafwsratio0,
	241	&(ddr_data_reg[nr]+i)->dt0fwsratio0);
	242	writel(data->datawrsratio0,
	243	&(ddr_data_reg[nr]+i)->dt0wrsratio0);
3ba65f97	244	}
62d7fe7c CN	245	}
62d7fe7c CN	246
965de8b9	247	void config_io_ctrl(const struct ctrl_ioregs *ioregs)
62d7fe7c	248	{
965de8b9 LV	249	if (!ioregs)
	250	return;
	251
	252	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
	253	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
	254	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
	255	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
	256	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
	257	#ifdef CONFIG_AM43XX
	258	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
	259	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
	260	writel(ioregs->emif_sdram_config_ext,
	261	&ioctrl_reg->emif_sdram_config_ext);
	262	#endif
62d7fe7c	263	}