]>
Commit | Line | Data |
---|---|---|
62d7fe7c CN |
1 | /* |
2 | * emif4.c | |
3 | * | |
4 | * AM33XX emif4 configuration file | |
5 | * | |
6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
62d7fe7c CN |
9 | */ |
10 | ||
11 | #include <common.h> | |
12 | #include <asm/arch/cpu.h> | |
13 | #include <asm/arch/ddr_defs.h> | |
14 | #include <asm/arch/hardware.h> | |
15 | #include <asm/arch/clock.h> | |
b971dfad | 16 | #include <asm/arch/sys_proto.h> |
62d7fe7c | 17 | #include <asm/io.h> |
fda35eb9 | 18 | #include <asm/emif.h> |
62d7fe7c CN |
19 | |
20 | DECLARE_GLOBAL_DATA_PTR; | |
21 | ||
62d7fe7c CN |
22 | int dram_init(void) |
23 | { | |
24 | /* dram_init must store complete ramsize in gd->ram_size */ | |
25 | gd->ram_size = get_ram_size( | |
26 | (void *)CONFIG_SYS_SDRAM_BASE, | |
27 | CONFIG_MAX_RAM_BANK_SIZE); | |
28 | return 0; | |
29 | } | |
30 | ||
31 | void dram_init_banksize(void) | |
32 | { | |
33 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
34 | gd->bd->bi_dram[0].size = gd->ram_size; | |
35 | } | |
36 | ||
37 | ||
8a8f084e | 38 | #ifdef CONFIG_SPL_BUILD |
4fab8d7b MP |
39 | static struct dmm_lisa_map_regs *hw_lisa_map_regs = |
40 | (struct dmm_lisa_map_regs *)DMM_BASE; | |
3ba65f97 MP |
41 | static struct vtp_reg *vtpreg[2] = { |
42 | (struct vtp_reg *)VTP0_CTRL_ADDR, | |
43 | (struct vtp_reg *)VTP1_CTRL_ADDR}; | |
44 | #ifdef CONFIG_AM33XX | |
942d3f01 | 45 | static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; |
3ba65f97 | 46 | #endif |
942d3f01 | 47 | |
4fab8d7b MP |
48 | void config_dmm(const struct dmm_lisa_map_regs *regs) |
49 | { | |
50 | enable_dmm_clocks(); | |
51 | ||
52 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); | |
53 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); | |
54 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); | |
55 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); | |
56 | ||
57 | writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); | |
58 | writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); | |
59 | writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); | |
60 | writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); | |
61 | } | |
62 | ||
3ba65f97 | 63 | static void config_vtp(int nr) |
62d7fe7c | 64 | { |
3ba65f97 MP |
65 | writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, |
66 | &vtpreg[nr]->vtp0ctrlreg); | |
67 | writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), | |
68 | &vtpreg[nr]->vtp0ctrlreg); | |
69 | writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, | |
70 | &vtpreg[nr]->vtp0ctrlreg); | |
62d7fe7c CN |
71 | |
72 | /* Poll for READY */ | |
3ba65f97 | 73 | while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != |
62d7fe7c CN |
74 | VTP_CTRL_READY) |
75 | ; | |
76 | } | |
77 | ||
c00f69db PK |
78 | void config_ddr(unsigned int pll, unsigned int ioctrl, |
79 | const struct ddr_data *data, const struct cmd_control *ctrl, | |
3ba65f97 | 80 | const struct emif_regs *regs, int nr) |
62d7fe7c | 81 | { |
318f27c9 | 82 | enable_emif_clocks(); |
c00f69db | 83 | ddr_pll_config(pll); |
3ba65f97 MP |
84 | config_vtp(nr); |
85 | config_cmd_ctrl(ctrl, nr); | |
62d7fe7c | 86 | |
3ba65f97 MP |
87 | config_ddr_data(data, nr); |
88 | #ifdef CONFIG_AM33XX | |
c00f69db | 89 | config_io_ctrl(ioctrl); |
62d7fe7c | 90 | |
318f27c9 TR |
91 | /* Set CKE to be controlled by EMIF/DDR PHY */ |
92 | writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); | |
3ba65f97 | 93 | #endif |
62d7fe7c | 94 | |
318f27c9 | 95 | /* Program EMIF instance */ |
3ba65f97 MP |
96 | config_ddr_phy(regs, nr); |
97 | set_sdram_timings(regs, nr); | |
98 | config_sdram(regs, nr); | |
62d7fe7c CN |
99 | } |
100 | #endif |