[thirdparty/u-boot.git] / arch / arm / cpu / armv7 / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2008 Texas Insturments
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * (C) Copyright 2002
 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
 */

/*
 * CPU specific code
 */

#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/system.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <linux/compiler.h>

void __weak cpu_cache_initialization(void){}

int cleanup_before_linux_select(int flags)
{
	/*
	 * this function is called just before we call linux
	 * it prepares the processor for linux
	 *
	 * we turn off caches etc ...
	 */
#ifndef CONFIG_SPL_BUILD
	disable_interrupts();
#endif

	if (flags & CBL_DISABLE_CACHES) {
		/*
		* turn off D-cache
		* dcache_disable() in turn flushes the d-cache and disables MMU
		*/
		dcache_disable();
		v7_outer_cache_disable();

		/*
		* After D-cache is flushed and before it is disabled there may
		* be some new valid entries brought into the cache. We are
		* sure that these lines are not dirty and will not affect our
		* execution. (because unwinding the call-stack and setting a
		* bit in CP15 SCTRL is all we did during this. We have not
		* pushed anything on to the stack. Neither have we affected
		* any static data) So just invalidate the entire d-cache again
		* to avoid coherency problems for kernel
		*/
		invalidate_dcache_all();

		icache_disable();
		invalidate_icache_all();
	} else {
		/*
		 * Turn off I-cache and invalidate it
		 */
		icache_disable();
		invalidate_icache_all();

		flush_dcache_all();
		invalidate_icache_all();
		icache_enable();
	}

	/*
	 * Some CPU need more cache attention before starting the kernel.
	 */
	cpu_cache_initialization();

	return 0;
}

int cleanup_before_linux(void)
{
	return cleanup_before_linux_select(CBL_ALL);
}

void allow_unaligned(void)
{
	v7_arch_cp15_allow_unaligned();
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
0b02b184 DB	2	/*
	3	* (C) Copyright 2008 Texas Insturments
	4	*
	5	* (C) Copyright 2002
	6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <mgroeger@sysgo.de>
	8	*
	9	* (C) Copyright 2002
792a09eb	10	* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
0b02b184 DB	11	*/
	12
	13	/*
	14	* CPU specific code
	15	*/
	16
d678a59d	17	#include <common.h>
0b02b184	18	#include <command.h>
9edefc27	19	#include <cpu_func.h>
36bf446b	20	#include <irq_func.h>
677e62f4	21	#include <asm/system.h>
06e758e7	22	#include <asm/cache.h>
c2dd0d45	23	#include <asm/armv7.h>
53e6f6a6	24	#include <linux/compiler.h>
0b02b184	25
53e6f6a6 MP	26	void __weak cpu_cache_initialization(void){}
53e6f6a6 MP	27
4d24a11e	28	int cleanup_before_linux_select(int flags)
0b02b184	29	{
0b02b184 DB	30	/*
	31	* this function is called just before we call linux
	32	* it prepares the processor for linux
	33	*
	34	* we turn off caches etc ...
	35	*/
d460587a	36	#ifndef CONFIG_SPL_BUILD
0b02b184	37	disable_interrupts();
d460587a	38	#endif
0b02b184	39
4d24a11e SG	40	if (flags & CBL_DISABLE_CACHES) {
	41	/*
	42	* turn off D-cache
	43	* dcache_disable() in turn flushes the d-cache and disables MMU
	44	*/
	45	dcache_disable();
	46	v7_outer_cache_disable();
0b02b184	47
4d24a11e SG	48	/*
	49	* After D-cache is flushed and before it is disabled there may
	50	* be some new valid entries brought into the cache. We are
	51	* sure that these lines are not dirty and will not affect our
	52	* execution. (because unwinding the call-stack and setting a
	53	* bit in CP15 SCTRL is all we did during this. We have not
	54	* pushed anything on to the stack. Neither have we affected
	55	* any static data) So just invalidate the entire d-cache again
	56	* to avoid coherency problems for kernel
	57	*/
	58	invalidate_dcache_all();
81b0618d SS	59
	60	icache_disable();
	61	invalidate_icache_all();
4d24a11e	62	} else {
81b0618d SS	63	/*
	64	* Turn off I-cache and invalidate it
	65	*/
	66	icache_disable();
	67	invalidate_icache_all();
	68
4d24a11e SG	69	flush_dcache_all();
	70	invalidate_icache_all();
	71	icache_enable();
	72	}
0b02b184	73
53e6f6a6 MP	74	/*
	75	* Some CPU need more cache attention before starting the kernel.
	76	*/
	77	cpu_cache_initialization();
	78
0b02b184 DB	79	return 0;
0b02b184 DB	80	}
4d24a11e SG	81
	82	int cleanup_before_linux(void)
	83	{
	84	return cleanup_before_linux_select(CBL_ALL);
	85	}
c3224860 MV	86
	87	void allow_unaligned(void)
	88	{
	89	v7_arch_cp15_allow_unaligned();
	90	}