[people/ms/u-boot.git] / arch / arm / cpu / armv7 / exynos / power.c

/*
 * Copyright (C) 2012 Samsung Electronics
 * Donghwa Lee <dh09.lee@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/power.h>

static void exynos4_mipi_phy_control(unsigned int dev_index,
					unsigned int enable)
{
	struct exynos4_power *pmu =
	    (struct exynos4_power *)samsung_get_base_power();
	unsigned int addr, cfg = 0;

	if (dev_index == 0)
		addr = (unsigned int)&pmu->mipi_phy0_control;
	else
		addr = (unsigned int)&pmu->mipi_phy1_control;


	cfg = readl(addr);
	if (enable)
		cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
	else
		cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);

	writel(cfg, addr);
}

void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
{
	if (cpu_is_exynos4())
		exynos4_mipi_phy_control(dev_index, enable);
}

void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
{
	struct exynos5_power *power =
		(struct exynos5_power *)samsung_get_base_power();

	if (enable) {
		/* Enabling USBHOST_PHY */
		setbits_le32(&power->usbhost_phy_control,
				POWER_USB_HOST_PHY_CTRL_EN);
	} else {
		/* Disabling USBHOST_PHY */
		clrbits_le32(&power->usbhost_phy_control,
				POWER_USB_HOST_PHY_CTRL_EN);
	}
}

void set_usbhost_phy_ctrl(unsigned int enable)
{
	if (cpu_is_exynos5())
		exynos5_set_usbhost_phy_ctrl(enable);
}

static void exynos5_dp_phy_control(unsigned int enable)
{
	unsigned int cfg;
	struct exynos5_power *power =
	    (struct exynos5_power *)samsung_get_base_power();

	cfg = readl(&power->dptx_phy_control);
	if (enable)
		cfg |= EXYNOS_DP_PHY_ENABLE;
	else
		cfg &= ~EXYNOS_DP_PHY_ENABLE;

	writel(cfg, &power->dptx_phy_control);
}

void set_dp_phy_ctrl(unsigned int enable)
{
	if (cpu_is_exynos5())
		exynos5_dp_phy_control(enable);
}

static void exynos5_set_ps_hold_ctrl(void)
{
	struct exynos5_power *power =
		(struct exynos5_power *)samsung_get_base_power();

	/* Set PS-Hold high */
	setbits_le32(&power->ps_hold_control,
			EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
}

void set_ps_hold_ctrl(void)
{
	if (cpu_is_exynos5())
		exynos5_set_ps_hold_ctrl();
}


static void exynos5_set_xclkout(void)
{
	struct exynos5_power *power =
		(struct exynos5_power *)samsung_get_base_power();

	/* use xxti for xclk out */
	clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
				PMU_DEBUG_XXTI);
}

void set_xclkout(void)
{
	if (cpu_is_exynos5())
		exynos5_set_xclkout();
}

/* Enables hardware tripping to power off the system when TMU fails */
void set_hw_thermal_trip(void)
{
	if (cpu_is_exynos5()) {
		struct exynos5_power *power =
			(struct exynos5_power *)samsung_get_base_power();

		/* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
		setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
	}
}

static uint32_t exynos5_get_reset_status(void)
{
	struct exynos5_power *power =
		(struct exynos5_power *)samsung_get_base_power();

	return power->inform1;
}

static uint32_t exynos4_get_reset_status(void)
{
	struct exynos4_power *power =
		(struct exynos4_power *)samsung_get_base_power();

	return power->inform1;
}

uint32_t get_reset_status(void)
{
	if (cpu_is_exynos5())
		return exynos5_get_reset_status();
	else
		return  exynos4_get_reset_status();
}

static void exynos5_power_exit_wakeup(void)
{
	struct exynos5_power *power =
		(struct exynos5_power *)samsung_get_base_power();
	typedef void (*resume_func)(void);

	((resume_func)power->inform0)();
}

static void exynos4_power_exit_wakeup(void)
{
	struct exynos4_power *power =
		(struct exynos4_power *)samsung_get_base_power();
	typedef void (*resume_func)(void);

	((resume_func)power->inform0)();
}

void power_exit_wakeup(void)
{
	if (cpu_is_exynos5())
		exynos5_power_exit_wakeup();
	else
		exynos4_power_exit_wakeup();
}
Commit	Line	Data
283591f1 DL	1	/*
	2	* Copyright (C) 2012 Samsung Electronics
	3	* Donghwa Lee <dh09.lee@samsung.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
283591f1 DL	6	*/
	7
	8	#include <common.h>
	9	#include <asm/io.h>
	10	#include <asm/arch/power.h>
	11
	12	static void exynos4_mipi_phy_control(unsigned int dev_index,
	13	unsigned int enable)
	14	{
	15	struct exynos4_power *pmu =
	16	(struct exynos4_power *)samsung_get_base_power();
	17	unsigned int addr, cfg = 0;
	18
	19	if (dev_index == 0)
	20	addr = (unsigned int)&pmu->mipi_phy0_control;
	21	else
	22	addr = (unsigned int)&pmu->mipi_phy1_control;
	23
	24
	25	cfg = readl(addr);
	26	if (enable)
	27	cfg \|= (EXYNOS_MIPI_PHY_MRESETN \| EXYNOS_MIPI_PHY_ENABLE);
	28	else
	29	cfg &= ~(EXYNOS_MIPI_PHY_MRESETN \| EXYNOS_MIPI_PHY_ENABLE);
	30
	31	writel(cfg, addr);
	32	}
	33
	34	void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
	35	{
	36	if (cpu_is_exynos4())
	37	exynos4_mipi_phy_control(dev_index, enable);
	38	}
c48ac113 RS	39
	40	void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
	41	{
	42	struct exynos5_power *power =
	43	(struct exynos5_power *)samsung_get_base_power();
	44
	45	if (enable) {
	46	/* Enabling USBHOST_PHY */
	47	setbits_le32(&power->usbhost_phy_control,
	48	POWER_USB_HOST_PHY_CTRL_EN);
	49	} else {
	50	/* Disabling USBHOST_PHY */
	51	clrbits_le32(&power->usbhost_phy_control,
	52	POWER_USB_HOST_PHY_CTRL_EN);
	53	}
	54	}
	55
	56	void set_usbhost_phy_ctrl(unsigned int enable)
	57	{
	58	if (cpu_is_exynos5())
	59	exynos5_set_usbhost_phy_ctrl(enable);
	60	}
b6516677 DL	61
	62	static void exynos5_dp_phy_control(unsigned int enable)
	63	{
	64	unsigned int cfg;
	65	struct exynos5_power *power =
	66	(struct exynos5_power *)samsung_get_base_power();
	67
	68	cfg = readl(&power->dptx_phy_control);
	69	if (enable)
	70	cfg \|= EXYNOS_DP_PHY_ENABLE;
	71	else
	72	cfg &= ~EXYNOS_DP_PHY_ENABLE;
	73
	74	writel(cfg, &power->dptx_phy_control);
	75	}
	76
	77	void set_dp_phy_ctrl(unsigned int enable)
	78	{
	79	if (cpu_is_exynos5())
	80	exynos5_dp_phy_control(enable);
	81	}
51ff1eda RS	82
	83	static void exynos5_set_ps_hold_ctrl(void)
	84	{
	85	struct exynos5_power *power =
	86	(struct exynos5_power *)samsung_get_base_power();
	87
	88	/* Set PS-Hold high */
	89	setbits_le32(&power->ps_hold_control,
	90	EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
	91	}
	92
	93	void set_ps_hold_ctrl(void)
	94	{
	95	if (cpu_is_exynos5())
	96	exynos5_set_ps_hold_ctrl();
	97	}
a006076b RS	98
	99
	100	static void exynos5_set_xclkout(void)
	101	{
	102	struct exynos5_power *power =
	103	(struct exynos5_power *)samsung_get_base_power();
	104
	105	/* use xxti for xclk out */
	106	clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
	107	PMU_DEBUG_XXTI);
	108	}
	109
	110	void set_xclkout(void)
	111	{
	112	if (cpu_is_exynos5())
	113	exynos5_set_xclkout();
	114	}
3a0b1dae AS	115
	116	/* Enables hardware tripping to power off the system when TMU fails */
	117	void set_hw_thermal_trip(void)
	118	{
	119	if (cpu_is_exynos5()) {
	120	struct exynos5_power *power =
	121	(struct exynos5_power *)samsung_get_base_power();
	122
	123	/* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
	124	setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
	125	}
	126	}
dc20fdd7 RS	127
	128	static uint32_t exynos5_get_reset_status(void)
	129	{
	130	struct exynos5_power *power =
	131	(struct exynos5_power *)samsung_get_base_power();
	132
	133	return power->inform1;
	134	}
	135
	136	static uint32_t exynos4_get_reset_status(void)
	137	{
	138	struct exynos4_power *power =
	139	(struct exynos4_power *)samsung_get_base_power();
	140
	141	return power->inform1;
	142	}
	143
	144	uint32_t get_reset_status(void)
	145	{
	146	if (cpu_is_exynos5())
	147	return exynos5_get_reset_status();
	148	else
	149	return exynos4_get_reset_status();
	150	}
	151
	152	static void exynos5_power_exit_wakeup(void)
	153	{
	154	struct exynos5_power *power =
	155	(struct exynos5_power *)samsung_get_base_power();
	156	typedef void (*resume_func)(void);
	157
	158	((resume_func)power->inform0)();
	159	}
	160
	161	static void exynos4_power_exit_wakeup(void)
	162	{
	163	struct exynos4_power *power =
	164	(struct exynos4_power *)samsung_get_base_power();
	165	typedef void (*resume_func)(void);
	166
	167	((resume_func)power->inform0)();
	168	}
	169
	170	void power_exit_wakeup(void)
	171	{
	172	if (cpu_is_exynos5())
	173	exynos5_power_exit_wakeup();
	174	else
	175	exynos4_power_exit_wakeup();
	176	}