[thirdparty/u-boot.git] / arch / arm / cpu / armv7 / ls102xa / fdt.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <clock_legacy.h>
#include <net.h>
#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/clock.h>
#include <linux/ctype.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
#include <tsec.h>
#include <asm/arch/immap_ls102xa.h>
#include <fsl_sec.h>
#include <dm.h>

DECLARE_GLOBAL_DATA_PTR;

void ft_fixup_enet_phy_connect_type(void *fdt)
{
	struct udevice *dev;
	struct tsec_private *priv;
	const char *enet_path, *phy_path;
	char enet[16];
	char phy[16];
	int phy_node;
	int i = 0;
	uint32_t ph;
	char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
			  "ethernet@2d90000" };

	for (; i < ARRAY_SIZE(name); i++) {
		dev = eth_get_dev_by_name(name[i]);
		if (dev) {
			sprintf(enet, "ethernet%d", i);
			sprintf(phy, "enet%d_rgmii_phy", i);
		} else {
			continue;
		}

		priv = dev_get_priv(dev);
		if (priv->flags & TSEC_SGMII)
			continue;

		enet_path = fdt_get_alias(fdt, enet);
		if (!enet_path)
			continue;

		phy_path = fdt_get_alias(fdt, phy);
		if (!phy_path)
			continue;

		phy_node = fdt_path_offset(fdt, phy_path);
		if (phy_node < 0)
			continue;

		ph = fdt_create_phandle(fdt, phy_node);
		if (ph)
			do_fixup_by_path_u32(fdt, enet_path,
					     "phy-handle", ph, 1);

		do_fixup_by_path(fdt, enet_path, "phy-connection-type",
				 phy_string_for_interface(
				 PHY_INTERFACE_MODE_RGMII_ID),
				 strlen(phy_string_for_interface(
				 PHY_INTERFACE_MODE_RGMII_ID)) + 1,
				 1);
	}
}

void ft_cpu_setup(void *blob, struct bd_info *bd)
{
	int off;
	int val;
	const char *sysclk_path;
	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
	unsigned int svr;
	svr = in_be32(&gur->svr);

	unsigned long busclk = get_bus_freq(0);

	/* delete crypto node if not on an E-processor */
	if (!IS_E_PROCESSOR(svr))
		fdt_fixup_crypto_node(blob, 0);
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
	else {
		ccsr_sec_t __iomem *sec;

		sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
	}
#endif

	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
	while (off != -FDT_ERR_NOTFOUND) {
		val = gd->cpu_clk;
		fdt_setprop(blob, off, "clock-frequency", &val, 4);
		off = fdt_node_offset_by_prop_value(blob, off,
						    "device_type", "cpu", 4);
	}

	do_fixup_by_prop_u32(blob, "device_type", "soc",
			     4, "bus-frequency", busclk, 1);

	ft_fixup_enet_phy_connect_type(blob);

#ifdef CONFIG_SYS_NS16550
	do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
			       "clock-frequency", CFG_SYS_NS16550_CLK, 1);
#endif

	sysclk_path = fdt_get_alias(blob, "sysclk");
	if (sysclk_path)
		do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
				     get_board_sys_clk(), 1);
	do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
			       "clock-frequency", get_board_sys_clk(), 1);

#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
#define UBOOT_HEAD_LEN	0x1000
	/*
	 * Reserved memory in SD boot deep sleep case.
	 * Second stage uboot binary and malloc space should be reserved.
	 * If the memory they occupied has not been reserved, then this
	 * space would be used by kernel and overwritten in uboot when
	 * deep sleep resume, which cause deep sleep failed.
	 * Since second uboot binary has a head, that space need to be
	 * reserved either(assuming its size is less than 0x1000).
	 */
	off = fdt_add_mem_rsv(blob, CONFIG_TEXT_BASE - UBOOT_HEAD_LEN,
			      CONFIG_SYS_MONITOR_LEN +
			      CONFIG_SPL_SYS_MALLOC_SIZE + UBOOT_HEAD_LEN);
	if (off < 0)
		printf("Failed to reserve memory for SD boot deep sleep: %s\n",
		       fdt_strerror(off));
#endif

#if defined(CONFIG_FSL_ESDHC)
	fdt_fixup_esdhc(blob, bd);
#endif

	/*
	 * platform bus clock = system bus clock/2
	 * Here busclk = system bus clock
	 * We are using the platform bus clock as 1588 Timer reference
	 * clock source select
	 */
	do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
			       "timer-frequency", busclk / 2, 1);

	/*
	 * clock-freq should change to clock-frequency and
	 * flexcan-v1.0 should change to p1010-flexcan respectively
	 * in the future.
	 */
	do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
			       "clock_freq", busclk / 2, 1);

	do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
			       "clock-frequency", busclk / 2, 1);

	do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
			       "clock-frequency", busclk / 2, 1);

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
	off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
					    CFG_SYS_IFC_ADDR);
	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#else
	off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
					    QSPI0_BASE_ADDR);
	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
	off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
					    DSPI1_BASE_ADDR);
	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#endif
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
d60a2099 WH	2	/*
d60a2099 WH	3	* Copyright 2014 Freescale Semiconductor, Inc.
d60a2099 WH	4	*/
d60a2099 WH	5
d678a59d	6	#include <common.h>
d96c2604	7	#include <clock_legacy.h>
90526e9f	8	#include <net.h>
401d1c4f	9	#include <asm/global_data.h>
b08c8c48	10	#include <linux/libfdt.h>
d60a2099 WH	11	#include <fdt_support.h>
	12	#include <asm/io.h>
	13	#include <asm/processor.h>
	14	#include <asm/arch/clock.h>
	15	#include <linux/ctype.h>
	16	#ifdef CONFIG_FSL_ESDHC
	17	#include <fsl_esdhc.h>
	18	#endif
	19	#include <tsec.h>
0181937f RG	20	#include <asm/arch/immap_ls102xa.h>
0181937f RG	21	#include <fsl_sec.h>
f588b4d2	22	#include <dm.h>
d60a2099 WH	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	void ft_fixup_enet_phy_connect_type(void *fdt)
	27	{
f588b4d2	28	struct udevice *dev;
d60a2099 WH	29	struct tsec_private *priv;
	30	const char enet_path, phy_path;
	31	char enet[16];
	32	char phy[16];
	33	int phy_node;
	34	int i = 0;
d60a2099	35	uint32_t ph;
f588b4d2 BM	36	char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
f588b4d2 BM	37	"ethernet@2d90000" };
d60a2099	38
afe6462d BM	39	for (; i < ARRAY_SIZE(name); i++) {
	40	dev = eth_get_dev_by_name(name[i]);
	41	if (dev) {
	42	sprintf(enet, "ethernet%d", i);
	43	sprintf(phy, "enet%d_rgmii_phy", i);
49a5e42a	44	} else {
d60a2099	45	continue;
49a5e42a	46	}
d60a2099	47
0fd3d911	48	priv = dev_get_priv(dev);
d60a2099 WH	49	if (priv->flags & TSEC_SGMII)
	50	continue;
	51
d60a2099 WH	52	enet_path = fdt_get_alias(fdt, enet);
	53	if (!enet_path)
	54	continue;
	55
d60a2099 WH	56	phy_path = fdt_get_alias(fdt, phy);
	57	if (!phy_path)
	58	continue;
	59
	60	phy_node = fdt_path_offset(fdt, phy_path);
	61	if (phy_node < 0)
	62	continue;
	63
	64	ph = fdt_create_phandle(fdt, phy_node);
	65	if (ph)
	66	do_fixup_by_path_u32(fdt, enet_path,
	67	"phy-handle", ph, 1);
	68
	69	do_fixup_by_path(fdt, enet_path, "phy-connection-type",
	70	phy_string_for_interface(
	71	PHY_INTERFACE_MODE_RGMII_ID),
e784cf1b BS	72	strlen(phy_string_for_interface(
e784cf1b BS	73	PHY_INTERFACE_MODE_RGMII_ID)) + 1,
d60a2099 WH	74	1);
	75	}
	76	}
	77
b75d8dc5	78	void ft_cpu_setup(void blob, struct bd_info bd)
d60a2099 WH	79	{
	80	int off;
	81	int val;
	82	const char *sysclk_path;
6cc04547	83	struct ccsr_gur __iomem gur = (void )(CFG_SYS_FSL_GUTS_ADDR);
0181937f RG	84	unsigned int svr;
0181937f RG	85	svr = in_be32(&gur->svr);
d60a2099 WH	86
	87	unsigned long busclk = get_bus_freq(0);
	88
0181937f RG	89	/* delete crypto node if not on an E-processor */
	90	if (!IS_E_PROCESSOR(svr))
	91	fdt_fixup_crypto_node(blob, 0);
	92	#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
	93	else {
	94	ccsr_sec_t __iomem *sec;
	95
6cc04547	96	sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
0181937f RG	97	fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
	98	}
	99	#endif
	100
d60a2099 WH	101	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
	102	while (off != -FDT_ERR_NOTFOUND) {
	103	val = gd->cpu_clk;
	104	fdt_setprop(blob, off, "clock-frequency", &val, 4);
	105	off = fdt_node_offset_by_prop_value(blob, off,
	106	"device_type", "cpu", 4);
	107	}
	108
	109	do_fixup_by_prop_u32(blob, "device_type", "soc",
b699b01e	110	4, "bus-frequency", busclk, 1);
d60a2099 WH	111
	112	ft_fixup_enet_phy_connect_type(blob);
	113
	114	#ifdef CONFIG_SYS_NS16550
	115	do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
91092132	116	"clock-frequency", CFG_SYS_NS16550_CLK, 1);
d60a2099 WH	117	#endif
	118
	119	sysclk_path = fdt_get_alias(blob, "sysclk");
	120	if (sysclk_path)
	121	do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
2f8a6db5	122	get_board_sys_clk(), 1);
d60a2099	123	do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
2f8a6db5	124	"clock-frequency", get_board_sys_clk(), 1);
d60a2099	125
41ba57d0	126	#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
	127	#define UBOOT_HEAD_LEN 0x1000
	128	/*
	129	* Reserved memory in SD boot deep sleep case.
	130	* Second stage uboot binary and malloc space should be reserved.
	131	* If the memory they occupied has not been reserved, then this
	132	* space would be used by kernel and overwritten in uboot when
	133	* deep sleep resume, which cause deep sleep failed.
	134	* Since second uboot binary has a head, that space need to be
	135	* reserved either(assuming its size is less than 0x1000).
	136	*/
98463903 SG	137	off = fdt_add_mem_rsv(blob, CONFIG_TEXT_BASE - UBOOT_HEAD_LEN,
98463903 SG	138	CONFIG_SYS_MONITOR_LEN +
82e26e0d	139	CONFIG_SPL_SYS_MALLOC_SIZE + UBOOT_HEAD_LEN);
41ba57d0	140	if (off < 0)
	141	printf("Failed to reserve memory for SD boot deep sleep: %s\n",
	142	fdt_strerror(off));
	143	#endif
	144
d60a2099 WH	145	#if defined(CONFIG_FSL_ESDHC)
	146	fdt_fixup_esdhc(blob, bd);
	147	#endif
	148
	149	/*
	150	* platform bus clock = system bus clock/2
	151	* Here busclk = system bus clock
	152	* We are using the platform bus clock as 1588 Timer reference
	153	* clock source select
	154	*/
	155	do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
	156	"timer-frequency", busclk / 2, 1);
	157
	158	/*
	159	* clock-freq should change to clock-frequency and
	160	* flexcan-v1.0 should change to p1010-flexcan respectively
	161	* in the future.
	162	*/
	163	do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
	164	"clock_freq", busclk / 2, 1);
	165
	166	do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
	167	"clock-frequency", busclk / 2, 1);
	168
	169	do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
	170	"clock-frequency", busclk / 2, 1);
33d2e465	171
0cbba8e9	172	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
33d2e465	173	off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
65cc0e2a	174	CFG_SYS_IFC_ADDR);
2105cd04	175	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
33d2e465 AW	176	#else
	177	off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
	178	QSPI0_BASE_ADDR);
2105cd04	179	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
33d2e465 AW	180	off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
33d2e465 AW	181	DSPI1_BASE_ADDR);
2105cd04	182	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
33d2e465	183	#endif
d60a2099	184	}