[thirdparty/u-boot.git] / arch / arm / cpu / armv7 / ls102xa / fsl_ls1_serdes.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/immap_ls102xa.h>
#include <linux/errno.h>
#include <asm/io.h>
#include "fsl_ls1_serdes.h"

#ifdef CONFIG_SYS_FSL_SRDS_1
static u64 serdes1_prtcl_map;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
static u64 serdes2_prtcl_map;
#endif

int is_serdes_configured(enum srds_prtcl device)
{
	u64 ret = 0;

#ifdef CONFIG_SYS_FSL_SRDS_1
	if (!(serdes1_prtcl_map & (1ULL << NONE)))
		fsl_serdes_init();

	ret |= (1ULL << device) & serdes1_prtcl_map;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	if (!(serdes2_prtcl_map & (1ULL << NONE)))
		fsl_serdes_init();

	ret |= (1ULL << device) & serdes2_prtcl_map;
#endif

	return !!ret;
}

int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
	u32 cfg = in_be32(&gur->rcwsr[4]);
	int i;

	switch (sd) {
#ifdef CONFIG_SYS_FSL_SRDS_1
	case FSL_SRDS_1:
		cfg &= RCWSR4_SRDS1_PRTCL_MASK;
		cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
		break;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	case FSL_SRDS_2:
		cfg &= RCWSR4_SRDS2_PRTCL_MASK;
		cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT;
		break;
#endif
	default:
		printf("invalid SerDes%d\n", sd);
		break;
	}
	/* Is serdes enabled at all? */
	if (unlikely(cfg == 0))
		return -ENODEV;

	for (i = 0; i < SRDS_MAX_LANES; i++) {
		if (serdes_get_prtcl(sd, cfg, i) == device)
			return i;
	}

	return -ENODEV;
}

u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{
	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
	u64 serdes_prtcl_map = 0;
	u32 cfg;
	int lane;

	cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
	cfg >>= sd_prctl_shift;
	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);

	if (!is_serdes_prtcl_valid(sd, cfg))
		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);

	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);

		serdes_prtcl_map |= (1ULL << lane_prtcl);
	}

	/* Set the first bit to indicate serdes has been initialized */
	serdes_prtcl_map |= (1ULL << NONE);

	return serdes_prtcl_map;
}

void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
	if (!(serdes1_prtcl_map & (1ULL << NONE)))
		serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
					CFG_SYS_FSL_SERDES_ADDR,
					RCWSR4_SRDS1_PRTCL_MASK,
					RCWSR4_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	if (!(serdes2_prtcl_map & (1ULL << NONE)))
		serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
					CFG_SYS_FSL_SERDES_ADDR +
					FSL_SRDS_2 * 0x1000,
					RCWSR4_SRDS2_PRTCL_MASK,
					RCWSR4_SRDS2_PRTCL_SHIFT);
#endif
}

const char *serdes_clock_to_string(u32 clock)
{
	switch (clock) {
	case SRDS_PLLCR0_RFCK_SEL_100:
		return "100";
	case SRDS_PLLCR0_RFCK_SEL_125:
		return "125";
	default:
		return "100";
	}
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
d60a2099 WH	2	/*
d60a2099 WH	3	* Copyright 2014 Freescale Semiconductor, Inc.
d60a2099 WH	4	*/
d60a2099 WH	5
d678a59d	6	#include <common.h>
d60a2099 WH	7	#include <asm/arch/fsl_serdes.h>
d60a2099 WH	8	#include <asm/arch/immap_ls102xa.h>
1221ce45	9	#include <linux/errno.h>
d60a2099 WH	10	#include <asm/io.h>
	11	#include "fsl_ls1_serdes.h"
	12
	13	#ifdef CONFIG_SYS_FSL_SRDS_1
	14	static u64 serdes1_prtcl_map;
	15	#endif
	16	#ifdef CONFIG_SYS_FSL_SRDS_2
	17	static u64 serdes2_prtcl_map;
	18	#endif
	19
	20	int is_serdes_configured(enum srds_prtcl device)
	21	{
	22	u64 ret = 0;
	23
	24	#ifdef CONFIG_SYS_FSL_SRDS_1
71fe2225 HZ	25	if (!(serdes1_prtcl_map & (1ULL << NONE)))
	26	fsl_serdes_init();
	27
d60a2099 WH	28	ret \|= (1ULL << device) & serdes1_prtcl_map;
	29	#endif
	30	#ifdef CONFIG_SYS_FSL_SRDS_2
71fe2225 HZ	31	if (!(serdes2_prtcl_map & (1ULL << NONE)))
	32	fsl_serdes_init();
	33
d60a2099 WH	34	ret \|= (1ULL << device) & serdes2_prtcl_map;
	35	#endif
	36
	37	return !!ret;
	38	}
	39
	40	int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
	41	{
6cc04547	42	struct ccsr_gur __iomem gur = (void )(CFG_SYS_FSL_GUTS_ADDR);
d60a2099 WH	43	u32 cfg = in_be32(&gur->rcwsr[4]);
	44	int i;
	45
	46	switch (sd) {
	47	#ifdef CONFIG_SYS_FSL_SRDS_1
	48	case FSL_SRDS_1:
	49	cfg &= RCWSR4_SRDS1_PRTCL_MASK;
	50	cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
	51	break;
	52	#endif
	53	#ifdef CONFIG_SYS_FSL_SRDS_2
	54	case FSL_SRDS_2:
	55	cfg &= RCWSR4_SRDS2_PRTCL_MASK;
	56	cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT;
	57	break;
	58	#endif
	59	default:
	60	printf("invalid SerDes%d\n", sd);
	61	break;
	62	}
	63	/* Is serdes enabled at all? */
	64	if (unlikely(cfg == 0))
	65	return -ENODEV;
	66
	67	for (i = 0; i < SRDS_MAX_LANES; i++) {
	68	if (serdes_get_prtcl(sd, cfg, i) == device)
	69	return i;
	70	}
	71
	72	return -ENODEV;
	73	}
	74
	75	u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
	76	{
6cc04547	77	struct ccsr_gur __iomem gur = (void )(CFG_SYS_FSL_GUTS_ADDR);
d60a2099 WH	78	u64 serdes_prtcl_map = 0;
	79	u32 cfg;
	80	int lane;
	81
	82	cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
	83	cfg >>= sd_prctl_shift;
	84	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
	85
	86	if (!is_serdes_prtcl_valid(sd, cfg))
	87	printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
	88
	89	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
	90	enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
	91
	92	serdes_prtcl_map \|= (1ULL << lane_prtcl);
	93	}
	94
71fe2225 HZ	95	/* Set the first bit to indicate serdes has been initialized */
	96	serdes_prtcl_map \|= (1ULL << NONE);
	97
d60a2099 WH	98	return serdes_prtcl_map;
	99	}
	100
	101	void fsl_serdes_init(void)
	102	{
	103	#ifdef CONFIG_SYS_FSL_SRDS_1
71fe2225 HZ	104	if (!(serdes1_prtcl_map & (1ULL << NONE)))
71fe2225 HZ	105	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
6cc04547	106	CFG_SYS_FSL_SERDES_ADDR,
d60a2099 WH	107	RCWSR4_SRDS1_PRTCL_MASK,
	108	RCWSR4_SRDS1_PRTCL_SHIFT);
	109	#endif
	110	#ifdef CONFIG_SYS_FSL_SRDS_2
71fe2225 HZ	111	if (!(serdes2_prtcl_map & (1ULL << NONE)))
71fe2225 HZ	112	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
6cc04547	113	CFG_SYS_FSL_SERDES_ADDR +
d60a2099 WH	114	FSL_SRDS_2 * 0x1000,
	115	RCWSR4_SRDS2_PRTCL_MASK,
	116	RCWSR4_SRDS2_PRTCL_SHIFT);
	117	#endif
	118	}
	119
	120	const char *serdes_clock_to_string(u32 clock)
	121	{
	122	switch (clock) {
	123	case SRDS_PLLCR0_RFCK_SEL_100:
	124	return "100";
	125	case SRDS_PLLCR0_RFCK_SEL_125:
	126	return "125";
	127	default:
	128	return "100";
	129	}
	130	}