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OMAP3/4/5/AM33xx: Correct logic for checking FAT or RAW MMC
[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap-common / lowlevel_init.S
CommitLineData
6b96a20d 1/*
d34efc76
SS
2 * Board specific setup info
3 *
4 * (C) Copyright 2010
5 * Texas Instruments, <www.ti.com>
6 *
7 * Author :
8 * Aneesh V <aneesh@ti.com>
6b96a20d
MK
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
98f92001 29#include <config.h>
508a58fa 30#include <asm/arch/omap.h>
90207b62 31#include <asm/arch/spl.h>
74236aca 32#include <linux/linkage.h>
78f455c0 33
74236aca 34ENTRY(save_boot_params)
8cf686e1
A
35 /*
36 * See if the rom code passed pointer is valid:
37 * It is not valid if it is not in non-secure SRAM
38 * This may happen if you are booting with the help of
39 * debugger
40 */
41 ldr r2, =NON_SECURE_SRAM_START
42 cmp r2, r0
43 bgt 1f
44 ldr r2, =NON_SECURE_SRAM_END
45 cmp r2, r0
46 blt 1f
47
78f455c0
S
48 /*
49 * store the boot params passed from rom code or saved
50 * and passed by SPL
51 */
52 cmp r0, #0
53 beq 1f
54 ldr r1, =boot_params
55 str r0, [r1]
56#ifdef CONFIG_SPL_BUILD
8e1b836e 57 /* Store the boot device in spl_boot_device */
78f455c0 58 ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
8cf686e1 59 and r2, #BOOT_DEVICE_MASK
78f455c0 60 ldr r3, =boot_params
8e1b836e 61 strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
8cf686e1 62
c3d2c24f
TR
63 /*
64 * boot mode is only valid for device that can be raw or FAT booted.
65 * in other cases it may be fatal to look. While platforms differ
66 * in the values used for each MMC slot, they are contiguous.
67 */
68 cmp r2, #MMC_BOOT_DEVICES_START
78f455c0 69 blt 2f
c3d2c24f 70 cmp r2, #MMC_BOOT_DEVICES_END
78f455c0 71 bgt 2f
6abbe744 72 /* Store the boot mode (raw/FAT) in omap_bootmode */
8cf686e1
A
73 ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
74 ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr
75 ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode
508a58fa 76 ldr r3, =omap_bootmode
8cf686e1 77 str r2, [r3]
78f455c0
S
78#endif
792:
80 ldrb r2, [r0, #CH_FLAGS_OFFSET]
81 ldr r3, =boot_params
82 strb r2, [r3, #CH_FLAGS_OFFSET]
8cf686e1
A
831:
84 bx lr
74236aca 85ENDPROC(save_boot_params)
78f455c0 86
74236aca 87ENTRY(set_pl310_ctrl_reg)
8b457fa8
A
88 PUSH {r4-r11, lr} @ save registers - ROM code may pollute
89 @ our registers
90 LDR r12, =0x102 @ Set PL310 control register - value in R0
91 .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
92 @ call ROM Code API to set control register
93 POP {r4-r11, pc}
74236aca 94ENDPROC(set_pl310_ctrl_reg)