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Commit | Line | Data |
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508a58fa S |
1 | /* |
2 | * | |
3 | * Functions for omap5 based boards. | |
4 | * | |
5 | * (C) Copyright 2011 | |
6 | * Texas Instruments, <www.ti.com> | |
7 | * | |
8 | * Author : | |
9 | * Aneesh V <aneesh@ti.com> | |
10 | * Steve Sakoman <steve@sakoman.com> | |
11 | * Sricharan <r.sricharan@ti.com> | |
12 | * | |
1a459660 | 13 | * SPDX-License-Identifier: GPL-2.0+ |
508a58fa S |
14 | */ |
15 | #include <common.h> | |
16 | #include <asm/armv7.h> | |
17 | #include <asm/arch/cpu.h> | |
18 | #include <asm/arch/sys_proto.h> | |
af1d002f | 19 | #include <asm/arch/clock.h> |
1ace4022 | 20 | #include <linux/sizes.h> |
508a58fa S |
21 | #include <asm/utils.h> |
22 | #include <asm/arch/gpio.h> | |
784ab7c5 | 23 | #include <asm/emif.h> |
f92f2277 | 24 | #include <asm/omap_common.h> |
508a58fa S |
25 | |
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
f92f2277 | 28 | u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; |
508a58fa | 29 | |
87bd05d7 | 30 | static struct gpio_bank gpio_bank_54xx[8] = { |
508a58fa S |
31 | { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX }, |
32 | { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX }, | |
33 | { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX }, | |
34 | { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX }, | |
35 | { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX }, | |
36 | { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX }, | |
87bd05d7 AL |
37 | { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX }, |
38 | { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX }, | |
508a58fa S |
39 | }; |
40 | ||
41 | const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; | |
42 | ||
1f68451c LV |
43 | void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) |
44 | { | |
45 | int i; | |
46 | struct pad_conf_entry *pad = (struct pad_conf_entry *)array; | |
47 | ||
48 | for (i = 0; i < size; i++, pad++) | |
49 | writel(pad->val, base + pad->offset); | |
50 | } | |
51 | ||
508a58fa | 52 | #ifdef CONFIG_SPL_BUILD |
eb4e18e8 LV |
53 | /* LPDDR2 specific IO settings */ |
54 | static void io_settings_lpddr2(void) | |
55 | { | |
ef1697e9 LV |
56 | const struct ctrl_ioregs *ioregs; |
57 | ||
58 | get_ioregs(&ioregs); | |
59 | writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); | |
60 | writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); | |
61 | writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); | |
62 | writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); | |
63 | writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); | |
64 | writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); | |
65 | writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); | |
66 | writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); | |
67 | writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); | |
eb4e18e8 LV |
68 | } |
69 | ||
70 | /* DDR3 specific IO settings */ | |
71 | static void io_settings_ddr3(void) | |
72 | { | |
73 | u32 io_settings = 0; | |
ef1697e9 | 74 | const struct ctrl_ioregs *ioregs; |
eb4e18e8 | 75 | |
ef1697e9 LV |
76 | get_ioregs(&ioregs); |
77 | writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); | |
78 | writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); | |
79 | writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); | |
eb4e18e8 | 80 | |
ef1697e9 LV |
81 | writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0); |
82 | writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); | |
83 | writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); | |
eb4e18e8 | 84 | |
ef1697e9 LV |
85 | writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); |
86 | writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); | |
a5c5c5b5 LV |
87 | |
88 | if (!is_dra7xx()) { | |
89 | writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); | |
90 | writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); | |
91 | } | |
eb4e18e8 LV |
92 | |
93 | /* omap5432 does not use lpddr2 */ | |
ef1697e9 | 94 | writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); |
eb4e18e8 | 95 | |
ef1697e9 LV |
96 | writel(ioregs->ctrl_emif_sdram_config_ext, |
97 | (*ctrl)->control_emif1_sdram_config_ext); | |
a5c5c5b5 LV |
98 | if (!is_dra72x()) |
99 | writel(ioregs->ctrl_emif_sdram_config_ext, | |
100 | (*ctrl)->control_emif2_sdram_config_ext); | |
eb4e18e8 | 101 | |
92b0482c S |
102 | if (is_omap54xx()) { |
103 | /* Disable DLL select */ | |
104 | io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) | |
eb4e18e8 | 105 | & 0xFFEFFFFF); |
92b0482c S |
106 | writel(io_settings, |
107 | (*ctrl)->control_port_emif1_sdram_config); | |
eb4e18e8 | 108 | |
92b0482c | 109 | io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) |
eb4e18e8 | 110 | & 0xFFEFFFFF); |
92b0482c S |
111 | writel(io_settings, |
112 | (*ctrl)->control_port_emif2_sdram_config); | |
113 | } else { | |
114 | writel(ioregs->ctrl_ddr_ctrl_ext_0, | |
115 | (*ctrl)->control_ddr_control_ext_0); | |
116 | } | |
eb4e18e8 LV |
117 | } |
118 | ||
508a58fa S |
119 | /* |
120 | * Some tuning of IOs for optimal power and performance | |
121 | */ | |
122 | void do_io_settings(void) | |
123 | { | |
6ad8d67d | 124 | u32 io_settings = 0, mask = 0; |
6ad8d67d S |
125 | |
126 | /* Impedance settings EMMC, C2C 1,2, hsi2 */ | |
127 | mask = (ds_mask << 2) | (ds_mask << 8) | | |
128 | (ds_mask << 16) | (ds_mask << 18); | |
c43c8339 | 129 | io_settings = readl((*ctrl)->control_smart1io_padconf_0) & |
6ad8d67d S |
130 | (~mask); |
131 | io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) | | |
132 | (ds_45_ohm << 18) | (ds_60_ohm << 2); | |
c43c8339 | 133 | writel(io_settings, (*ctrl)->control_smart1io_padconf_0); |
6ad8d67d S |
134 | |
135 | /* Impedance settings Mcspi2 */ | |
136 | mask = (ds_mask << 30); | |
c43c8339 | 137 | io_settings = readl((*ctrl)->control_smart1io_padconf_1) & |
6ad8d67d S |
138 | (~mask); |
139 | io_settings |= (ds_60_ohm << 30); | |
c43c8339 | 140 | writel(io_settings, (*ctrl)->control_smart1io_padconf_1); |
6ad8d67d S |
141 | |
142 | /* Impedance settings C2C 3,4 */ | |
143 | mask = (ds_mask << 14) | (ds_mask << 16); | |
c43c8339 | 144 | io_settings = readl((*ctrl)->control_smart1io_padconf_2) & |
6ad8d67d S |
145 | (~mask); |
146 | io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16); | |
c43c8339 | 147 | writel(io_settings, (*ctrl)->control_smart1io_padconf_2); |
6ad8d67d S |
148 | |
149 | /* Slew rate settings EMMC, C2C 1,2 */ | |
150 | mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18); | |
c43c8339 | 151 | io_settings = readl((*ctrl)->control_smart2io_padconf_0) & |
6ad8d67d S |
152 | (~mask); |
153 | io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18); | |
c43c8339 | 154 | writel(io_settings, (*ctrl)->control_smart2io_padconf_0); |
6ad8d67d S |
155 | |
156 | /* Slew rate settings hsi2, Mcspi2 */ | |
157 | mask = (sc_mask << 24) | (sc_mask << 28); | |
c43c8339 | 158 | io_settings = readl((*ctrl)->control_smart2io_padconf_1) & |
6ad8d67d S |
159 | (~mask); |
160 | io_settings |= (sc_fast << 28) | (sc_fast << 24); | |
c43c8339 | 161 | writel(io_settings, (*ctrl)->control_smart2io_padconf_1); |
6ad8d67d S |
162 | |
163 | /* Slew rate settings C2C 3,4 */ | |
164 | mask = (sc_mask << 16) | (sc_mask << 18); | |
c43c8339 | 165 | io_settings = readl((*ctrl)->control_smart2io_padconf_2) & |
6ad8d67d S |
166 | (~mask); |
167 | io_settings |= (sc_na << 16) | (sc_na << 18); | |
c43c8339 | 168 | writel(io_settings, (*ctrl)->control_smart2io_padconf_2); |
6ad8d67d S |
169 | |
170 | /* impedance and slew rate settings for usb */ | |
171 | mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) | | |
172 | (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14); | |
c43c8339 | 173 | io_settings = readl((*ctrl)->control_smart3io_padconf_1) & |
6ad8d67d S |
174 | (~mask); |
175 | io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) | | |
176 | (ds_60_ohm << 23) | (sc_fast << 20) | | |
177 | (sc_fast << 17) | (sc_fast << 14); | |
c43c8339 | 178 | writel(io_settings, (*ctrl)->control_smart3io_padconf_1); |
6ad8d67d | 179 | |
9ca8bfea | 180 | if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) |
eb4e18e8 LV |
181 | io_settings_lpddr2(); |
182 | else | |
183 | io_settings_ddr3(); | |
508a58fa | 184 | } |
d4d986ee LV |
185 | |
186 | static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { | |
187 | {0x45, 0x1}, /* 12 MHz */ | |
188 | {-1, -1}, /* 13 MHz */ | |
189 | {0x63, 0x2}, /* 16.8 MHz */ | |
190 | {0x57, 0x2}, /* 19.2 MHz */ | |
191 | {0x20, 0x1}, /* 26 MHz */ | |
192 | {-1, -1}, /* 27 MHz */ | |
193 | {0x41, 0x3} /* 38.4 MHz */ | |
194 | }; | |
195 | ||
196 | void srcomp_enable(void) | |
197 | { | |
198 | u32 srcomp_value, mul_factor, div_factor, clk_val, i; | |
199 | u32 sysclk_ind = get_sys_clk_index(); | |
200 | u32 omap_rev = omap_revision(); | |
201 | ||
e9d6cd04 LV |
202 | if (!is_omap54xx()) |
203 | return; | |
204 | ||
d4d986ee LV |
205 | mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; |
206 | div_factor = srcomp_parameters[sysclk_ind].divide_factor; | |
207 | ||
208 | for (i = 0; i < 4; i++) { | |
209 | srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); | |
210 | srcomp_value &= | |
211 | ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK); | |
212 | srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | | |
213 | (div_factor << DIVIDE_FACTOR_XS_SHIFT); | |
214 | writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4); | |
215 | } | |
216 | ||
217 | if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) { | |
218 | clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); | |
219 | clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; | |
220 | writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); | |
221 | ||
222 | for (i = 0; i < 4; i++) { | |
223 | srcomp_value = | |
224 | readl((*ctrl)->control_srcomp_north_side + i*4); | |
225 | srcomp_value &= ~PWRDWN_XS_MASK; | |
226 | writel(srcomp_value, | |
227 | (*ctrl)->control_srcomp_north_side + i*4); | |
228 | ||
229 | while (((readl((*ctrl)->control_srcomp_north_side + i*4) | |
230 | & SRCODE_READ_XS_MASK) >> | |
231 | SRCODE_READ_XS_SHIFT) == 0) | |
232 | ; | |
233 | ||
234 | srcomp_value = | |
235 | readl((*ctrl)->control_srcomp_north_side + i*4); | |
236 | srcomp_value &= ~OVERRIDE_XS_MASK; | |
237 | writel(srcomp_value, | |
238 | (*ctrl)->control_srcomp_north_side + i*4); | |
239 | } | |
240 | } else { | |
241 | srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup); | |
242 | srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK | | |
243 | DIVIDE_FACTOR_XS_MASK); | |
244 | srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | | |
245 | (div_factor << DIVIDE_FACTOR_XS_SHIFT); | |
246 | writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); | |
247 | ||
248 | for (i = 0; i < 4; i++) { | |
249 | srcomp_value = | |
250 | readl((*ctrl)->control_srcomp_north_side + i*4); | |
251 | srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; | |
252 | writel(srcomp_value, | |
253 | (*ctrl)->control_srcomp_north_side + i*4); | |
254 | ||
255 | srcomp_value = | |
256 | readl((*ctrl)->control_srcomp_north_side + i*4); | |
257 | srcomp_value &= ~OVERRIDE_XS_MASK; | |
258 | writel(srcomp_value, | |
259 | (*ctrl)->control_srcomp_north_side + i*4); | |
260 | } | |
261 | ||
262 | srcomp_value = | |
263 | readl((*ctrl)->control_srcomp_east_side_wkup); | |
264 | srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; | |
265 | writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); | |
266 | ||
267 | srcomp_value = | |
268 | readl((*ctrl)->control_srcomp_east_side_wkup); | |
269 | srcomp_value &= ~OVERRIDE_XS_MASK; | |
270 | writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); | |
271 | ||
272 | clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); | |
273 | clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; | |
274 | writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); | |
275 | ||
276 | clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl); | |
277 | clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; | |
278 | writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl); | |
279 | ||
280 | for (i = 0; i < 4; i++) { | |
281 | while (((readl((*ctrl)->control_srcomp_north_side + i*4) | |
282 | & SRCODE_READ_XS_MASK) >> | |
283 | SRCODE_READ_XS_SHIFT) == 0) | |
284 | ; | |
285 | ||
286 | srcomp_value = | |
287 | readl((*ctrl)->control_srcomp_north_side + i*4); | |
288 | srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; | |
289 | writel(srcomp_value, | |
290 | (*ctrl)->control_srcomp_north_side + i*4); | |
291 | } | |
292 | ||
293 | while (((readl((*ctrl)->control_srcomp_east_side_wkup) & | |
294 | SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0) | |
295 | ; | |
296 | ||
297 | srcomp_value = | |
298 | readl((*ctrl)->control_srcomp_east_side_wkup); | |
299 | srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; | |
300 | writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); | |
301 | } | |
302 | } | |
508a58fa S |
303 | #endif |
304 | ||
784ab7c5 LV |
305 | void config_data_eye_leveling_samples(u32 emif_base) |
306 | { | |
6c70935d S |
307 | const struct ctrl_ioregs *ioregs; |
308 | ||
309 | get_ioregs(&ioregs); | |
310 | ||
784ab7c5 LV |
311 | /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ |
312 | if (emif_base == EMIF1_BASE) | |
6c70935d S |
313 | writel(ioregs->ctrl_emif_sdram_config_ext_final, |
314 | (*ctrl)->control_emif1_sdram_config_ext); | |
784ab7c5 | 315 | else if (emif_base == EMIF2_BASE) |
6c70935d S |
316 | writel(ioregs->ctrl_emif_sdram_config_ext_final, |
317 | (*ctrl)->control_emif2_sdram_config_ext); | |
784ab7c5 LV |
318 | } |
319 | ||
fc7368ec NM |
320 | void init_cpu_configuration(void) |
321 | { | |
322 | u32 l2actlr; | |
323 | ||
324 | asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr)); | |
325 | /* | |
326 | * L2ACTLR: Ensure to enable the following: | |
327 | * 3: Disable clean/evict push to external | |
328 | * 4: Disable WriteUnique and WriteLineUnique transactions from master | |
329 | * 8: Disable DVM/CMO message broadcast | |
330 | */ | |
331 | l2actlr |= 0x118; | |
332 | omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr); | |
333 | } | |
334 | ||
508a58fa S |
335 | void init_omap_revision(void) |
336 | { | |
337 | /* | |
338 | * For some of the ES2/ES1 boards ID_CODE is not reliable: | |
339 | * Also, ES1 and ES2 have different ARM revisions | |
340 | * So use ARM revision for identification | |
341 | */ | |
342 | unsigned int rev = cortex_rev(); | |
343 | ||
eed7c0f7 S |
344 | switch (readl(CONTROL_ID_CODE)) { |
345 | case OMAP5430_CONTROL_ID_CODE_ES1_0: | |
346 | *omap_si_rev = OMAP5430_ES1_0; | |
347 | if (rev == MIDR_CORTEX_A15_R2P2) | |
348 | *omap_si_rev = OMAP5430_ES2_0; | |
349 | break; | |
350 | case OMAP5432_CONTROL_ID_CODE_ES1_0: | |
351 | *omap_si_rev = OMAP5432_ES1_0; | |
352 | if (rev == MIDR_CORTEX_A15_R2P2) | |
353 | *omap_si_rev = OMAP5432_ES2_0; | |
354 | break; | |
355 | case OMAP5430_CONTROL_ID_CODE_ES2_0: | |
356 | *omap_si_rev = OMAP5430_ES2_0; | |
357 | break; | |
358 | case OMAP5432_CONTROL_ID_CODE_ES2_0: | |
359 | *omap_si_rev = OMAP5432_ES2_0; | |
cdd50a8d | 360 | break; |
de62688b LV |
361 | case DRA752_CONTROL_ID_CODE_ES1_0: |
362 | *omap_si_rev = DRA752_ES1_0; | |
363 | break; | |
3ac8c0bf NM |
364 | case DRA752_CONTROL_ID_CODE_ES1_1: |
365 | *omap_si_rev = DRA752_ES1_1; | |
366 | break; | |
ee77a238 LV |
367 | case DRA722_CONTROL_ID_CODE_ES1_0: |
368 | *omap_si_rev = DRA722_ES1_0; | |
369 | break; | |
508a58fa | 370 | default: |
087189fb | 371 | *omap_si_rev = OMAP5430_SILICON_ID_INVALID; |
508a58fa | 372 | } |
fc7368ec | 373 | init_cpu_configuration(); |
508a58fa | 374 | } |
0696473b S |
375 | |
376 | void reset_cpu(ulong ignored) | |
377 | { | |
378 | u32 omap_rev = omap_revision(); | |
379 | ||
380 | /* | |
381 | * WARM reset is not functional in case of OMAP5430 ES1.0 soc. | |
382 | * So use cold reset in case instead. | |
383 | */ | |
384 | if (omap_rev == OMAP5430_ES1_0) | |
d4e4129c | 385 | writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl); |
0696473b | 386 | else |
d4e4129c LV |
387 | writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl); |
388 | } | |
389 | ||
390 | u32 warm_reset(void) | |
391 | { | |
392 | return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK; | |
0696473b | 393 | } |
0b1b60c7 LV |
394 | |
395 | void setup_warmreset_time(void) | |
396 | { | |
397 | u32 rst_time, rst_val; | |
398 | ||
399 | #ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC | |
400 | rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC; | |
401 | #else | |
402 | rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC; | |
403 | #endif | |
404 | rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT; | |
405 | ||
406 | if (rst_time > RSTTIME1_MASK) | |
407 | rst_time = RSTTIME1_MASK; | |
408 | ||
409 | rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK; | |
410 | rst_val |= rst_time; | |
411 | writel(rst_val, (*prcm)->prm_rsttime); | |
412 | } | |
5f603761 PR |
413 | |
414 | void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, | |
415 | u32 cpu_rev_comb, u32 cpu_variant, | |
416 | u32 cpu_rev) | |
417 | { | |
418 | omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl); | |
419 | } |