[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap5 / hwinit.c

/*
 *
 * Functions for omap5 based boards.
 *
 * (C) Copyright 2011
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *	Aneesh V	<aneesh@ti.com>
 *	Steve Sakoman	<steve@sakoman.com>
 *	Sricharan	<r.sricharan@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <linux/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include <asm/omap_common.h>

DECLARE_GLOBAL_DATA_PTR;

u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;

#ifndef CONFIG_DM_GPIO
static struct gpio_bank gpio_bank_54xx[8] = {
	{ (void *)OMAP54XX_GPIO1_BASE },
	{ (void *)OMAP54XX_GPIO2_BASE },
	{ (void *)OMAP54XX_GPIO3_BASE },
	{ (void *)OMAP54XX_GPIO4_BASE },
	{ (void *)OMAP54XX_GPIO5_BASE },
	{ (void *)OMAP54XX_GPIO6_BASE },
	{ (void *)OMAP54XX_GPIO7_BASE },
	{ (void *)OMAP54XX_GPIO8_BASE },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
#endif

void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
{
	int i;
	struct pad_conf_entry *pad = (struct pad_conf_entry *)array;

	for (i = 0; i < size; i++, pad++)
		writel(pad->val, base + pad->offset);
}

#ifdef CONFIG_SPL_BUILD
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
}

/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
	u32 io_settings = 0;
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);
	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);

	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);

	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);

	if (!is_dra7xx()) {
		writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
		writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	}

	/* omap5432 does not use lpddr2 */
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);

	writel(ioregs->ctrl_emif_sdram_config_ext,
	       (*ctrl)->control_emif1_sdram_config_ext);
	if (!is_dra72x())
		writel(ioregs->ctrl_emif_sdram_config_ext,
		       (*ctrl)->control_emif2_sdram_config_ext);

	if (is_omap54xx()) {
		/* Disable DLL select */
		io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
							& 0xFFEFFFFF);
		writel(io_settings,
			(*ctrl)->control_port_emif1_sdram_config);

		io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
							& 0xFFEFFFFF);
		writel(io_settings,
			(*ctrl)->control_port_emif2_sdram_config);
	} else {
		writel(ioregs->ctrl_ddr_ctrl_ext_0,
				(*ctrl)->control_ddr_control_ext_0);
	}
}

/*
 * Some tuning of IOs for optimal power and performance
 */
void do_io_settings(void)
{
	u32 io_settings = 0, mask = 0;
	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;

	/* Impedance settings EMMC, C2C 1,2, hsi2 */
	mask = (ds_mask << 2) | (ds_mask << 8) |
		(ds_mask << 16) | (ds_mask << 18);
	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
				(~mask);
	io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
			(ds_45_ohm << 18) | (ds_60_ohm << 2);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_0);

	/* Impedance settings Mcspi2 */
	mask = (ds_mask << 30);
	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
			(~mask);
	io_settings |= (ds_60_ohm << 30);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_1);

	/* Impedance settings C2C 3,4 */
	mask = (ds_mask << 14) | (ds_mask << 16);
	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
			(~mask);
	io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_2);

	/* Slew rate settings EMMC, C2C 1,2 */
	mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
			(~mask);
	io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_0);

	/* Slew rate settings hsi2, Mcspi2 */
	mask = (sc_mask << 24) | (sc_mask << 28);
	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
			(~mask);
	io_settings |= (sc_fast << 28) | (sc_fast << 24);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_1);

	/* Slew rate settings C2C 3,4 */
	mask = (sc_mask << 16) | (sc_mask << 18);
	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
			(~mask);
	io_settings |= (sc_na << 16) | (sc_na << 18);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_2);

	/* impedance and slew rate settings for usb */
	mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
		(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
			(~mask);
	io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
		       (ds_60_ohm << 23) | (sc_fast << 20) |
		       (sc_fast << 17) | (sc_fast << 14);
	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);

	if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
		io_settings_lpddr2();
	else
		io_settings_ddr3();
}

static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
	{0x45, 0x1},	/* 12 MHz   */
	{-1, -1},	/* 13 MHz   */
	{0x63, 0x2},	/* 16.8 MHz */
	{0x57, 0x2},	/* 19.2 MHz */
	{0x20, 0x1},	/* 26 MHz   */
	{-1, -1},	/* 27 MHz   */
	{0x41, 0x3}	/* 38.4 MHz */
};

void srcomp_enable(void)
{
	u32 srcomp_value, mul_factor, div_factor, clk_val, i;
	u32 sysclk_ind	= get_sys_clk_index();
	u32 omap_rev	= omap_revision();

	if (!is_omap54xx())
		return;

	mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
	div_factor = srcomp_parameters[sysclk_ind].divide_factor;

	for (i = 0; i < 4; i++) {
		srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
		srcomp_value &=
			~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
			(div_factor << DIVIDE_FACTOR_XS_SHIFT);
		writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
	}

	if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);

		for (i = 0; i < 4; i++) {
			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~PWRDWN_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);

			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
				& SRCODE_READ_XS_MASK) >>
				SRCODE_READ_XS_SHIFT) == 0)
				;

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~OVERRIDE_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}
	} else {
		srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
				  DIVIDE_FACTOR_XS_MASK);
		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
				(div_factor << DIVIDE_FACTOR_XS_SHIFT);
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		for (i = 0; i < 4; i++) {
			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~OVERRIDE_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~OVERRIDE_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);

		clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);

		for (i = 0; i < 4; i++) {
			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
				& SRCODE_READ_XS_MASK) >>
				SRCODE_READ_XS_SHIFT) == 0)
				;

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}

		while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
			SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
			;

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	}
}
#endif

void config_data_eye_leveling_samples(u32 emif_base)
{
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);

	/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
	if (emif_base == EMIF1_BASE)
		writel(ioregs->ctrl_emif_sdram_config_ext_final,
		       (*ctrl)->control_emif1_sdram_config_ext);
	else if (emif_base == EMIF2_BASE)
		writel(ioregs->ctrl_emif_sdram_config_ext_final,
		       (*ctrl)->control_emif2_sdram_config_ext);
}

void init_cpu_configuration(void)
{
	u32 l2actlr;

	asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
	/*
	 * L2ACTLR: Ensure to enable the following:
	 * 3: Disable clean/evict push to external
	 * 4: Disable WriteUnique and WriteLineUnique transactions from master
	 * 8: Disable DVM/CMO message broadcast
	 */
	l2actlr |= 0x118;
	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
}

void init_omap_revision(void)
{
	/*
	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
	 * Also, ES1 and ES2 have different ARM revisions
	 * So use ARM revision for identification
	 */
	unsigned int rev = cortex_rev();

	switch (readl(CONTROL_ID_CODE)) {
	case OMAP5430_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = OMAP5430_ES1_0;
		if (rev == MIDR_CORTEX_A15_R2P2)
			*omap_si_rev = OMAP5430_ES2_0;
		break;
	case OMAP5432_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = OMAP5432_ES1_0;
		if (rev == MIDR_CORTEX_A15_R2P2)
			*omap_si_rev = OMAP5432_ES2_0;
		break;
	case OMAP5430_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = OMAP5430_ES2_0;
		break;
	case OMAP5432_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = OMAP5432_ES2_0;
		break;
	case DRA752_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = DRA752_ES1_0;
		break;
	case DRA752_CONTROL_ID_CODE_ES1_1:
		*omap_si_rev = DRA752_ES1_1;
		break;
	case DRA752_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = DRA752_ES2_0;
		break;
	case DRA722_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = DRA722_ES1_0;
		break;
	default:
		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
	}
	init_cpu_configuration();
}

void omap_die_id(unsigned int *die_id)
{
	die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
	die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
	die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
	die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
}

void reset_cpu(ulong ignored)
{
	u32 omap_rev = omap_revision();

	/*
	 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
	 * So use cold reset in case instead.
	 */
	if (omap_rev == OMAP5430_ES1_0)
		writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
	else
		writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
}

u32 warm_reset(void)
{
	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}

void setup_warmreset_time(void)
{
	u32 rst_time, rst_val;

#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
	rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
#else
	rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
#endif
	rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;

	if (rst_time > RSTTIME1_MASK)
		rst_time = RSTTIME1_MASK;

	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
	rst_val |= rst_time;
	writel(rst_val, (*prcm)->prm_rsttime);
}

void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
				 u32 cpu_rev_comb, u32 cpu_variant,
				 u32 cpu_rev)
{
	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
}

void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
			  u32 cpu_variant, u32 cpu_rev)
{

#ifdef CONFIG_ARM_ERRATA_801819
	/*
	 * DRA72x processors are uniprocessors and DONOT have
	 * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
	 * Extensions) Hence the erratum workaround is not applicable for
	 * DRA72x processors.
	 */
	if (is_dra72x())
		acr &= ~((0x3 << 23) | (0x3 << 25));
#endif
	omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
}
Commit	Line	Data
508a58fa S	1	/*
	2	*
	3	* Functions for omap5 based boards.
	4	*
	5	* (C) Copyright 2011
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Aneesh V <aneesh@ti.com>
	10	* Steve Sakoman <steve@sakoman.com>
	11	* Sricharan <r.sricharan@ti.com>
	12	*
1a459660	13	* SPDX-License-Identifier: GPL-2.0+
508a58fa S	14	*/
	15	#include <common.h>
	16	#include <asm/armv7.h>
	17	#include <asm/arch/cpu.h>
	18	#include <asm/arch/sys_proto.h>
af1d002f	19	#include <asm/arch/clock.h>
1ace4022	20	#include <linux/sizes.h>
508a58fa S	21	#include <asm/utils.h>
508a58fa S	22	#include <asm/arch/gpio.h>
784ab7c5	23	#include <asm/emif.h>
f92f2277	24	#include <asm/omap_common.h>
508a58fa S	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
f92f2277	28	u32 const omap_si_rev = (u32 )OMAP_SRAM_SCRATCH_OMAP_REV;
508a58fa	29
0a9e3405	30	#ifndef CONFIG_DM_GPIO
87bd05d7	31	static struct gpio_bank gpio_bank_54xx[8] = {
0a9e3405 TR	32	{ (void *)OMAP54XX_GPIO1_BASE },
	33	{ (void *)OMAP54XX_GPIO2_BASE },
	34	{ (void *)OMAP54XX_GPIO3_BASE },
	35	{ (void *)OMAP54XX_GPIO4_BASE },
	36	{ (void *)OMAP54XX_GPIO5_BASE },
	37	{ (void *)OMAP54XX_GPIO6_BASE },
	38	{ (void *)OMAP54XX_GPIO7_BASE },
	39	{ (void *)OMAP54XX_GPIO8_BASE },
508a58fa S	40	};
	41
	42	const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
0a9e3405	43	#endif
508a58fa	44
1f68451c LV	45	void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
	46	{
	47	int i;
	48	struct pad_conf_entry pad = (struct pad_conf_entry )array;
	49
	50	for (i = 0; i < size; i++, pad++)
	51	writel(pad->val, base + pad->offset);
	52	}
	53
508a58fa	54	#ifdef CONFIG_SPL_BUILD
eb4e18e8 LV	55	/* LPDDR2 specific IO settings */
	56	static void io_settings_lpddr2(void)
	57	{
ef1697e9 LV	58	const struct ctrl_ioregs *ioregs;
	59
	60	get_ioregs(&ioregs);
	61	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	62	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
	63	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	64	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
	65	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
	66	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	67	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	68	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	69	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
eb4e18e8 LV	70	}
	71
	72	/* DDR3 specific IO settings */
	73	static void io_settings_ddr3(void)
	74	{
	75	u32 io_settings = 0;
ef1697e9	76	const struct ctrl_ioregs *ioregs;
eb4e18e8	77
ef1697e9 LV	78	get_ioregs(&ioregs);
	79	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
	80	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	81	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
eb4e18e8	82
ef1697e9 LV	83	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
	84	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	85	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
eb4e18e8	86
ef1697e9 LV	87	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
ef1697e9 LV	88	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
a5c5c5b5 LV	89
	90	if (!is_dra7xx()) {
	91	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
	92	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	93	}
eb4e18e8 LV	94
eb4e18e8 LV	95	/* omap5432 does not use lpddr2 */
ef1697e9	96	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
eb4e18e8	97
ef1697e9 LV	98	writel(ioregs->ctrl_emif_sdram_config_ext,
ef1697e9 LV	99	(*ctrl)->control_emif1_sdram_config_ext);
a5c5c5b5 LV	100	if (!is_dra72x())
	101	writel(ioregs->ctrl_emif_sdram_config_ext,
	102	(*ctrl)->control_emif2_sdram_config_ext);
eb4e18e8	103
92b0482c S	104	if (is_omap54xx()) {
	105	/* Disable DLL select */
	106	io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
eb4e18e8	107	& 0xFFEFFFFF);
92b0482c S	108	writel(io_settings,
92b0482c S	109	(*ctrl)->control_port_emif1_sdram_config);
eb4e18e8	110
92b0482c	111	io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
eb4e18e8	112	& 0xFFEFFFFF);
92b0482c S	113	writel(io_settings,
	114	(*ctrl)->control_port_emif2_sdram_config);
	115	} else {
	116	writel(ioregs->ctrl_ddr_ctrl_ext_0,
	117	(*ctrl)->control_ddr_control_ext_0);
	118	}
eb4e18e8 LV	119	}
eb4e18e8 LV	120
508a58fa S	121	/*
	122	* Some tuning of IOs for optimal power and performance
	123	*/
	124	void do_io_settings(void)
	125	{
6ad8d67d	126	u32 io_settings = 0, mask = 0;
7c352cd3	127	struct emif_reg_struct emif = (struct emif_reg_struct )EMIF1_BASE;
6ad8d67d S	128
	129	/* Impedance settings EMMC, C2C 1,2, hsi2 */
	130	mask = (ds_mask << 2) \| (ds_mask << 8) \|
	131	(ds_mask << 16) \| (ds_mask << 18);
c43c8339	132	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
6ad8d67d S	133	(~mask);
	134	io_settings \|= (ds_60_ohm << 8) \| (ds_45_ohm << 16) \|
	135	(ds_45_ohm << 18) \| (ds_60_ohm << 2);
c43c8339	136	writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
6ad8d67d S	137
	138	/* Impedance settings Mcspi2 */
	139	mask = (ds_mask << 30);
c43c8339	140	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
6ad8d67d S	141	(~mask);
6ad8d67d S	142	io_settings \|= (ds_60_ohm << 30);
c43c8339	143	writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
6ad8d67d S	144
	145	/* Impedance settings C2C 3,4 */
	146	mask = (ds_mask << 14) \| (ds_mask << 16);
c43c8339	147	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
6ad8d67d S	148	(~mask);
6ad8d67d S	149	io_settings \|= (ds_45_ohm << 14) \| (ds_45_ohm << 16);
c43c8339	150	writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
6ad8d67d S	151
	152	/* Slew rate settings EMMC, C2C 1,2 */
	153	mask = (sc_mask << 8) \| (sc_mask << 16) \| (sc_mask << 18);
c43c8339	154	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
6ad8d67d S	155	(~mask);
6ad8d67d S	156	io_settings \|= (sc_fast << 8) \| (sc_na << 16) \| (sc_na << 18);
c43c8339	157	writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
6ad8d67d S	158
	159	/* Slew rate settings hsi2, Mcspi2 */
	160	mask = (sc_mask << 24) \| (sc_mask << 28);
c43c8339	161	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
6ad8d67d S	162	(~mask);
6ad8d67d S	163	io_settings \|= (sc_fast << 28) \| (sc_fast << 24);
c43c8339	164	writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
6ad8d67d S	165
	166	/* Slew rate settings C2C 3,4 */
	167	mask = (sc_mask << 16) \| (sc_mask << 18);
c43c8339	168	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
6ad8d67d S	169	(~mask);
6ad8d67d S	170	io_settings \|= (sc_na << 16) \| (sc_na << 18);
c43c8339	171	writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
6ad8d67d S	172
	173	/* impedance and slew rate settings for usb */
	174	mask = (usb_i_mask << 29) \| (usb_i_mask << 26) \| (usb_i_mask << 23) \|
	175	(usb_i_mask << 20) \| (usb_i_mask << 17) \| (usb_i_mask << 14);
c43c8339	176	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
6ad8d67d S	177	(~mask);
	178	io_settings \|= (ds_60_ohm << 29) \| (ds_60_ohm << 26) \|
	179	(ds_60_ohm << 23) \| (sc_fast << 20) \|
	180	(sc_fast << 17) \| (sc_fast << 14);
c43c8339	181	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
6ad8d67d	182
7c352cd3	183	if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
eb4e18e8 LV	184	io_settings_lpddr2();
	185	else
	186	io_settings_ddr3();
508a58fa	187	}
d4d986ee LV	188
	189	static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
	190	{0x45, 0x1}, /* 12 MHz */
	191	{-1, -1}, /* 13 MHz */
	192	{0x63, 0x2}, /* 16.8 MHz */
	193	{0x57, 0x2}, /* 19.2 MHz */
	194	{0x20, 0x1}, /* 26 MHz */
	195	{-1, -1}, /* 27 MHz */
	196	{0x41, 0x3} /* 38.4 MHz */
	197	};
	198
	199	void srcomp_enable(void)
	200	{
	201	u32 srcomp_value, mul_factor, div_factor, clk_val, i;
	202	u32 sysclk_ind = get_sys_clk_index();
	203	u32 omap_rev = omap_revision();
	204
e9d6cd04 LV	205	if (!is_omap54xx())
	206	return;
	207
d4d986ee LV	208	mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
	209	div_factor = srcomp_parameters[sysclk_ind].divide_factor;
	210
	211	for (i = 0; i < 4; i++) {
	212	srcomp_value = readl((ctrl)->control_srcomp_north_side + i4);
	213	srcomp_value &=
	214	~(MULTIPLY_FACTOR_XS_MASK \| DIVIDE_FACTOR_XS_MASK);
	215	srcomp_value \|= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) \|
	216	(div_factor << DIVIDE_FACTOR_XS_SHIFT);
	217	writel(srcomp_value, (ctrl)->control_srcomp_north_side + i4);
	218	}
	219
	220	if ((omap_rev == OMAP5430_ES1_0) \|\| (omap_rev == OMAP5432_ES1_0)) {
	221	clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
	222	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
	223	writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
	224
	225	for (i = 0; i < 4; i++) {
	226	srcomp_value =
	227	readl((ctrl)->control_srcomp_north_side + i4);
	228	srcomp_value &= ~PWRDWN_XS_MASK;
	229	writel(srcomp_value,
	230	(ctrl)->control_srcomp_north_side + i4);
	231
	232	while (((readl((ctrl)->control_srcomp_north_side + i4)
	233	& SRCODE_READ_XS_MASK) >>
	234	SRCODE_READ_XS_SHIFT) == 0)
	235	;
	236
	237	srcomp_value =
	238	readl((ctrl)->control_srcomp_north_side + i4);
	239	srcomp_value &= ~OVERRIDE_XS_MASK;
	240	writel(srcomp_value,
	241	(ctrl)->control_srcomp_north_side + i4);
	242	}
	243	} else {
	244	srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
	245	srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK \|
	246	DIVIDE_FACTOR_XS_MASK);
	247	srcomp_value \|= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) \|
	248	(div_factor << DIVIDE_FACTOR_XS_SHIFT);
	249	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	250
	251	for (i = 0; i < 4; i++) {
	252	srcomp_value =
	253	readl((ctrl)->control_srcomp_north_side + i4);
	254	srcomp_value \|= SRCODE_OVERRIDE_SEL_XS_MASK;
	255	writel(srcomp_value,
	256	(ctrl)->control_srcomp_north_side + i4);
	257
	258	srcomp_value =
	259	readl((ctrl)->control_srcomp_north_side + i4);
	260	srcomp_value &= ~OVERRIDE_XS_MASK;
	261	writel(srcomp_value,
	262	(ctrl)->control_srcomp_north_side + i4);
	263	}
	264
	265	srcomp_value =
	266	readl((*ctrl)->control_srcomp_east_side_wkup);
	267	srcomp_value \|= SRCODE_OVERRIDE_SEL_XS_MASK;
	268	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	269
	270	srcomp_value =
	271	readl((*ctrl)->control_srcomp_east_side_wkup);
272	srcomp_value &= ~OVERRIDE_XS_MASK;
273	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
274
275	clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
276	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
277	writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
278
279	clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
280	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
281	writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
282
283	for (i = 0; i < 4; i++) {
284	while (((readl((ctrl)->control_srcomp_north_side + i4)
285	& SRCODE_READ_XS_MASK) >>
286	SRCODE_READ_XS_SHIFT) == 0)
287	;
288
289	srcomp_value =
290	readl((ctrl)->control_srcomp_north_side + i4);
291	srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
292	writel(srcomp_value,
293	(ctrl)->control_srcomp_north_side + i4);
294	}
295
296	while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
297	SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
298	;
299
300	srcomp_value =
301	readl((*ctrl)->control_srcomp_east_side_wkup);
302	srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
303	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
304	}
305	}
508a58fa S	306	#endif
508a58fa S	307
784ab7c5 LV	308	void config_data_eye_leveling_samples(u32 emif_base)
784ab7c5 LV	309	{
6c70935d S	310	const struct ctrl_ioregs *ioregs;
	311
	312	get_ioregs(&ioregs);
	313
784ab7c5 LV	314	/EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4/
784ab7c5 LV	315	if (emif_base == EMIF1_BASE)
6c70935d S	316	writel(ioregs->ctrl_emif_sdram_config_ext_final,
6c70935d S	317	(*ctrl)->control_emif1_sdram_config_ext);
784ab7c5	318	else if (emif_base == EMIF2_BASE)
6c70935d S	319	writel(ioregs->ctrl_emif_sdram_config_ext_final,
6c70935d S	320	(*ctrl)->control_emif2_sdram_config_ext);
784ab7c5 LV	321	}
784ab7c5 LV	322
fc7368ec NM	323	void init_cpu_configuration(void)
	324	{
	325	u32 l2actlr;
	326
	327	asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
	328	/*
	329	* L2ACTLR: Ensure to enable the following:
	330	* 3: Disable clean/evict push to external
	331	* 4: Disable WriteUnique and WriteLineUnique transactions from master
	332	* 8: Disable DVM/CMO message broadcast
	333	*/
	334	l2actlr \|= 0x118;
	335	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
	336	}
	337
508a58fa S	338	void init_omap_revision(void)
	339	{
	340	/*
	341	* For some of the ES2/ES1 boards ID_CODE is not reliable:
	342	* Also, ES1 and ES2 have different ARM revisions
	343	* So use ARM revision for identification
	344	*/
	345	unsigned int rev = cortex_rev();
	346
eed7c0f7 S	347	switch (readl(CONTROL_ID_CODE)) {
	348	case OMAP5430_CONTROL_ID_CODE_ES1_0:
	349	*omap_si_rev = OMAP5430_ES1_0;
	350	if (rev == MIDR_CORTEX_A15_R2P2)
	351	*omap_si_rev = OMAP5430_ES2_0;
	352	break;
	353	case OMAP5432_CONTROL_ID_CODE_ES1_0:
	354	*omap_si_rev = OMAP5432_ES1_0;
	355	if (rev == MIDR_CORTEX_A15_R2P2)
	356	*omap_si_rev = OMAP5432_ES2_0;
	357	break;
	358	case OMAP5430_CONTROL_ID_CODE_ES2_0:
	359	*omap_si_rev = OMAP5430_ES2_0;
	360	break;
	361	case OMAP5432_CONTROL_ID_CODE_ES2_0:
	362	*omap_si_rev = OMAP5432_ES2_0;
cdd50a8d	363	break;
de62688b LV	364	case DRA752_CONTROL_ID_CODE_ES1_0:
	365	*omap_si_rev = DRA752_ES1_0;
	366	break;
3ac8c0bf NM	367	case DRA752_CONTROL_ID_CODE_ES1_1:
	368	*omap_si_rev = DRA752_ES1_1;
	369	break;
c1ea3bec NM	370	case DRA752_CONTROL_ID_CODE_ES2_0:
	371	*omap_si_rev = DRA752_ES2_0;
	372	break;
ee77a238 LV	373	case DRA722_CONTROL_ID_CODE_ES1_0:
	374	*omap_si_rev = DRA722_ES1_0;
	375	break;
508a58fa	376	default:
087189fb	377	*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
508a58fa	378	}
fc7368ec	379	init_cpu_configuration();
508a58fa	380	}
0696473b	381
9fd54016 PK	382	void omap_die_id(unsigned int *die_id)
	383	{
	384	die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
	385	die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
	386	die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
	387	die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
	388	}
	389
0696473b S	390	void reset_cpu(ulong ignored)
	391	{
	392	u32 omap_rev = omap_revision();
	393
	394	/*
	395	* WARM reset is not functional in case of OMAP5430 ES1.0 soc.
	396	* So use cold reset in case instead.
	397	*/
	398	if (omap_rev == OMAP5430_ES1_0)
d4e4129c	399	writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
0696473b	400	else
d4e4129c LV	401	writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
	402	}
	403
	404	u32 warm_reset(void)
	405	{
	406	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
0696473b	407	}
0b1b60c7 LV	408
	409	void setup_warmreset_time(void)
	410	{
	411	u32 rst_time, rst_val;
	412
	413	#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
	414	rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
	415	#else
	416	rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
	417	#endif
	418	rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
	419
	420	if (rst_time > RSTTIME1_MASK)
	421	rst_time = RSTTIME1_MASK;
	422
	423	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
	424	rst_val \|= rst_time;
	425	writel(rst_val, (*prcm)->prm_rsttime);
	426	}
5f603761 PR	427
	428	void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
	429	u32 cpu_rev_comb, u32 cpu_variant,
	430	u32 cpu_rev)
	431	{
	432	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
	433	}
1bbb556a NM	434
	435	void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
	436	u32 cpu_variant, u32 cpu_rev)
	437	{
095a5ef8 NM	438
	439	#ifdef CONFIG_ARM_ERRATA_801819
	440	/*
	441	* DRA72x processors are uniprocessors and DONOT have
	442	* ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
	443	* Extensions) Hence the erratum workaround is not applicable for
	444	* DRA72x processors.
	445	*/
	446	if (is_dra72x())
	447	acr &= ~((0x3 << 23) \| (0x3 << 25));
	448	#endif
1bbb556a NM	449	omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
1bbb556a NM	450	}