[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap5 / hwinit.c

/*
 *
 * Functions for omap5 based boards.
 *
 * (C) Copyright 2011
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *	Aneesh V	<aneesh@ti.com>
 *	Steve Sakoman	<steve@sakoman.com>
 *	Sricharan	<r.sricharan@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <linux/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include <asm/omap_common.h>

DECLARE_GLOBAL_DATA_PTR;

u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;

static struct gpio_bank gpio_bank_54xx[8] = {
	{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;

#ifdef CONFIG_SPL_BUILD
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
}

/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
	u32 io_settings = 0;
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);
	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);

	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);

	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);

	/* omap5432 does not use lpddr2 */
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);

	writel(ioregs->ctrl_emif_sdram_config_ext,
	       (*ctrl)->control_emif1_sdram_config_ext);
	writel(ioregs->ctrl_emif_sdram_config_ext,
	       (*ctrl)->control_emif2_sdram_config_ext);

	if (is_omap54xx()) {
		/* Disable DLL select */
		io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
							& 0xFFEFFFFF);
		writel(io_settings,
			(*ctrl)->control_port_emif1_sdram_config);

		io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
							& 0xFFEFFFFF);
		writel(io_settings,
			(*ctrl)->control_port_emif2_sdram_config);
	} else {
		writel(ioregs->ctrl_ddr_ctrl_ext_0,
				(*ctrl)->control_ddr_control_ext_0);
	}
}

/*
 * Some tuning of IOs for optimal power and performance
 */
void do_io_settings(void)
{
	u32 io_settings = 0, mask = 0;

	/* Impedance settings EMMC, C2C 1,2, hsi2 */
	mask = (ds_mask << 2) | (ds_mask << 8) |
		(ds_mask << 16) | (ds_mask << 18);
	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
				(~mask);
	io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
			(ds_45_ohm << 18) | (ds_60_ohm << 2);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_0);

	/* Impedance settings Mcspi2 */
	mask = (ds_mask << 30);
	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
			(~mask);
	io_settings |= (ds_60_ohm << 30);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_1);

	/* Impedance settings C2C 3,4 */
	mask = (ds_mask << 14) | (ds_mask << 16);
	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
			(~mask);
	io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_2);

	/* Slew rate settings EMMC, C2C 1,2 */
	mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
			(~mask);
	io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_0);

	/* Slew rate settings hsi2, Mcspi2 */
	mask = (sc_mask << 24) | (sc_mask << 28);
	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
			(~mask);
	io_settings |= (sc_fast << 28) | (sc_fast << 24);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_1);

	/* Slew rate settings C2C 3,4 */
	mask = (sc_mask << 16) | (sc_mask << 18);
	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
			(~mask);
	io_settings |= (sc_na << 16) | (sc_na << 18);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_2);

	/* impedance and slew rate settings for usb */
	mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
		(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
			(~mask);
	io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
		       (ds_60_ohm << 23) | (sc_fast << 20) |
		       (sc_fast << 17) | (sc_fast << 14);
	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);

	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
		io_settings_lpddr2();
	else
		io_settings_ddr3();
}

static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
	{0x45, 0x1},	/* 12 MHz   */
	{-1, -1},	/* 13 MHz   */
	{0x63, 0x2},	/* 16.8 MHz */
	{0x57, 0x2},	/* 19.2 MHz */
	{0x20, 0x1},	/* 26 MHz   */
	{-1, -1},	/* 27 MHz   */
	{0x41, 0x3}	/* 38.4 MHz */
};

void srcomp_enable(void)
{
	u32 srcomp_value, mul_factor, div_factor, clk_val, i;
	u32 sysclk_ind	= get_sys_clk_index();
	u32 omap_rev	= omap_revision();

	if (!is_omap54xx())
		return;

	mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
	div_factor = srcomp_parameters[sysclk_ind].divide_factor;

	for (i = 0; i < 4; i++) {
		srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
		srcomp_value &=
			~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
			(div_factor << DIVIDE_FACTOR_XS_SHIFT);
		writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
	}

	if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);

		for (i = 0; i < 4; i++) {
			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~PWRDWN_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);

			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
				& SRCODE_READ_XS_MASK) >>
				SRCODE_READ_XS_SHIFT) == 0)
				;

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~OVERRIDE_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}
	} else {
		srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
				  DIVIDE_FACTOR_XS_MASK);
		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
				(div_factor << DIVIDE_FACTOR_XS_SHIFT);
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		for (i = 0; i < 4; i++) {
			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~OVERRIDE_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~OVERRIDE_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);

		clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);

		for (i = 0; i < 4; i++) {
			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
				& SRCODE_READ_XS_MASK) >>
				SRCODE_READ_XS_SHIFT) == 0)
				;

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}

		while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
			SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
			;

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	}
}
#endif

void config_data_eye_leveling_samples(u32 emif_base)
{
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);

	/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
	if (emif_base == EMIF1_BASE)
		writel(ioregs->ctrl_emif_sdram_config_ext_final,
		       (*ctrl)->control_emif1_sdram_config_ext);
	else if (emif_base == EMIF2_BASE)
		writel(ioregs->ctrl_emif_sdram_config_ext_final,
		       (*ctrl)->control_emif2_sdram_config_ext);
}

void init_omap_revision(void)
{
	/*
	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
	 * Also, ES1 and ES2 have different ARM revisions
	 * So use ARM revision for identification
	 */
	unsigned int rev = cortex_rev();

	switch (readl(CONTROL_ID_CODE)) {
	case OMAP5430_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = OMAP5430_ES1_0;
		if (rev == MIDR_CORTEX_A15_R2P2)
			*omap_si_rev = OMAP5430_ES2_0;
		break;
	case OMAP5432_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = OMAP5432_ES1_0;
		if (rev == MIDR_CORTEX_A15_R2P2)
			*omap_si_rev = OMAP5432_ES2_0;
		break;
	case OMAP5430_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = OMAP5430_ES2_0;
		break;
	case OMAP5432_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = OMAP5432_ES2_0;
		break;
	case DRA752_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = DRA752_ES1_0;
		break;
	case DRA752_CONTROL_ID_CODE_ES1_1:
		*omap_si_rev = DRA752_ES1_1;
		break;
	case DRA722_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = DRA722_ES1_0;
		break;
	default:
		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
	}
}

void reset_cpu(ulong ignored)
{
	u32 omap_rev = omap_revision();

	/*
	 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
	 * So use cold reset in case instead.
	 */
	if (omap_rev == OMAP5430_ES1_0)
		writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
	else
		writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
}

u32 warm_reset(void)
{
	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}

void setup_warmreset_time(void)
{
	u32 rst_time, rst_val;

#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
	rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
#else
	rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
#endif
	rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;

	if (rst_time > RSTTIME1_MASK)
		rst_time = RSTTIME1_MASK;

	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
	rst_val |= rst_time;
	writel(rst_val, (*prcm)->prm_rsttime);
}
Commit	Line	Data
508a58fa S	1	/*
	2	*
	3	* Functions for omap5 based boards.
	4	*
	5	* (C) Copyright 2011
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Aneesh V <aneesh@ti.com>
	10	* Steve Sakoman <steve@sakoman.com>
	11	* Sricharan <r.sricharan@ti.com>
	12	*
1a459660	13	* SPDX-License-Identifier: GPL-2.0+
508a58fa S	14	*/
	15	#include <common.h>
	16	#include <asm/armv7.h>
	17	#include <asm/arch/cpu.h>
	18	#include <asm/arch/sys_proto.h>
af1d002f	19	#include <asm/arch/clock.h>
1ace4022	20	#include <linux/sizes.h>
508a58fa S	21	#include <asm/utils.h>
508a58fa S	22	#include <asm/arch/gpio.h>
784ab7c5	23	#include <asm/emif.h>
f92f2277	24	#include <asm/omap_common.h>
508a58fa S	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
f92f2277	28	u32 const omap_si_rev = (u32 )OMAP_SRAM_SCRATCH_OMAP_REV;
508a58fa	29
87bd05d7	30	static struct gpio_bank gpio_bank_54xx[8] = {
508a58fa S	31	{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
	32	{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
	33	{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
	34	{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
	35	{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
	36	{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
87bd05d7 AL	37	{ (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
87bd05d7 AL	38	{ (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
508a58fa S	39	};
	40
	41	const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
	42
	43	#ifdef CONFIG_SPL_BUILD
eb4e18e8 LV	44	/* LPDDR2 specific IO settings */
	45	static void io_settings_lpddr2(void)
	46	{
ef1697e9 LV	47	const struct ctrl_ioregs *ioregs;
	48
	49	get_ioregs(&ioregs);
	50	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	51	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
	52	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	53	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
	54	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
	55	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	56	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	57	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	58	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
eb4e18e8 LV	59	}
	60
	61	/* DDR3 specific IO settings */
	62	static void io_settings_ddr3(void)
	63	{
	64	u32 io_settings = 0;
ef1697e9	65	const struct ctrl_ioregs *ioregs;
eb4e18e8	66
ef1697e9 LV	67	get_ioregs(&ioregs);
	68	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
	69	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	70	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
eb4e18e8	71
ef1697e9 LV	72	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
	73	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	74	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
eb4e18e8	75
ef1697e9 LV	76	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	77	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	78	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
eb4e18e8 LV	79
eb4e18e8 LV	80	/* omap5432 does not use lpddr2 */
ef1697e9 LV	81	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
ef1697e9 LV	82	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
eb4e18e8	83
ef1697e9 LV	84	writel(ioregs->ctrl_emif_sdram_config_ext,
	85	(*ctrl)->control_emif1_sdram_config_ext);
	86	writel(ioregs->ctrl_emif_sdram_config_ext,
	87	(*ctrl)->control_emif2_sdram_config_ext);
eb4e18e8	88
92b0482c S	89	if (is_omap54xx()) {
	90	/* Disable DLL select */
	91	io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
eb4e18e8	92	& 0xFFEFFFFF);
92b0482c S	93	writel(io_settings,
92b0482c S	94	(*ctrl)->control_port_emif1_sdram_config);
eb4e18e8	95
92b0482c	96	io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
eb4e18e8	97	& 0xFFEFFFFF);
92b0482c S	98	writel(io_settings,
	99	(*ctrl)->control_port_emif2_sdram_config);
	100	} else {
	101	writel(ioregs->ctrl_ddr_ctrl_ext_0,
	102	(*ctrl)->control_ddr_control_ext_0);
	103	}
eb4e18e8 LV	104	}
eb4e18e8 LV	105
508a58fa S	106	/*
	107	* Some tuning of IOs for optimal power and performance
	108	*/
	109	void do_io_settings(void)
	110	{
6ad8d67d	111	u32 io_settings = 0, mask = 0;
6ad8d67d S	112
	113	/* Impedance settings EMMC, C2C 1,2, hsi2 */
	114	mask = (ds_mask << 2) \| (ds_mask << 8) \|
	115	(ds_mask << 16) \| (ds_mask << 18);
c43c8339	116	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
6ad8d67d S	117	(~mask);
	118	io_settings \|= (ds_60_ohm << 8) \| (ds_45_ohm << 16) \|
	119	(ds_45_ohm << 18) \| (ds_60_ohm << 2);
c43c8339	120	writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
6ad8d67d S	121
	122	/* Impedance settings Mcspi2 */
	123	mask = (ds_mask << 30);
c43c8339	124	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
6ad8d67d S	125	(~mask);
6ad8d67d S	126	io_settings \|= (ds_60_ohm << 30);
c43c8339	127	writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
6ad8d67d S	128
	129	/* Impedance settings C2C 3,4 */
	130	mask = (ds_mask << 14) \| (ds_mask << 16);
c43c8339	131	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
6ad8d67d S	132	(~mask);
6ad8d67d S	133	io_settings \|= (ds_45_ohm << 14) \| (ds_45_ohm << 16);
c43c8339	134	writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
6ad8d67d S	135
	136	/* Slew rate settings EMMC, C2C 1,2 */
	137	mask = (sc_mask << 8) \| (sc_mask << 16) \| (sc_mask << 18);
c43c8339	138	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
6ad8d67d S	139	(~mask);
6ad8d67d S	140	io_settings \|= (sc_fast << 8) \| (sc_na << 16) \| (sc_na << 18);
c43c8339	141	writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
6ad8d67d S	142
	143	/* Slew rate settings hsi2, Mcspi2 */
	144	mask = (sc_mask << 24) \| (sc_mask << 28);
c43c8339	145	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
6ad8d67d S	146	(~mask);
6ad8d67d S	147	io_settings \|= (sc_fast << 28) \| (sc_fast << 24);
c43c8339	148	writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
6ad8d67d S	149
	150	/* Slew rate settings C2C 3,4 */
	151	mask = (sc_mask << 16) \| (sc_mask << 18);
c43c8339	152	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
6ad8d67d S	153	(~mask);
6ad8d67d S	154	io_settings \|= (sc_na << 16) \| (sc_na << 18);
c43c8339	155	writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
6ad8d67d S	156
	157	/* impedance and slew rate settings for usb */
	158	mask = (usb_i_mask << 29) \| (usb_i_mask << 26) \| (usb_i_mask << 23) \|
	159	(usb_i_mask << 20) \| (usb_i_mask << 17) \| (usb_i_mask << 14);
c43c8339	160	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
6ad8d67d S	161	(~mask);
	162	io_settings \|= (ds_60_ohm << 29) \| (ds_60_ohm << 26) \|
	163	(ds_60_ohm << 23) \| (sc_fast << 20) \|
	164	(sc_fast << 17) \| (sc_fast << 14);
c43c8339	165	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
6ad8d67d	166
9ca8bfea	167	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
eb4e18e8 LV	168	io_settings_lpddr2();
	169	else
	170	io_settings_ddr3();
508a58fa	171	}
d4d986ee LV	172
	173	static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
	174	{0x45, 0x1}, /* 12 MHz */
	175	{-1, -1}, /* 13 MHz */
	176	{0x63, 0x2}, /* 16.8 MHz */
	177	{0x57, 0x2}, /* 19.2 MHz */
	178	{0x20, 0x1}, /* 26 MHz */
	179	{-1, -1}, /* 27 MHz */
	180	{0x41, 0x3} /* 38.4 MHz */
	181	};
	182
	183	void srcomp_enable(void)
	184	{
	185	u32 srcomp_value, mul_factor, div_factor, clk_val, i;
	186	u32 sysclk_ind = get_sys_clk_index();
	187	u32 omap_rev = omap_revision();
	188
e9d6cd04 LV	189	if (!is_omap54xx())
	190	return;
	191
d4d986ee LV	192	mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
	193	div_factor = srcomp_parameters[sysclk_ind].divide_factor;
	194
	195	for (i = 0; i < 4; i++) {
	196	srcomp_value = readl((ctrl)->control_srcomp_north_side + i4);
	197	srcomp_value &=
	198	~(MULTIPLY_FACTOR_XS_MASK \| DIVIDE_FACTOR_XS_MASK);
	199	srcomp_value \|= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) \|
	200	(div_factor << DIVIDE_FACTOR_XS_SHIFT);
	201	writel(srcomp_value, (ctrl)->control_srcomp_north_side + i4);
	202	}
	203
	204	if ((omap_rev == OMAP5430_ES1_0) \|\| (omap_rev == OMAP5432_ES1_0)) {
	205	clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
	206	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
	207	writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
	208
	209	for (i = 0; i < 4; i++) {
	210	srcomp_value =
	211	readl((ctrl)->control_srcomp_north_side + i4);
	212	srcomp_value &= ~PWRDWN_XS_MASK;
	213	writel(srcomp_value,
	214	(ctrl)->control_srcomp_north_side + i4);
	215
	216	while (((readl((ctrl)->control_srcomp_north_side + i4)
	217	& SRCODE_READ_XS_MASK) >>
	218	SRCODE_READ_XS_SHIFT) == 0)
	219	;
	220
	221	srcomp_value =
	222	readl((ctrl)->control_srcomp_north_side + i4);
	223	srcomp_value &= ~OVERRIDE_XS_MASK;
	224	writel(srcomp_value,
	225	(ctrl)->control_srcomp_north_side + i4);
	226	}
	227	} else {
	228	srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
	229	srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK \|
	230	DIVIDE_FACTOR_XS_MASK);
	231	srcomp_value \|= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) \|
	232	(div_factor << DIVIDE_FACTOR_XS_SHIFT);
	233	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	234
	235	for (i = 0; i < 4; i++) {
	236	srcomp_value =
	237	readl((ctrl)->control_srcomp_north_side + i4);
	238	srcomp_value \|= SRCODE_OVERRIDE_SEL_XS_MASK;
	239	writel(srcomp_value,
	240	(ctrl)->control_srcomp_north_side + i4);
	241
	242	srcomp_value =
	243	readl((ctrl)->control_srcomp_north_side + i4);
	244	srcomp_value &= ~OVERRIDE_XS_MASK;
	245	writel(srcomp_value,
	246	(ctrl)->control_srcomp_north_side + i4);
	247	}
	248
	249	srcomp_value =
	250	readl((*ctrl)->control_srcomp_east_side_wkup);
	251	srcomp_value \|= SRCODE_OVERRIDE_SEL_XS_MASK;
	252	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	253
	254	srcomp_value =
	255	readl((*ctrl)->control_srcomp_east_side_wkup);
256	srcomp_value &= ~OVERRIDE_XS_MASK;
257	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
258
259	clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
260	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
261	writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
262
263	clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
264	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
265	writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
266
267	for (i = 0; i < 4; i++) {
268	while (((readl((ctrl)->control_srcomp_north_side + i4)
269	& SRCODE_READ_XS_MASK) >>
270	SRCODE_READ_XS_SHIFT) == 0)
271	;
272
273	srcomp_value =
274	readl((ctrl)->control_srcomp_north_side + i4);
275	srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
276	writel(srcomp_value,
277	(ctrl)->control_srcomp_north_side + i4);
278	}
279
280	while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
281	SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
282	;
283
284	srcomp_value =
285	readl((*ctrl)->control_srcomp_east_side_wkup);
286	srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
287	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
288	}
289	}
508a58fa S	290	#endif
508a58fa S	291
784ab7c5 LV	292	void config_data_eye_leveling_samples(u32 emif_base)
784ab7c5 LV	293	{
6c70935d S	294	const struct ctrl_ioregs *ioregs;
	295
	296	get_ioregs(&ioregs);
	297
784ab7c5 LV	298	/EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4/
784ab7c5 LV	299	if (emif_base == EMIF1_BASE)
6c70935d S	300	writel(ioregs->ctrl_emif_sdram_config_ext_final,
6c70935d S	301	(*ctrl)->control_emif1_sdram_config_ext);
784ab7c5	302	else if (emif_base == EMIF2_BASE)
6c70935d S	303	writel(ioregs->ctrl_emif_sdram_config_ext_final,
6c70935d S	304	(*ctrl)->control_emif2_sdram_config_ext);
784ab7c5 LV	305	}
784ab7c5 LV	306
508a58fa S	307	void init_omap_revision(void)
	308	{
	309	/*
	310	* For some of the ES2/ES1 boards ID_CODE is not reliable:
	311	* Also, ES1 and ES2 have different ARM revisions
	312	* So use ARM revision for identification
	313	*/
	314	unsigned int rev = cortex_rev();
	315
eed7c0f7 S	316	switch (readl(CONTROL_ID_CODE)) {
	317	case OMAP5430_CONTROL_ID_CODE_ES1_0:
	318	*omap_si_rev = OMAP5430_ES1_0;
	319	if (rev == MIDR_CORTEX_A15_R2P2)
	320	*omap_si_rev = OMAP5430_ES2_0;
	321	break;
	322	case OMAP5432_CONTROL_ID_CODE_ES1_0:
	323	*omap_si_rev = OMAP5432_ES1_0;
	324	if (rev == MIDR_CORTEX_A15_R2P2)
	325	*omap_si_rev = OMAP5432_ES2_0;
	326	break;
	327	case OMAP5430_CONTROL_ID_CODE_ES2_0:
	328	*omap_si_rev = OMAP5430_ES2_0;
	329	break;
	330	case OMAP5432_CONTROL_ID_CODE_ES2_0:
	331	*omap_si_rev = OMAP5432_ES2_0;
cdd50a8d	332	break;
de62688b LV	333	case DRA752_CONTROL_ID_CODE_ES1_0:
	334	*omap_si_rev = DRA752_ES1_0;
	335	break;
3ac8c0bf NM	336	case DRA752_CONTROL_ID_CODE_ES1_1:
	337	*omap_si_rev = DRA752_ES1_1;
	338	break;
ee77a238 LV	339	case DRA722_CONTROL_ID_CODE_ES1_0:
	340	*omap_si_rev = DRA722_ES1_0;
	341	break;
508a58fa	342	default:
087189fb	343	*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
508a58fa S	344	}
508a58fa S	345	}
0696473b S	346
	347	void reset_cpu(ulong ignored)
	348	{
	349	u32 omap_rev = omap_revision();
	350
	351	/*
	352	* WARM reset is not functional in case of OMAP5430 ES1.0 soc.
	353	* So use cold reset in case instead.
	354	*/
	355	if (omap_rev == OMAP5430_ES1_0)
d4e4129c	356	writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
0696473b	357	else
d4e4129c LV	358	writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
	359	}
	360
	361	u32 warm_reset(void)
	362	{
	363	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
0696473b	364	}
0b1b60c7 LV	365
	366	void setup_warmreset_time(void)
	367	{
	368	u32 rst_time, rst_val;
	369
	370	#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
	371	rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
	372	#else
	373	rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
	374	#endif
	375	rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
	376
	377	if (rst_time > RSTTIME1_MASK)
	378	rst_time = RSTTIME1_MASK;
	379
	380	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
	381	rst_val \|= rst_time;
	382	writel(rst_val, (*prcm)->prm_rsttime);
	383	}