[people/ms/u-boot.git] / arch / arm / cpu / armv7 / zynq / slcr.c

/*
 * Copyright (c) 2013 Xilinx Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>

#define SLCR_LOCK_MAGIC		0x767B
#define SLCR_UNLOCK_MAGIC	0xDF0D

static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */

void zynq_slcr_lock(void)
{
	if (!slcr_lock)
		writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
}

void zynq_slcr_unlock(void)
{
	if (slcr_lock)
		writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
}

/* Reset the entire system */
void zynq_slcr_cpu_reset(void)
{
	/*
	 * Unlock the SLCR then reset the system.
	 * Note that this seems to require raw i/o
	 * functions or there's a lockup?
	 */
	zynq_slcr_unlock();

	/*
	 * Clear 0x0F000000 bits of reboot status register to workaround
	 * the FSBL not loading the bitstream after soft-reboot
	 * This is a temporary solution until we know more.
	 */
	clrbits_le32(&slcr_base->reboot_status, 0xF000000);

	writel(1, &slcr_base->pss_rst_ctrl);
}

/* Setup clk for network */
void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
{
	zynq_slcr_unlock();

	if (gem_id > 1) {
		printf("Non existing GEM id %d\n", gem_id);
		goto out;
	}

	if (gem_id) {
		/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
		writel(clk, &slcr_base->gem1_clk_ctrl);
		/* Configure GEM_RCLK_CTRL */
		writel(rclk, &slcr_base->gem1_rclk_ctrl);
	} else {
		/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
		writel(clk, &slcr_base->gem0_clk_ctrl);
		/* Configure GEM_RCLK_CTRL */
		writel(rclk, &slcr_base->gem0_rclk_ctrl);
	}

out:
	zynq_slcr_lock();
}
Commit	Line	Data
59c651f4 MS	1	/*
	2	* Copyright (c) 2013 Xilinx Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <asm/io.h>
	25	#include <malloc.h>
	26	#include <asm/arch/hardware.h>
	27
	28	#define SLCR_LOCK_MAGIC 0x767B
	29	#define SLCR_UNLOCK_MAGIC 0xDF0D
	30
	31	static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
	32
	33	void zynq_slcr_lock(void)
	34	{
	35	if (!slcr_lock)
	36	writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
	37	}
	38
	39	void zynq_slcr_unlock(void)
	40	{
	41	if (slcr_lock)
	42	writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
	43	}
	44
	45	/* Reset the entire system */
	46	void zynq_slcr_cpu_reset(void)
	47	{
	48	/*
	49	* Unlock the SLCR then reset the system.
	50	* Note that this seems to require raw i/o
	51	* functions or there's a lockup?
	52	*/
	53	zynq_slcr_unlock();
	54
	55	/*
	56	* Clear 0x0F000000 bits of reboot status register to workaround
	57	* the FSBL not loading the bitstream after soft-reboot
	58	* This is a temporary solution until we know more.
	59	*/
	60	clrbits_le32(&slcr_base->reboot_status, 0xF000000);
	61
	62	writel(1, &slcr_base->pss_rst_ctrl);
	63	}
80243528 MS	64
	65	/* Setup clk for network */
	66	void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
	67	{
	68	zynq_slcr_unlock();
	69
	70	if (gem_id > 1) {
	71	printf("Non existing GEM id %d\n", gem_id);
	72	goto out;
	73	}
	74
	75	if (gem_id) {
	76	/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
	77	writel(clk, &slcr_base->gem1_clk_ctrl);
	78	/* Configure GEM_RCLK_CTRL */
	79	writel(rclk, &slcr_base->gem1_rclk_ctrl);
	80	} else {
	81	/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
	82	writel(clk, &slcr_base->gem0_clk_ctrl);
	83	/* Configure GEM_RCLK_CTRL */
	84	writel(rclk, &slcr_base->gem0_rclk_ctrl);
	85	}
	86
	87	out:
	88	zynq_slcr_lock();
	89	}