[people/ms/u-boot.git] / arch / arm / cpu / armv7 / zynq / slcr.c

/*
 * Copyright (c) 2013 Xilinx Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>

#define SLCR_LOCK_MAGIC		0x767B
#define SLCR_UNLOCK_MAGIC	0xDF0D

#define SLCR_IDCODE_MASK	0x1F000
#define SLCR_IDCODE_SHIFT	12

static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */

void zynq_slcr_lock(void)
{
	if (!slcr_lock)
		writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
}

void zynq_slcr_unlock(void)
{
	if (slcr_lock)
		writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
}

/* Reset the entire system */
void zynq_slcr_cpu_reset(void)
{
	/*
	 * Unlock the SLCR then reset the system.
	 * Note that this seems to require raw i/o
	 * functions or there's a lockup?
	 */
	zynq_slcr_unlock();

	/*
	 * Clear 0x0F000000 bits of reboot status register to workaround
	 * the FSBL not loading the bitstream after soft-reboot
	 * This is a temporary solution until we know more.
	 */
	clrbits_le32(&slcr_base->reboot_status, 0xF000000);

	writel(1, &slcr_base->pss_rst_ctrl);
}

/* Setup clk for network */
void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
	int ret;

	zynq_slcr_unlock();

	if (gem_id > 1) {
		printf("Non existing GEM id %d\n", gem_id);
		goto out;
	}

	ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
	if (ret)
		goto out;

	if (gem_id) {
		/* Configure GEM_RCLK_CTRL */
		writel(1, &slcr_base->gem1_rclk_ctrl);
	} else {
		/* Configure GEM_RCLK_CTRL */
		writel(1, &slcr_base->gem0_rclk_ctrl);
	}
	udelay(100000);
out:
	zynq_slcr_lock();
}

void zynq_slcr_devcfg_disable(void)
{
	zynq_slcr_unlock();

	/* Disable AXI interface */
	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);

	/* Set Level Shifters DT618760 */
	writel(0xA, &slcr_base->lvl_shftr_en);

	zynq_slcr_lock();
}

void zynq_slcr_devcfg_enable(void)
{
	zynq_slcr_unlock();

	/* Set Level Shifters DT618760 */
	writel(0xF, &slcr_base->lvl_shftr_en);

	/* Disable AXI interface */
	writel(0x0, &slcr_base->fpga_rst_ctrl);

	zynq_slcr_lock();
}

u32 zynq_slcr_get_boot_mode(void)
{
	/* Get the bootmode register value */
	return readl(&slcr_base->boot_mode);
}

u32 zynq_slcr_get_idcode(void)
{
	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
							SLCR_IDCODE_SHIFT;
}
Commit	Line	Data
59c651f4 MS	1	/*
	2	* Copyright (c) 2013 Xilinx Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
59c651f4 MS	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <malloc.h>
	10	#include <asm/arch/hardware.h>
97598fcf	11	#include <asm/arch/clk.h>
59c651f4 MS	12
	13	#define SLCR_LOCK_MAGIC 0x767B
	14	#define SLCR_UNLOCK_MAGIC 0xDF0D
	15
d5dae85f MS	16	#define SLCR_IDCODE_MASK 0x1F000
	17	#define SLCR_IDCODE_SHIFT 12
	18
59c651f4 MS	19	static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
	20
	21	void zynq_slcr_lock(void)
	22	{
	23	if (!slcr_lock)
	24	writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
	25	}
	26
	27	void zynq_slcr_unlock(void)
	28	{
	29	if (slcr_lock)
	30	writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
	31	}
	32
	33	/* Reset the entire system */
	34	void zynq_slcr_cpu_reset(void)
	35	{
	36	/*
	37	* Unlock the SLCR then reset the system.
	38	* Note that this seems to require raw i/o
	39	* functions or there's a lockup?
	40	*/
	41	zynq_slcr_unlock();
	42
	43	/*
	44	* Clear 0x0F000000 bits of reboot status register to workaround
	45	* the FSBL not loading the bitstream after soft-reboot
	46	* This is a temporary solution until we know more.
	47	*/
	48	clrbits_le32(&slcr_base->reboot_status, 0xF000000);
	49
	50	writel(1, &slcr_base->pss_rst_ctrl);
	51	}
80243528 MS	52
80243528 MS	53	/* Setup clk for network */
97598fcf	54	void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
80243528	55	{
97598fcf SB	56	int ret;
97598fcf SB	57
80243528 MS	58	zynq_slcr_unlock();
	59
	60	if (gem_id > 1) {
	61	printf("Non existing GEM id %d\n", gem_id);
	62	goto out;
	63	}
	64
97598fcf SB	65	ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
	66	if (ret)
	67	goto out;
	68
80243528	69	if (gem_id) {
80243528	70	/* Configure GEM_RCLK_CTRL */
1cd46ed2	71	writel(1, &slcr_base->gem1_rclk_ctrl);
80243528	72	} else {
80243528	73	/* Configure GEM_RCLK_CTRL */
1cd46ed2	74	writel(1, &slcr_base->gem0_rclk_ctrl);
80243528	75	}
39523bef	76	udelay(100000);
80243528 MS	77	out:
	78	zynq_slcr_lock();
	79	}
d5dae85f MS	80
	81	void zynq_slcr_devcfg_disable(void)
	82	{
	83	zynq_slcr_unlock();
	84
	85	/* Disable AXI interface */
	86	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
	87
	88	/* Set Level Shifters DT618760 */
	89	writel(0xA, &slcr_base->lvl_shftr_en);
	90
	91	zynq_slcr_lock();
	92	}
	93
	94	void zynq_slcr_devcfg_enable(void)
	95	{
	96	zynq_slcr_unlock();
	97
	98	/* Set Level Shifters DT618760 */
	99	writel(0xF, &slcr_base->lvl_shftr_en);
	100
	101	/* Disable AXI interface */
	102	writel(0x0, &slcr_base->fpga_rst_ctrl);
	103
	104	zynq_slcr_lock();
	105	}
	106
b3de9249 JT	107	u32 zynq_slcr_get_boot_mode(void)
	108	{
	109	/* Get the bootmode register value */
	110	return readl(&slcr_base->boot_mode);
	111	}
	112
d5dae85f MS	113	u32 zynq_slcr_get_idcode(void)
	114	{
	115	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
	116	SLCR_IDCODE_SHIFT;
	117	}