[people/ms/u-boot.git] / arch / arm / cpu / armv7 / zynq / slcr.c

/*
 * Copyright (c) 2013 Xilinx Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>

#define SLCR_LOCK_MAGIC		0x767B
#define SLCR_UNLOCK_MAGIC	0xDF0D

#define SLCR_IDCODE_MASK	0x1F000
#define SLCR_IDCODE_SHIFT	12

static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */

void zynq_slcr_lock(void)
{
	if (!slcr_lock)
		writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
}

void zynq_slcr_unlock(void)
{
	if (slcr_lock)
		writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
}

/* Reset the entire system */
void zynq_slcr_cpu_reset(void)
{
	/*
	 * Unlock the SLCR then reset the system.
	 * Note that this seems to require raw i/o
	 * functions or there's a lockup?
	 */
	zynq_slcr_unlock();

	/*
	 * Clear 0x0F000000 bits of reboot status register to workaround
	 * the FSBL not loading the bitstream after soft-reboot
	 * This is a temporary solution until we know more.
	 */
	clrbits_le32(&slcr_base->reboot_status, 0xF000000);

	writel(1, &slcr_base->pss_rst_ctrl);
}

/* Setup clk for network */
void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
{
	zynq_slcr_unlock();

	if (gem_id > 1) {
		printf("Non existing GEM id %d\n", gem_id);
		goto out;
	}

	if (gem_id) {
		/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
		writel(clk, &slcr_base->gem1_clk_ctrl);
		/* Configure GEM_RCLK_CTRL */
		writel(rclk, &slcr_base->gem1_rclk_ctrl);
	} else {
		/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
		writel(clk, &slcr_base->gem0_clk_ctrl);
		/* Configure GEM_RCLK_CTRL */
		writel(rclk, &slcr_base->gem0_rclk_ctrl);
	}

out:
	zynq_slcr_lock();
}

void zynq_slcr_devcfg_disable(void)
{
	zynq_slcr_unlock();

	/* Disable AXI interface */
	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);

	/* Set Level Shifters DT618760 */
	writel(0xA, &slcr_base->lvl_shftr_en);

	zynq_slcr_lock();
}

void zynq_slcr_devcfg_enable(void)
{
	zynq_slcr_unlock();

	/* Set Level Shifters DT618760 */
	writel(0xF, &slcr_base->lvl_shftr_en);

	/* Disable AXI interface */
	writel(0x0, &slcr_base->fpga_rst_ctrl);

	zynq_slcr_lock();
}

u32 zynq_slcr_get_idcode(void)
{
	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
							SLCR_IDCODE_SHIFT;
}
Commit	Line	Data
59c651f4 MS	1	/*
	2	* Copyright (c) 2013 Xilinx Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <asm/io.h>
	25	#include <malloc.h>
	26	#include <asm/arch/hardware.h>
	27
	28	#define SLCR_LOCK_MAGIC 0x767B
	29	#define SLCR_UNLOCK_MAGIC 0xDF0D
	30
d5dae85f MS	31	#define SLCR_IDCODE_MASK 0x1F000
	32	#define SLCR_IDCODE_SHIFT 12
	33
59c651f4 MS	34	static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
	35
	36	void zynq_slcr_lock(void)
	37	{
	38	if (!slcr_lock)
	39	writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
	40	}
	41
	42	void zynq_slcr_unlock(void)
	43	{
	44	if (slcr_lock)
	45	writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
	46	}
	47
	48	/* Reset the entire system */
	49	void zynq_slcr_cpu_reset(void)
	50	{
	51	/*
	52	* Unlock the SLCR then reset the system.
	53	* Note that this seems to require raw i/o
	54	* functions or there's a lockup?
	55	*/
	56	zynq_slcr_unlock();
	57
	58	/*
	59	* Clear 0x0F000000 bits of reboot status register to workaround
	60	* the FSBL not loading the bitstream after soft-reboot
	61	* This is a temporary solution until we know more.
	62	*/
	63	clrbits_le32(&slcr_base->reboot_status, 0xF000000);
	64
	65	writel(1, &slcr_base->pss_rst_ctrl);
	66	}
80243528 MS	67
	68	/* Setup clk for network */
	69	void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
	70	{
	71	zynq_slcr_unlock();
	72
	73	if (gem_id > 1) {
	74	printf("Non existing GEM id %d\n", gem_id);
	75	goto out;
	76	}
	77
	78	if (gem_id) {
	79	/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
	80	writel(clk, &slcr_base->gem1_clk_ctrl);
	81	/* Configure GEM_RCLK_CTRL */
	82	writel(rclk, &slcr_base->gem1_rclk_ctrl);
	83	} else {
	84	/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
	85	writel(clk, &slcr_base->gem0_clk_ctrl);
	86	/* Configure GEM_RCLK_CTRL */
	87	writel(rclk, &slcr_base->gem0_rclk_ctrl);
	88	}
	89
	90	out:
	91	zynq_slcr_lock();
	92	}
d5dae85f MS	93
	94	void zynq_slcr_devcfg_disable(void)
	95	{
	96	zynq_slcr_unlock();
	97
	98	/* Disable AXI interface */
	99	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
	100
	101	/* Set Level Shifters DT618760 */
	102	writel(0xA, &slcr_base->lvl_shftr_en);
	103
	104	zynq_slcr_lock();
	105	}
	106
	107	void zynq_slcr_devcfg_enable(void)
	108	{
	109	zynq_slcr_unlock();
	110
	111	/* Set Level Shifters DT618760 */
	112	writel(0xF, &slcr_base->lvl_shftr_en);
	113
	114	/* Disable AXI interface */
	115	writel(0x0, &slcr_base->fpga_rst_ctrl);
	116
	117	zynq_slcr_lock();
	118	}
	119
	120	u32 zynq_slcr_get_idcode(void)
	121	{
	122	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
	123	SLCR_IDCODE_SHIFT;
	124	}