]>
Commit | Line | Data |
---|---|---|
9533acf3 | 1 | config ARCH_LS1012A |
4a444176 | 2 | bool |
ee2a5102 | 3 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 4 | select FSL_LSCH2 |
24aaa094 | 5 | select SYS_FSL_DDR_BE |
9533acf3 | 6 | select SYS_FSL_MMDC |
0a37cf8f | 7 | select SYS_FSL_ERRATUM_A010315 |
a421192f | 8 | select ARCH_EARLY_INIT_R |
a5d67547 | 9 | select BOARD_EARLY_INIT_F |
0a37cf8f YS |
10 | |
11 | config ARCH_LS1043A | |
4a444176 | 12 | bool |
ee2a5102 | 13 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 14 | select FSL_LSCH2 |
d26e34c4 | 15 | select SYS_FSL_DDR |
24aaa094 YS |
16 | select SYS_FSL_DDR_BE |
17 | select SYS_FSL_DDR_VER_50 | |
ba1b6fb5 YS |
18 | select SYS_FSL_ERRATUM_A008850 |
19 | select SYS_FSL_ERRATUM_A009660 | |
20 | select SYS_FSL_ERRATUM_A009663 | |
21 | select SYS_FSL_ERRATUM_A009929 | |
22 | select SYS_FSL_ERRATUM_A009942 | |
0a37cf8f | 23 | select SYS_FSL_ERRATUM_A010315 |
0ea3671d | 24 | select SYS_FSL_ERRATUM_A010539 |
d26e34c4 YS |
25 | select SYS_FSL_HAS_DDR3 |
26 | select SYS_FSL_HAS_DDR4 | |
a421192f | 27 | select ARCH_EARLY_INIT_R |
a5d67547 | 28 | select BOARD_EARLY_INIT_F |
fedb428c | 29 | imply SCSI |
6500ec7a | 30 | imply CMD_PCI |
9533acf3 | 31 | |
da28e58a | 32 | config ARCH_LS1046A |
4a444176 | 33 | bool |
ee2a5102 | 34 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 35 | select FSL_LSCH2 |
d26e34c4 | 36 | select SYS_FSL_DDR |
24aaa094 | 37 | select SYS_FSL_DDR_BE |
24aaa094 | 38 | select SYS_FSL_DDR_VER_50 |
0ae7050c | 39 | select SYS_FSL_ERRATUM_A008336 |
ba1b6fb5 | 40 | select SYS_FSL_ERRATUM_A008511 |
fb806ad6 | 41 | select SYS_FSL_ERRATUM_A008850 |
ba1b6fb5 YS |
42 | select SYS_FSL_ERRATUM_A009801 |
43 | select SYS_FSL_ERRATUM_A009803 | |
44 | select SYS_FSL_ERRATUM_A009942 | |
45 | select SYS_FSL_ERRATUM_A010165 | |
0ea3671d | 46 | select SYS_FSL_ERRATUM_A010539 |
d26e34c4 | 47 | select SYS_FSL_HAS_DDR4 |
f534b8f5 | 48 | select SYS_FSL_SRDS_2 |
a421192f | 49 | select ARCH_EARLY_INIT_R |
a5d67547 | 50 | select BOARD_EARLY_INIT_F |
fedb428c | 51 | imply SCSI |
9533acf3 | 52 | |
6d9b82d0 AK |
53 | config ARCH_LS1088A |
54 | bool | |
55 | select ARMV8_SET_SMPEN | |
56 | select FSL_LSCH3 | |
57 | select SYS_FSL_DDR | |
58 | select SYS_FSL_DDR_LE | |
59 | select SYS_FSL_DDR_VER_50 | |
17d066fc AK |
60 | select SYS_FSL_EC1 |
61 | select SYS_FSL_EC2 | |
6d9b82d0 AK |
62 | select SYS_FSL_ERRATUM_A009803 |
63 | select SYS_FSL_ERRATUM_A009942 | |
64 | select SYS_FSL_ERRATUM_A010165 | |
65 | select SYS_FSL_ERRATUM_A008511 | |
66 | select SYS_FSL_ERRATUM_A008850 | |
67 | select SYS_FSL_HAS_CCI400 | |
68 | select SYS_FSL_HAS_DDR4 | |
17d066fc | 69 | select SYS_FSL_HAS_RGMII |
6d9b82d0 AK |
70 | select SYS_FSL_HAS_SEC |
71 | select SYS_FSL_SEC_COMPAT_5 | |
72 | select SYS_FSL_SEC_LE | |
73 | select SYS_FSL_SRDS_1 | |
74 | select SYS_FSL_SRDS_2 | |
75 | select FSL_TZASC_1 | |
76 | select ARCH_EARLY_INIT_R | |
77 | select BOARD_EARLY_INIT_F | |
78 | ||
4a444176 YS |
79 | config ARCH_LS2080A |
80 | bool | |
ee2a5102 | 81 | select ARMV8_SET_SMPEN |
8dda2e2f TR |
82 | select ARM_ERRATA_826974 |
83 | select ARM_ERRATA_828024 | |
84 | select ARM_ERRATA_829520 | |
85 | select ARM_ERRATA_833471 | |
fb2bf8c2 | 86 | select FSL_LSCH3 |
d26e34c4 | 87 | select SYS_FSL_DDR |
24aaa094 YS |
88 | select SYS_FSL_DDR_LE |
89 | select SYS_FSL_DDR_VER_50 | |
c055cee1 | 90 | select SYS_FSL_HAS_CCN504 |
f534b8f5 | 91 | select SYS_FSL_HAS_DP_DDR |
2c2e2c9e | 92 | select SYS_FSL_HAS_SEC |
d26e34c4 | 93 | select SYS_FSL_HAS_DDR4 |
2c2e2c9e | 94 | select SYS_FSL_SEC_COMPAT_5 |
90b80386 | 95 | select SYS_FSL_SEC_LE |
f534b8f5 | 96 | select SYS_FSL_SRDS_2 |
85a9a14e A |
97 | select FSL_TZASC_1 |
98 | select FSL_TZASC_2 | |
ba1b6fb5 YS |
99 | select SYS_FSL_ERRATUM_A008336 |
100 | select SYS_FSL_ERRATUM_A008511 | |
101 | select SYS_FSL_ERRATUM_A008514 | |
102 | select SYS_FSL_ERRATUM_A008585 | |
103 | select SYS_FSL_ERRATUM_A009635 | |
104 | select SYS_FSL_ERRATUM_A009663 | |
105 | select SYS_FSL_ERRATUM_A009801 | |
106 | select SYS_FSL_ERRATUM_A009803 | |
107 | select SYS_FSL_ERRATUM_A009942 | |
108 | select SYS_FSL_ERRATUM_A010165 | |
dd48f0bf | 109 | select SYS_FSL_ERRATUM_A009203 |
a421192f | 110 | select ARCH_EARLY_INIT_R |
a5d67547 | 111 | select BOARD_EARLY_INIT_F |
fb2bf8c2 YS |
112 | |
113 | config FSL_LSCH2 | |
114 | bool | |
63b2316c | 115 | select SYS_FSL_HAS_CCI400 |
2c2e2c9e YS |
116 | select SYS_FSL_HAS_SEC |
117 | select SYS_FSL_SEC_COMPAT_5 | |
90b80386 | 118 | select SYS_FSL_SEC_BE |
f534b8f5 YS |
119 | select SYS_FSL_SRDS_1 |
120 | select SYS_HAS_SERDES | |
fb2bf8c2 YS |
121 | |
122 | config FSL_LSCH3 | |
123 | bool | |
f534b8f5 YS |
124 | select SYS_FSL_SRDS_1 |
125 | select SYS_HAS_SERDES | |
fb2bf8c2 | 126 | |
e243b6e1 YS |
127 | config FSL_MC_ENET |
128 | bool "Management Complex network" | |
6d9b82d0 | 129 | depends on ARCH_LS2080A || ARCH_LS1088A |
e243b6e1 YS |
130 | default y |
131 | select RESV_RAM | |
132 | help | |
133 | Enable Management Complex (MC) network | |
134 | ||
fb2bf8c2 YS |
135 | menu "Layerscape architecture" |
136 | depends on FSL_LSCH2 || FSL_LSCH3 | |
4a444176 | 137 | |
19538f30 HZ |
138 | config FSL_PCIE_COMPAT |
139 | string "PCIe compatible of Kernel DT" | |
140 | depends on PCIE_LAYERSCAPE | |
141 | default "fsl,ls1012a-pcie" if ARCH_LS1012A | |
142 | default "fsl,ls1043a-pcie" if ARCH_LS1043A | |
143 | default "fsl,ls1046a-pcie" if ARCH_LS1046A | |
144 | default "fsl,ls2080a-pcie" if ARCH_LS2080A | |
6d9b82d0 | 145 | default "fsl,ls1088a-pcie" if ARCH_LS1088A |
19538f30 HZ |
146 | help |
147 | This compatible is used to find pci controller node in Kernel DT | |
148 | to complete fixup. | |
149 | ||
fa18ed76 WS |
150 | config HAS_FEATURE_GIC64K_ALIGN |
151 | bool | |
152 | default y if ARCH_LS1043A | |
153 | ||
2ca84bf7 WS |
154 | config HAS_FEATURE_ENHANCED_MSI |
155 | bool | |
156 | default y if ARCH_LS1043A | |
fa18ed76 | 157 | |
2d16a1a6 | 158 | menu "Layerscape PPA" |
159 | config FSL_LS_PPA | |
160 | bool "FSL Layerscape PPA firmware support" | |
df88cb3b | 161 | depends on !ARMV8_PSCI |
0541527b | 162 | select ARMV8_SEC_FIRMWARE_SUPPORT |
daa92644 | 163 | select SEC_FIRMWARE_ARMV8_PSCI |
0541527b | 164 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 |
2d16a1a6 | 165 | help |
166 | The FSL Primary Protected Application (PPA) is a software component | |
167 | which is loaded during boot stage, and then remains resident in RAM | |
168 | and runs in the TrustZone after boot. | |
169 | Say y to enable it. | |
8e59778b YS |
170 | |
171 | config SPL_FSL_LS_PPA | |
172 | bool "FSL Layerscape PPA firmware support for SPL build" | |
173 | depends on !ARMV8_PSCI | |
174 | select SPL_ARMV8_SEC_FIRMWARE_SUPPORT | |
175 | select SEC_FIRMWARE_ARMV8_PSCI | |
176 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 | |
177 | help | |
178 | The FSL Primary Protected Application (PPA) is a software component | |
179 | which is loaded during boot stage, and then remains resident in RAM | |
180 | and runs in the TrustZone after boot. This is to load PPA during SPL | |
181 | stage instead of the RAM version of U-Boot. Once PPA is initialized, | |
182 | the rest of U-Boot (including RAM version) runs at EL2. | |
0541527b HZ |
183 | choice |
184 | prompt "FSL Layerscape PPA firmware loading-media select" | |
185 | depends on FSL_LS_PPA | |
77bbe55d HZ |
186 | default SYS_LS_PPA_FW_IN_MMC if SD_BOOT |
187 | default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT | |
0541527b HZ |
188 | default SYS_LS_PPA_FW_IN_XIP |
189 | ||
190 | config SYS_LS_PPA_FW_IN_XIP | |
191 | bool "XIP" | |
192 | help | |
193 | Say Y here if the PPA firmware locate at XIP flash, such | |
194 | as NOR or QSPI flash. | |
195 | ||
77bbe55d HZ |
196 | config SYS_LS_PPA_FW_IN_MMC |
197 | bool "eMMC or SD Card" | |
198 | help | |
199 | Say Y here if the PPA firmware locate at eMMC/SD card. | |
200 | ||
201 | config SYS_LS_PPA_FW_IN_NAND | |
202 | bool "NAND" | |
203 | help | |
204 | Say Y here if the PPA firmware locate at NAND flash. | |
205 | ||
0541527b HZ |
206 | endchoice |
207 | ||
208 | config SYS_LS_PPA_FW_ADDR | |
209 | hex "Address of PPA firmware loading from" | |
210 | depends on FSL_LS_PPA | |
89a168f7 | 211 | default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A |
a9a5cef3 | 212 | default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT |
f5bf23d8 | 213 | default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A |
e84a324b | 214 | default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A |
a9a5cef3 AW |
215 | default 0x60400000 if SYS_LS_PPA_FW_IN_XIP |
216 | default 0x400000 if SYS_LS_PPA_FW_IN_MMC | |
217 | default 0x400000 if SYS_LS_PPA_FW_IN_NAND | |
77bbe55d | 218 | |
0541527b HZ |
219 | help |
220 | If the PPA firmware locate at XIP flash, such as NOR or | |
221 | QSPI flash, this address is a directly memory-mapped. | |
222 | If it is in a serial accessed flash, such as NAND and SD | |
223 | card, it is a byte offset. | |
d1a795ac VPB |
224 | |
225 | config SYS_LS_PPA_ESBC_ADDR | |
226 | hex "hdr address of PPA firmware loading from" | |
227 | depends on FSL_LS_PPA && CHAIN_OF_TRUST | |
06fb06f6 SG |
228 | default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A |
229 | default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A | |
230 | default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A | |
15e7c681 UA |
231 | default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A |
232 | default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A | |
06fb06f6 SG |
233 | default 0x680000 if SYS_LS_PPA_FW_IN_MMC |
234 | default 0x680000 if SYS_LS_PPA_FW_IN_NAND | |
d1a795ac VPB |
235 | help |
236 | If the PPA header firmware locate at XIP flash, such as NOR or | |
237 | QSPI flash, this address is a directly memory-mapped. | |
238 | If it is in a serial accessed flash, such as NAND and SD | |
239 | card, it is a byte offset. | |
240 | ||
9fa3a542 SG |
241 | config LS_PPA_ESBC_HDR_SIZE |
242 | hex "Length of PPA ESBC header" | |
243 | depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP | |
244 | default 0x2000 | |
245 | help | |
246 | Length (in bytes) of PPA ESBC header to be copied from MMC/SD or | |
247 | NAND to memory to validate PPA image. | |
248 | ||
2d16a1a6 | 249 | endmenu |
250 | ||
0a37cf8f YS |
251 | config SYS_FSL_ERRATUM_A010315 |
252 | bool "Workaround for PCIe erratum A010315" | |
0ea3671d HZ |
253 | |
254 | config SYS_FSL_ERRATUM_A010539 | |
255 | bool "Workaround for PIN MUX erratum A010539" | |
fb2bf8c2 | 256 | |
b4b60d06 YS |
257 | config MAX_CPUS |
258 | int "Maximum number of CPUs permitted for Layerscape" | |
259 | default 4 if ARCH_LS1043A | |
260 | default 4 if ARCH_LS1046A | |
261 | default 16 if ARCH_LS2080A | |
6d9b82d0 | 262 | default 8 if ARCH_LS1088A |
b4b60d06 YS |
263 | default 1 |
264 | help | |
265 | Set this number to the maximum number of possible CPUs in the SoC. | |
266 | SoCs may have multiple clusters with each cluster may have multiple | |
267 | ports. If some ports are reserved but higher ports are used for | |
268 | cores, count the reserved ports. This will allocate enough memory | |
269 | in spin table to properly handle all cores. | |
270 | ||
01f65d97 | 271 | config SECURE_BOOT |
9cfab06e | 272 | bool "Secure Boot" |
01f65d97 YS |
273 | help |
274 | Enable Freescale Secure Boot feature | |
275 | ||
dd2ad2f1 YY |
276 | config QSPI_AHB_INIT |
277 | bool "Init the QSPI AHB bus" | |
278 | help | |
279 | The default setting for QSPI AHB bus just support 3bytes addressing. | |
280 | But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB | |
281 | bus for those flashes to support the full QSPI flash size. | |
282 | ||
63b2316c AK |
283 | config SYS_CCI400_OFFSET |
284 | hex "Offset for CCI400 base" | |
285 | depends on SYS_FSL_HAS_CCI400 | |
286 | default 0x3090000 if ARCH_LS1088A | |
287 | default 0x180000 if FSL_LSCH2 | |
288 | help | |
289 | Offset for CCI400 base | |
290 | CCI400 base addr = CCSRBAR + CCI400_OFFSET | |
291 | ||
25af7dc1 YS |
292 | config SYS_FSL_IFC_BANK_COUNT |
293 | int "Maximum banks of Integrated flash controller" | |
6d9b82d0 | 294 | depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A |
25af7dc1 YS |
295 | default 4 if ARCH_LS1043A |
296 | default 4 if ARCH_LS1046A | |
6d9b82d0 | 297 | default 8 if ARCH_LS2080A || ARCH_LS1088A |
25af7dc1 | 298 | |
63b2316c AK |
299 | config SYS_FSL_HAS_CCI400 |
300 | bool | |
301 | ||
c055cee1 AK |
302 | config SYS_FSL_HAS_CCN504 |
303 | bool | |
304 | ||
fd638102 YS |
305 | config SYS_FSL_HAS_DP_DDR |
306 | bool | |
307 | ||
f534b8f5 YS |
308 | config SYS_FSL_SRDS_1 |
309 | bool | |
310 | ||
311 | config SYS_FSL_SRDS_2 | |
312 | bool | |
313 | ||
314 | config SYS_HAS_SERDES | |
315 | bool | |
316 | ||
85a9a14e A |
317 | config FSL_TZASC_1 |
318 | bool | |
319 | ||
320 | config FSL_TZASC_2 | |
321 | bool | |
322 | ||
fb2bf8c2 | 323 | endmenu |
ba1b6fb5 | 324 | |
904110c7 HZ |
325 | menu "Layerscape clock tree configuration" |
326 | depends on FSL_LSCH2 || FSL_LSCH3 | |
327 | ||
328 | config SYS_FSL_CLK | |
329 | bool "Enable clock tree initialization" | |
330 | default y | |
331 | ||
332 | config CLUSTER_CLK_FREQ | |
333 | int "Reference clock of core cluster" | |
334 | depends on ARCH_LS1012A | |
335 | default 100000000 | |
336 | help | |
337 | This number is the reference clock frequency of core PLL. | |
338 | For most platforms, the core PLL and Platform PLL have the same | |
339 | reference clock, but for some platforms, LS1012A for instance, | |
340 | they are provided sepatately. | |
341 | ||
342 | config SYS_FSL_PCLK_DIV | |
343 | int "Platform clock divider" | |
344 | default 1 if ARCH_LS1043A | |
345 | default 1 if ARCH_LS1046A | |
6d9b82d0 | 346 | default 1 if ARCH_LS1088A |
904110c7 HZ |
347 | default 2 |
348 | help | |
349 | This is the divider that is used to derive Platform clock from | |
350 | Platform PLL, in another word: | |
351 | Platform_clk = Platform_PLL_freq / this_divider | |
352 | ||
353 | config SYS_FSL_DSPI_CLK_DIV | |
354 | int "DSPI clock divider" | |
355 | default 1 if ARCH_LS1043A | |
356 | default 2 | |
357 | help | |
358 | This is the divider that is used to derive DSPI clock from Platform | |
bf7aecce | 359 | clock, in another word DSPI_clk = Platform_clk / this_divider. |
904110c7 HZ |
360 | |
361 | config SYS_FSL_DUART_CLK_DIV | |
362 | int "DUART clock divider" | |
363 | default 1 if ARCH_LS1043A | |
364 | default 2 | |
365 | help | |
366 | This is the divider that is used to derive DUART clock from Platform | |
367 | clock, in another word DUART_clk = Platform_clk / this_divider. | |
368 | ||
369 | config SYS_FSL_I2C_CLK_DIV | |
370 | int "I2C clock divider" | |
371 | default 1 if ARCH_LS1043A | |
372 | default 2 | |
373 | help | |
374 | This is the divider that is used to derive I2C clock from Platform | |
375 | clock, in another word I2C_clk = Platform_clk / this_divider. | |
376 | ||
377 | config SYS_FSL_IFC_CLK_DIV | |
378 | int "IFC clock divider" | |
379 | default 1 if ARCH_LS1043A | |
380 | default 2 | |
381 | help | |
382 | This is the divider that is used to derive IFC clock from Platform | |
383 | clock, in another word IFC_clk = Platform_clk / this_divider. | |
384 | ||
385 | config SYS_FSL_LPUART_CLK_DIV | |
386 | int "LPUART clock divider" | |
387 | default 1 if ARCH_LS1043A | |
388 | default 2 | |
389 | help | |
390 | This is the divider that is used to derive LPUART clock from Platform | |
391 | clock, in another word LPUART_clk = Platform_clk / this_divider. | |
392 | ||
393 | config SYS_FSL_SDHC_CLK_DIV | |
394 | int "SDHC clock divider" | |
395 | default 1 if ARCH_LS1043A | |
396 | default 1 if ARCH_LS1012A | |
397 | default 2 | |
398 | help | |
399 | This is the divider that is used to derive SDHC clock from Platform | |
400 | clock, in another word SDHC_clk = Platform_clk / this_divider. | |
401 | endmenu | |
402 | ||
f2ccf7f7 YS |
403 | config RESV_RAM |
404 | bool | |
405 | help | |
406 | Reserve memory from the top, tracked by gd->arch.resv_ram. This | |
407 | reserved RAM can be used by special driver that resides in memory | |
408 | after U-Boot exits. It's up to implementation to allocate and allow | |
409 | access to this reserved memory. For example, the reserved RAM can | |
410 | be at the high end of physical memory. The reserve RAM may be | |
411 | excluded from memory bank(s) passed to OS, or marked as reserved. | |
412 | ||
17d066fc AK |
413 | config SYS_FSL_EC1 |
414 | bool | |
415 | help | |
416 | Ethernet controller 1, this is connected to MAC3. | |
417 | Provides DPAA2 capabilities | |
418 | ||
419 | config SYS_FSL_EC2 | |
420 | bool | |
421 | help | |
422 | Ethernet controller 2, this is connected to MAC4. | |
423 | Provides DPAA2 capabilities | |
424 | ||
ba1b6fb5 YS |
425 | config SYS_FSL_ERRATUM_A008336 |
426 | bool | |
427 | ||
428 | config SYS_FSL_ERRATUM_A008514 | |
429 | bool | |
430 | ||
431 | config SYS_FSL_ERRATUM_A008585 | |
432 | bool | |
433 | ||
434 | config SYS_FSL_ERRATUM_A008850 | |
435 | bool | |
436 | ||
dd48f0bf A |
437 | config SYS_FSL_ERRATUM_A009203 |
438 | bool | |
439 | ||
ba1b6fb5 YS |
440 | config SYS_FSL_ERRATUM_A009635 |
441 | bool | |
442 | ||
443 | config SYS_FSL_ERRATUM_A009660 | |
444 | bool | |
445 | ||
446 | config SYS_FSL_ERRATUM_A009929 | |
447 | bool | |
f692d4ee | 448 | |
17d066fc AK |
449 | |
450 | config SYS_FSL_HAS_RGMII | |
451 | bool | |
452 | depends on SYS_FSL_EC1 || SYS_FSL_EC2 | |
453 | ||
454 | ||
f692d4ee YS |
455 | config SYS_MC_RSV_MEM_ALIGN |
456 | hex "Management Complex reserved memory alignment" | |
457 | depends on RESV_RAM | |
6d9b82d0 AK |
458 | default 0x20000000 if ARCH_LS2080A |
459 | default 0x70000000 if ARCH_LS1088A | |
f692d4ee YS |
460 | help |
461 | Reserved memory needs to be aligned for MC to use. Default value | |
462 | is 512MB. | |
b529993e PT |
463 | |
464 | config SPL_LDSCRIPT | |
465 | default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A |