[people/ms/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

config ARCH_LS1012A
	bool
	select ARMV8_SET_SMPEN
	select FSL_LSCH2
	select SYS_FSL_DDR_BE
	select SYS_FSL_MMDC
	select SYS_FSL_ERRATUM_A010315
	select ARCH_EARLY_INIT_R
	select BOARD_EARLY_INIT_F

config ARCH_LS1043A
	bool
	select ARMV8_SET_SMPEN
	select FSL_LSCH2
	select SYS_FSL_DDR
	select SYS_FSL_DDR_BE
	select SYS_FSL_DDR_VER_50
	select SYS_FSL_ERRATUM_A008850
	select SYS_FSL_ERRATUM_A009660
	select SYS_FSL_ERRATUM_A009663
	select SYS_FSL_ERRATUM_A009929
	select SYS_FSL_ERRATUM_A009942
	select SYS_FSL_ERRATUM_A010315
	select SYS_FSL_ERRATUM_A010539
	select SYS_FSL_HAS_DDR3
	select SYS_FSL_HAS_DDR4
	select ARCH_EARLY_INIT_R
	select BOARD_EARLY_INIT_F
	imply SCSI
	imply CMD_PCI

config ARCH_LS1046A
	bool
	select ARMV8_SET_SMPEN
	select FSL_LSCH2
	select SYS_FSL_DDR
	select SYS_FSL_DDR_BE
	select SYS_FSL_DDR_VER_50
	select SYS_FSL_ERRATUM_A008336
	select SYS_FSL_ERRATUM_A008511
	select SYS_FSL_ERRATUM_A008850
	select SYS_FSL_ERRATUM_A009801
	select SYS_FSL_ERRATUM_A009803
	select SYS_FSL_ERRATUM_A009942
	select SYS_FSL_ERRATUM_A010165
	select SYS_FSL_ERRATUM_A010539
	select SYS_FSL_HAS_DDR4
	select SYS_FSL_SRDS_2
	select ARCH_EARLY_INIT_R
	select BOARD_EARLY_INIT_F
	imply SCSI

config ARCH_LS2080A
	bool
	select ARMV8_SET_SMPEN
	select ARM_ERRATA_826974
	select ARM_ERRATA_828024
	select ARM_ERRATA_829520
	select ARM_ERRATA_833471
	select FSL_LSCH3
	select SYS_FSL_DDR
	select SYS_FSL_DDR_LE
	select SYS_FSL_DDR_VER_50
	select SYS_FSL_HAS_DP_DDR
	select SYS_FSL_HAS_SEC
	select SYS_FSL_HAS_DDR4
	select SYS_FSL_SEC_COMPAT_5
	select SYS_FSL_SEC_LE
	select SYS_FSL_SRDS_2
	select FSL_TZASC_1
	select FSL_TZASC_2
	select SYS_FSL_ERRATUM_A008336
	select SYS_FSL_ERRATUM_A008511
	select SYS_FSL_ERRATUM_A008514
	select SYS_FSL_ERRATUM_A008585
	select SYS_FSL_ERRATUM_A009635
	select SYS_FSL_ERRATUM_A009663
	select SYS_FSL_ERRATUM_A009801
	select SYS_FSL_ERRATUM_A009803
	select SYS_FSL_ERRATUM_A009942
	select SYS_FSL_ERRATUM_A010165
	select SYS_FSL_ERRATUM_A009203
	select ARCH_EARLY_INIT_R
	select BOARD_EARLY_INIT_F

config FSL_LSCH2
	bool
	select SYS_FSL_HAS_SEC
	select SYS_FSL_SEC_COMPAT_5
	select SYS_FSL_SEC_BE
	select SYS_FSL_SRDS_1
	select SYS_HAS_SERDES

config FSL_LSCH3
	bool
	select SYS_FSL_SRDS_1
	select SYS_HAS_SERDES

config FSL_MC_ENET
	bool "Management Complex network"
	depends on ARCH_LS2080A
	default y
	select RESV_RAM
	help
	  Enable Management Complex (MC) network

menu "Layerscape architecture"
	depends on FSL_LSCH2 || FSL_LSCH3

config FSL_PCIE_COMPAT
	string "PCIe compatible of Kernel DT"
	depends on PCIE_LAYERSCAPE
	default "fsl,ls1012a-pcie" if ARCH_LS1012A
	default "fsl,ls1043a-pcie" if ARCH_LS1043A
	default "fsl,ls1046a-pcie" if ARCH_LS1046A
	default "fsl,ls2080a-pcie" if ARCH_LS2080A
	help
	  This compatible is used to find pci controller node in Kernel DT
	  to complete fixup.

config HAS_FEATURE_GIC64K_ALIGN
	bool
	default y if ARCH_LS1043A

config HAS_FEATURE_ENHANCED_MSI
	bool
	default y if ARCH_LS1043A

menu "Layerscape PPA"
config FSL_LS_PPA
	bool "FSL Layerscape PPA firmware support"
	depends on !ARMV8_PSCI
	select ARMV8_SEC_FIRMWARE_SUPPORT
	select SEC_FIRMWARE_ARMV8_PSCI
	select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
	help
	  The FSL Primary Protected Application (PPA) is a software component
	  which is loaded during boot stage, and then remains resident in RAM
	  and runs in the TrustZone after boot.
	  Say y to enable it.

config SPL_FSL_LS_PPA
	bool "FSL Layerscape PPA firmware support for SPL build"
	depends on !ARMV8_PSCI
	select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
	select SEC_FIRMWARE_ARMV8_PSCI
	select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
	help
	  The FSL Primary Protected Application (PPA) is a software component
	  which is loaded during boot stage, and then remains resident in RAM
	  and runs in the TrustZone after boot. This is to load PPA during SPL
	  stage instead of the RAM version of U-Boot. Once PPA is initialized,
	  the rest of U-Boot (including RAM version) runs at EL2.
choice
	prompt "FSL Layerscape PPA firmware loading-media select"
	depends on FSL_LS_PPA
	default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
	default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
	default SYS_LS_PPA_FW_IN_XIP

config SYS_LS_PPA_FW_IN_XIP
	bool "XIP"
	help
	  Say Y here if the PPA firmware locate at XIP flash, such
	  as NOR or QSPI flash.

config SYS_LS_PPA_FW_IN_MMC
	bool "eMMC or SD Card"
	help
	  Say Y here if the PPA firmware locate at eMMC/SD card.

config SYS_LS_PPA_FW_IN_NAND
	bool "NAND"
	help
	  Say Y here if the PPA firmware locate at NAND flash.

endchoice

config SYS_LS_PPA_FW_ADDR
	hex "Address of PPA firmware loading from"
	depends on FSL_LS_PPA
	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
	default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
	default 0x400000 if SYS_LS_PPA_FW_IN_MMC
	default 0x400000 if SYS_LS_PPA_FW_IN_NAND

	help
	  If the PPA firmware locate at XIP flash, such as NOR or
	  QSPI flash, this address is a directly memory-mapped.
	  If it is in a serial accessed flash, such as NAND and SD
	  card, it is a byte offset.

config SYS_LS_PPA_ESBC_ADDR
	hex "hdr address of PPA firmware loading from"
	depends on FSL_LS_PPA && CHAIN_OF_TRUST
	default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
	default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
	default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
	default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
	default 0x700000 if SYS_LS_PPA_FW_IN_MMC
	default 0x700000 if SYS_LS_PPA_FW_IN_NAND
	help
	  If the PPA header firmware locate at XIP flash, such as NOR or
	  QSPI flash, this address is a directly memory-mapped.
	  If it is in a serial accessed flash, such as NAND and SD
	  card, it is a byte offset.

config LS_PPA_ESBC_HDR_SIZE
	hex "Length of PPA ESBC header"
	depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
	default 0x2000
	help
	  Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
	  NAND to memory to validate PPA image.

endmenu

config SYS_FSL_ERRATUM_A010315
	bool "Workaround for PCIe erratum A010315"

config SYS_FSL_ERRATUM_A010539
	bool "Workaround for PIN MUX erratum A010539"

config MAX_CPUS
	int "Maximum number of CPUs permitted for Layerscape"
	default 4 if ARCH_LS1043A
	default 4 if ARCH_LS1046A
	default 16 if ARCH_LS2080A
	default 1
	help
	  Set this number to the maximum number of possible CPUs in the SoC.
	  SoCs may have multiple clusters with each cluster may have multiple
	  ports. If some ports are reserved but higher ports are used for
	  cores, count the reserved ports. This will allocate enough memory
	  in spin table to properly handle all cores.

config SECURE_BOOT
	bool "Secure Boot"
	help
		Enable Freescale Secure Boot feature

config QSPI_AHB_INIT
	bool "Init the QSPI AHB bus"
	help
	  The default setting for QSPI AHB bus just support 3bytes addressing.
	  But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
	  bus for those flashes to support the full QSPI flash size.

config SYS_FSL_IFC_BANK_COUNT
	int "Maximum banks of Integrated flash controller"
	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
	default 4 if ARCH_LS1043A
	default 4 if ARCH_LS1046A
	default 8 if ARCH_LS2080A

config SYS_FSL_HAS_DP_DDR
	bool

config SYS_FSL_SRDS_1
	bool

config SYS_FSL_SRDS_2
	bool

config SYS_HAS_SERDES
	bool

config FSL_TZASC_1
	bool

config FSL_TZASC_2
	bool

endmenu

menu "Layerscape clock tree configuration"
	depends on FSL_LSCH2 || FSL_LSCH3

config SYS_FSL_CLK
	bool "Enable clock tree initialization"
	default y

config CLUSTER_CLK_FREQ
	int "Reference clock of core cluster"
	depends on ARCH_LS1012A
	default 100000000
	help
	  This number is the reference clock frequency of core PLL.
	  For most platforms, the core PLL and Platform PLL have the same
	  reference clock, but for some platforms, LS1012A for instance,
	  they are provided sepatately.

config SYS_FSL_PCLK_DIV
	int "Platform clock divider"
	default 1 if ARCH_LS1043A
	default 1 if ARCH_LS1046A
	default 2
	help
	  This is the divider that is used to derive Platform clock from
	  Platform PLL, in another word:
		Platform_clk = Platform_PLL_freq / this_divider

config SYS_FSL_DSPI_CLK_DIV
	int "DSPI clock divider"
	default 1 if ARCH_LS1043A
	default 2
	help
	  This is the divider that is used to derive DSPI clock from Platform
	  clock, in another word DSPI_clk = Platform_clk / this_divider.

config SYS_FSL_DUART_CLK_DIV
	int "DUART clock divider"
	default 1 if ARCH_LS1043A
	default 2
	help
	  This is the divider that is used to derive DUART clock from Platform
	  clock, in another word DUART_clk = Platform_clk / this_divider.

config SYS_FSL_I2C_CLK_DIV
	int "I2C clock divider"
	default 1 if ARCH_LS1043A
	default 2
	help
	  This is the divider that is used to derive I2C clock from Platform
	  clock, in another word I2C_clk = Platform_clk / this_divider.

config SYS_FSL_IFC_CLK_DIV
	int "IFC clock divider"
	default 1 if ARCH_LS1043A
	default 2
	help
	  This is the divider that is used to derive IFC clock from Platform
	  clock, in another word IFC_clk = Platform_clk / this_divider.

config SYS_FSL_LPUART_CLK_DIV
	int "LPUART clock divider"
	default 1 if ARCH_LS1043A
	default 2
	help
	  This is the divider that is used to derive LPUART clock from Platform
	  clock, in another word LPUART_clk = Platform_clk / this_divider.

config SYS_FSL_SDHC_CLK_DIV
	int "SDHC clock divider"
	default 1 if ARCH_LS1043A
	default 1 if ARCH_LS1012A
	default 2
	help
	  This is the divider that is used to derive SDHC clock from Platform
	  clock, in another word SDHC_clk = Platform_clk / this_divider.
endmenu

config RESV_RAM
	bool
	help
	  Reserve memory from the top, tracked by gd->arch.resv_ram. This
	  reserved RAM can be used by special driver that resides in memory
	  after U-Boot exits. It's up to implementation to allocate and allow
	  access to this reserved memory. For example, the reserved RAM can
	  be at the high end of physical memory. The reserve RAM may be
	  excluded from memory bank(s) passed to OS, or marked as reserved.

config SYS_FSL_ERRATUM_A008336
	bool

config SYS_FSL_ERRATUM_A008514
	bool

config SYS_FSL_ERRATUM_A008585
	bool

config SYS_FSL_ERRATUM_A008850
	bool

config SYS_FSL_ERRATUM_A009203
	bool

config SYS_FSL_ERRATUM_A009635
	bool

config SYS_FSL_ERRATUM_A009660
	bool

config SYS_FSL_ERRATUM_A009929
	bool

config SYS_MC_RSV_MEM_ALIGN
	hex "Management Complex reserved memory alignment"
	depends on RESV_RAM
	default 0x20000000
	help
	  Reserved memory needs to be aligned for MC to use. Default value
	  is 512MB.
Commit	Line	Data
9533acf3	1	config ARCH_LS1012A
4a444176	2	bool
ee2a5102	3	select ARMV8_SET_SMPEN
fb2bf8c2	4	select FSL_LSCH2
24aaa094	5	select SYS_FSL_DDR_BE
9533acf3	6	select SYS_FSL_MMDC
0a37cf8f	7	select SYS_FSL_ERRATUM_A010315
a421192f	8	select ARCH_EARLY_INIT_R
a5d67547	9	select BOARD_EARLY_INIT_F
0a37cf8f YS	10
0a37cf8f YS	11	config ARCH_LS1043A
4a444176	12	bool
ee2a5102	13	select ARMV8_SET_SMPEN
fb2bf8c2	14	select FSL_LSCH2
d26e34c4	15	select SYS_FSL_DDR
24aaa094 YS	16	select SYS_FSL_DDR_BE
24aaa094 YS	17	select SYS_FSL_DDR_VER_50
ba1b6fb5 YS	18	select SYS_FSL_ERRATUM_A008850
	19	select SYS_FSL_ERRATUM_A009660
	20	select SYS_FSL_ERRATUM_A009663
	21	select SYS_FSL_ERRATUM_A009929
	22	select SYS_FSL_ERRATUM_A009942
0a37cf8f	23	select SYS_FSL_ERRATUM_A010315
0ea3671d	24	select SYS_FSL_ERRATUM_A010539
d26e34c4 YS	25	select SYS_FSL_HAS_DDR3
d26e34c4 YS	26	select SYS_FSL_HAS_DDR4
a421192f	27	select ARCH_EARLY_INIT_R
a5d67547	28	select BOARD_EARLY_INIT_F
fedb428c	29	imply SCSI
6500ec7a	30	imply CMD_PCI
9533acf3	31
da28e58a	32	config ARCH_LS1046A
4a444176	33	bool
ee2a5102	34	select ARMV8_SET_SMPEN
fb2bf8c2	35	select FSL_LSCH2
d26e34c4	36	select SYS_FSL_DDR
24aaa094	37	select SYS_FSL_DDR_BE
24aaa094	38	select SYS_FSL_DDR_VER_50
0ae7050c	39	select SYS_FSL_ERRATUM_A008336
ba1b6fb5	40	select SYS_FSL_ERRATUM_A008511
fb806ad6	41	select SYS_FSL_ERRATUM_A008850
ba1b6fb5 YS	42	select SYS_FSL_ERRATUM_A009801
	43	select SYS_FSL_ERRATUM_A009803
	44	select SYS_FSL_ERRATUM_A009942
	45	select SYS_FSL_ERRATUM_A010165
0ea3671d	46	select SYS_FSL_ERRATUM_A010539
d26e34c4	47	select SYS_FSL_HAS_DDR4
f534b8f5	48	select SYS_FSL_SRDS_2
a421192f	49	select ARCH_EARLY_INIT_R
a5d67547	50	select BOARD_EARLY_INIT_F
fedb428c	51	imply SCSI
9533acf3	52
4a444176 YS	53	config ARCH_LS2080A
4a444176 YS	54	bool
ee2a5102	55	select ARMV8_SET_SMPEN
8dda2e2f TR	56	select ARM_ERRATA_826974
	57	select ARM_ERRATA_828024
	58	select ARM_ERRATA_829520
	59	select ARM_ERRATA_833471
fb2bf8c2	60	select FSL_LSCH3
d26e34c4	61	select SYS_FSL_DDR
24aaa094 YS	62	select SYS_FSL_DDR_LE
24aaa094 YS	63	select SYS_FSL_DDR_VER_50
f534b8f5	64	select SYS_FSL_HAS_DP_DDR
2c2e2c9e	65	select SYS_FSL_HAS_SEC
d26e34c4	66	select SYS_FSL_HAS_DDR4
2c2e2c9e	67	select SYS_FSL_SEC_COMPAT_5
90b80386	68	select SYS_FSL_SEC_LE
f534b8f5	69	select SYS_FSL_SRDS_2
85a9a14e A	70	select FSL_TZASC_1
85a9a14e A	71	select FSL_TZASC_2
ba1b6fb5 YS	72	select SYS_FSL_ERRATUM_A008336
	73	select SYS_FSL_ERRATUM_A008511
	74	select SYS_FSL_ERRATUM_A008514
	75	select SYS_FSL_ERRATUM_A008585
	76	select SYS_FSL_ERRATUM_A009635
	77	select SYS_FSL_ERRATUM_A009663
	78	select SYS_FSL_ERRATUM_A009801
	79	select SYS_FSL_ERRATUM_A009803
	80	select SYS_FSL_ERRATUM_A009942
	81	select SYS_FSL_ERRATUM_A010165
dd48f0bf	82	select SYS_FSL_ERRATUM_A009203
a421192f	83	select ARCH_EARLY_INIT_R
a5d67547	84	select BOARD_EARLY_INIT_F
fb2bf8c2 YS	85
	86	config FSL_LSCH2
	87	bool
2c2e2c9e YS	88	select SYS_FSL_HAS_SEC
2c2e2c9e YS	89	select SYS_FSL_SEC_COMPAT_5
90b80386	90	select SYS_FSL_SEC_BE
f534b8f5 YS	91	select SYS_FSL_SRDS_1
f534b8f5 YS	92	select SYS_HAS_SERDES
fb2bf8c2 YS	93
	94	config FSL_LSCH3
	95	bool
f534b8f5 YS	96	select SYS_FSL_SRDS_1
f534b8f5 YS	97	select SYS_HAS_SERDES
fb2bf8c2	98
e243b6e1 YS	99	config FSL_MC_ENET
	100	bool "Management Complex network"
	101	depends on ARCH_LS2080A
	102	default y
	103	select RESV_RAM
	104	help
	105	Enable Management Complex (MC) network
	106
fb2bf8c2 YS	107	menu "Layerscape architecture"
fb2bf8c2 YS	108	depends on FSL_LSCH2 \|\| FSL_LSCH3
4a444176	109
19538f30 HZ	110	config FSL_PCIE_COMPAT
	111	string "PCIe compatible of Kernel DT"
	112	depends on PCIE_LAYERSCAPE
	113	default "fsl,ls1012a-pcie" if ARCH_LS1012A
	114	default "fsl,ls1043a-pcie" if ARCH_LS1043A
	115	default "fsl,ls1046a-pcie" if ARCH_LS1046A
	116	default "fsl,ls2080a-pcie" if ARCH_LS2080A
	117	help
	118	This compatible is used to find pci controller node in Kernel DT
	119	to complete fixup.
	120
fa18ed76 WS	121	config HAS_FEATURE_GIC64K_ALIGN
	122	bool
	123	default y if ARCH_LS1043A
	124
2ca84bf7 WS	125	config HAS_FEATURE_ENHANCED_MSI
	126	bool
	127	default y if ARCH_LS1043A
fa18ed76	128
2d16a1a6	129	menu "Layerscape PPA"
	130	config FSL_LS_PPA
	131	bool "FSL Layerscape PPA firmware support"
df88cb3b	132	depends on !ARMV8_PSCI
0541527b	133	select ARMV8_SEC_FIRMWARE_SUPPORT
daa92644	134	select SEC_FIRMWARE_ARMV8_PSCI
0541527b	135	select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
2d16a1a6	136	help
	137	The FSL Primary Protected Application (PPA) is a software component
	138	which is loaded during boot stage, and then remains resident in RAM
	139	and runs in the TrustZone after boot.
	140	Say y to enable it.
8e59778b YS	141
	142	config SPL_FSL_LS_PPA
	143	bool "FSL Layerscape PPA firmware support for SPL build"
	144	depends on !ARMV8_PSCI
	145	select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
	146	select SEC_FIRMWARE_ARMV8_PSCI
	147	select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
	148	help
	149	The FSL Primary Protected Application (PPA) is a software component
	150	which is loaded during boot stage, and then remains resident in RAM
	151	and runs in the TrustZone after boot. This is to load PPA during SPL
	152	stage instead of the RAM version of U-Boot. Once PPA is initialized,
	153	the rest of U-Boot (including RAM version) runs at EL2.
0541527b HZ	154	choice
	155	prompt "FSL Layerscape PPA firmware loading-media select"
	156	depends on FSL_LS_PPA
77bbe55d HZ	157	default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
77bbe55d HZ	158	default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
0541527b HZ	159	default SYS_LS_PPA_FW_IN_XIP
	160
	161	config SYS_LS_PPA_FW_IN_XIP
	162	bool "XIP"
	163	help
	164	Say Y here if the PPA firmware locate at XIP flash, such
	165	as NOR or QSPI flash.
	166
77bbe55d HZ	167	config SYS_LS_PPA_FW_IN_MMC
	168	bool "eMMC or SD Card"
	169	help
	170	Say Y here if the PPA firmware locate at eMMC/SD card.
	171
	172	config SYS_LS_PPA_FW_IN_NAND
	173	bool "NAND"
	174	help
	175	Say Y here if the PPA firmware locate at NAND flash.
	176
0541527b HZ	177	endchoice
	178
	179	config SYS_LS_PPA_FW_ADDR
	180	hex "Address of PPA firmware loading from"
	181	depends on FSL_LS_PPA
89a168f7	182	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
a9a5cef3	183	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
f5bf23d8	184	default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
a9a5cef3 AW	185	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
	186	default 0x400000 if SYS_LS_PPA_FW_IN_MMC
	187	default 0x400000 if SYS_LS_PPA_FW_IN_NAND
77bbe55d	188
0541527b HZ	189	help
	190	If the PPA firmware locate at XIP flash, such as NOR or
	191	QSPI flash, this address is a directly memory-mapped.
	192	If it is in a serial accessed flash, such as NAND and SD
	193	card, it is a byte offset.
d1a795ac VPB	194
	195	config SYS_LS_PPA_ESBC_ADDR
	196	hex "hdr address of PPA firmware loading from"
	197	depends on FSL_LS_PPA && CHAIN_OF_TRUST
	198	default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
b3635f57	199	default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
d2a99502	200	default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
d1a795ac	201	default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
9fa3a542 SG	202	default 0x700000 if SYS_LS_PPA_FW_IN_MMC
9fa3a542 SG	203	default 0x700000 if SYS_LS_PPA_FW_IN_NAND
d1a795ac VPB	204	help
	205	If the PPA header firmware locate at XIP flash, such as NOR or
	206	QSPI flash, this address is a directly memory-mapped.
	207	If it is in a serial accessed flash, such as NAND and SD
	208	card, it is a byte offset.
	209
9fa3a542 SG	210	config LS_PPA_ESBC_HDR_SIZE
	211	hex "Length of PPA ESBC header"
	212	depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
	213	default 0x2000
	214	help
	215	Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
	216	NAND to memory to validate PPA image.
	217
2d16a1a6	218	endmenu
2d16a1a6	219
0a37cf8f YS	220	config SYS_FSL_ERRATUM_A010315
0a37cf8f YS	221	bool "Workaround for PCIe erratum A010315"
0ea3671d HZ	222
	223	config SYS_FSL_ERRATUM_A010539
	224	bool "Workaround for PIN MUX erratum A010539"
fb2bf8c2	225
b4b60d06 YS	226	config MAX_CPUS
	227	int "Maximum number of CPUs permitted for Layerscape"
	228	default 4 if ARCH_LS1043A
	229	default 4 if ARCH_LS1046A
	230	default 16 if ARCH_LS2080A
	231	default 1
	232	help
	233	Set this number to the maximum number of possible CPUs in the SoC.
	234	SoCs may have multiple clusters with each cluster may have multiple
	235	ports. If some ports are reserved but higher ports are used for
	236	cores, count the reserved ports. This will allocate enough memory
	237	in spin table to properly handle all cores.
	238
01f65d97	239	config SECURE_BOOT
9cfab06e	240	bool "Secure Boot"
01f65d97 YS	241	help
	242	Enable Freescale Secure Boot feature
	243
dd2ad2f1 YY	244	config QSPI_AHB_INIT
	245	bool "Init the QSPI AHB bus"
	246	help
	247	The default setting for QSPI AHB bus just support 3bytes addressing.
	248	But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
	249	bus for those flashes to support the full QSPI flash size.
	250
25af7dc1 YS	251	config SYS_FSL_IFC_BANK_COUNT
	252	int "Maximum banks of Integrated flash controller"
	253	depends on ARCH_LS1043A \|\| ARCH_LS1046A \|\| ARCH_LS2080A
	254	default 4 if ARCH_LS1043A
	255	default 4 if ARCH_LS1046A
	256	default 8 if ARCH_LS2080A
	257
fd638102 YS	258	config SYS_FSL_HAS_DP_DDR
	259	bool
	260
f534b8f5 YS	261	config SYS_FSL_SRDS_1
	262	bool
	263
	264	config SYS_FSL_SRDS_2
	265	bool
	266
	267	config SYS_HAS_SERDES
	268	bool
	269
85a9a14e A	270	config FSL_TZASC_1
	271	bool
	272
	273	config FSL_TZASC_2
	274	bool
	275
fb2bf8c2	276	endmenu
ba1b6fb5	277
904110c7 HZ	278	menu "Layerscape clock tree configuration"
	279	depends on FSL_LSCH2 \|\| FSL_LSCH3
	280
	281	config SYS_FSL_CLK
	282	bool "Enable clock tree initialization"
	283	default y
	284
	285	config CLUSTER_CLK_FREQ
	286	int "Reference clock of core cluster"
	287	depends on ARCH_LS1012A
	288	default 100000000
	289	help
	290	This number is the reference clock frequency of core PLL.
	291	For most platforms, the core PLL and Platform PLL have the same
	292	reference clock, but for some platforms, LS1012A for instance,
	293	they are provided sepatately.
	294
	295	config SYS_FSL_PCLK_DIV
	296	int "Platform clock divider"
	297	default 1 if ARCH_LS1043A
	298	default 1 if ARCH_LS1046A
	299	default 2
	300	help
	301	This is the divider that is used to derive Platform clock from
	302	Platform PLL, in another word:
	303	Platform_clk = Platform_PLL_freq / this_divider
	304
	305	config SYS_FSL_DSPI_CLK_DIV
	306	int "DSPI clock divider"
	307	default 1 if ARCH_LS1043A
	308	default 2
	309	help
	310	This is the divider that is used to derive DSPI clock from Platform
bf7aecce	311	clock, in another word DSPI_clk = Platform_clk / this_divider.
904110c7 HZ	312
	313	config SYS_FSL_DUART_CLK_DIV
	314	int "DUART clock divider"
	315	default 1 if ARCH_LS1043A
	316	default 2
	317	help
	318	This is the divider that is used to derive DUART clock from Platform
	319	clock, in another word DUART_clk = Platform_clk / this_divider.
	320
	321	config SYS_FSL_I2C_CLK_DIV
	322	int "I2C clock divider"
	323	default 1 if ARCH_LS1043A
	324	default 2
	325	help
	326	This is the divider that is used to derive I2C clock from Platform
	327	clock, in another word I2C_clk = Platform_clk / this_divider.
	328
	329	config SYS_FSL_IFC_CLK_DIV
	330	int "IFC clock divider"
	331	default 1 if ARCH_LS1043A
	332	default 2
	333	help
	334	This is the divider that is used to derive IFC clock from Platform
	335	clock, in another word IFC_clk = Platform_clk / this_divider.
	336
	337	config SYS_FSL_LPUART_CLK_DIV
	338	int "LPUART clock divider"
	339	default 1 if ARCH_LS1043A
	340	default 2
	341	help
	342	This is the divider that is used to derive LPUART clock from Platform
	343	clock, in another word LPUART_clk = Platform_clk / this_divider.
	344
	345	config SYS_FSL_SDHC_CLK_DIV
	346	int "SDHC clock divider"
	347	default 1 if ARCH_LS1043A
	348	default 1 if ARCH_LS1012A
	349	default 2
	350	help
	351	This is the divider that is used to derive SDHC clock from Platform
	352	clock, in another word SDHC_clk = Platform_clk / this_divider.
	353	endmenu
	354
f2ccf7f7 YS	355	config RESV_RAM
	356	bool
	357	help
	358	Reserve memory from the top, tracked by gd->arch.resv_ram. This
	359	reserved RAM can be used by special driver that resides in memory
	360	after U-Boot exits. It's up to implementation to allocate and allow
	361	access to this reserved memory. For example, the reserved RAM can
	362	be at the high end of physical memory. The reserve RAM may be
	363	excluded from memory bank(s) passed to OS, or marked as reserved.
	364
ba1b6fb5 YS	365	config SYS_FSL_ERRATUM_A008336
	366	bool
	367
	368	config SYS_FSL_ERRATUM_A008514
	369	bool
	370
	371	config SYS_FSL_ERRATUM_A008585
	372	bool
	373
	374	config SYS_FSL_ERRATUM_A008850
	375	bool
	376
dd48f0bf A	377	config SYS_FSL_ERRATUM_A009203
	378	bool
	379
ba1b6fb5 YS	380	config SYS_FSL_ERRATUM_A009635
	381	bool
	382
	383	config SYS_FSL_ERRATUM_A009660
	384	bool
	385
	386	config SYS_FSL_ERRATUM_A009929
	387	bool
f692d4ee YS	388
	389	config SYS_MC_RSV_MEM_ALIGN
	390	hex "Management Complex reserved memory alignment"
	391	depends on RESV_RAM
	392	default 0x20000000
	393	help
	394	Reserved memory needs to be aligned for MC to use. Default value
	395	is 512MB.