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Commit | Line | Data |
---|---|---|
9533acf3 | 1 | config ARCH_LS1012A |
4a444176 | 2 | bool |
ee2a5102 | 3 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 4 | select FSL_LSCH2 |
24aaa094 | 5 | select SYS_FSL_DDR_BE |
9533acf3 | 6 | select SYS_FSL_MMDC |
0a37cf8f YS |
7 | select SYS_FSL_ERRATUM_A010315 |
8 | ||
9 | config ARCH_LS1043A | |
4a444176 | 10 | bool |
ee2a5102 | 11 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 12 | select FSL_LSCH2 |
d26e34c4 | 13 | select SYS_FSL_DDR |
24aaa094 YS |
14 | select SYS_FSL_DDR_BE |
15 | select SYS_FSL_DDR_VER_50 | |
ba1b6fb5 YS |
16 | select SYS_FSL_ERRATUM_A008850 |
17 | select SYS_FSL_ERRATUM_A009660 | |
18 | select SYS_FSL_ERRATUM_A009663 | |
19 | select SYS_FSL_ERRATUM_A009929 | |
20 | select SYS_FSL_ERRATUM_A009942 | |
0a37cf8f | 21 | select SYS_FSL_ERRATUM_A010315 |
0ea3671d | 22 | select SYS_FSL_ERRATUM_A010539 |
d26e34c4 YS |
23 | select SYS_FSL_HAS_DDR3 |
24 | select SYS_FSL_HAS_DDR4 | |
9533acf3 | 25 | |
da28e58a | 26 | config ARCH_LS1046A |
4a444176 | 27 | bool |
ee2a5102 | 28 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 29 | select FSL_LSCH2 |
d26e34c4 | 30 | select SYS_FSL_DDR |
24aaa094 | 31 | select SYS_FSL_DDR_BE |
24aaa094 | 32 | select SYS_FSL_DDR_VER_50 |
ba1b6fb5 YS |
33 | select SYS_FSL_ERRATUM_A008511 |
34 | select SYS_FSL_ERRATUM_A009801 | |
35 | select SYS_FSL_ERRATUM_A009803 | |
36 | select SYS_FSL_ERRATUM_A009942 | |
37 | select SYS_FSL_ERRATUM_A010165 | |
0ea3671d | 38 | select SYS_FSL_ERRATUM_A010539 |
d26e34c4 | 39 | select SYS_FSL_HAS_DDR4 |
f534b8f5 | 40 | select SYS_FSL_SRDS_2 |
9533acf3 | 41 | |
4a444176 YS |
42 | config ARCH_LS2080A |
43 | bool | |
ee2a5102 | 44 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 45 | select FSL_LSCH3 |
d26e34c4 | 46 | select SYS_FSL_DDR |
24aaa094 YS |
47 | select SYS_FSL_DDR_LE |
48 | select SYS_FSL_DDR_VER_50 | |
f534b8f5 | 49 | select SYS_FSL_HAS_DP_DDR |
2c2e2c9e | 50 | select SYS_FSL_HAS_SEC |
d26e34c4 | 51 | select SYS_FSL_HAS_DDR4 |
2c2e2c9e | 52 | select SYS_FSL_SEC_COMPAT_5 |
90b80386 | 53 | select SYS_FSL_SEC_LE |
f534b8f5 | 54 | select SYS_FSL_SRDS_2 |
ba1b6fb5 YS |
55 | select SYS_FSL_ERRATUM_A008336 |
56 | select SYS_FSL_ERRATUM_A008511 | |
57 | select SYS_FSL_ERRATUM_A008514 | |
58 | select SYS_FSL_ERRATUM_A008585 | |
59 | select SYS_FSL_ERRATUM_A009635 | |
60 | select SYS_FSL_ERRATUM_A009663 | |
61 | select SYS_FSL_ERRATUM_A009801 | |
62 | select SYS_FSL_ERRATUM_A009803 | |
63 | select SYS_FSL_ERRATUM_A009942 | |
64 | select SYS_FSL_ERRATUM_A010165 | |
fb2bf8c2 YS |
65 | |
66 | config FSL_LSCH2 | |
67 | bool | |
2c2e2c9e YS |
68 | select SYS_FSL_HAS_SEC |
69 | select SYS_FSL_SEC_COMPAT_5 | |
90b80386 | 70 | select SYS_FSL_SEC_BE |
f534b8f5 YS |
71 | select SYS_FSL_SRDS_1 |
72 | select SYS_HAS_SERDES | |
fb2bf8c2 YS |
73 | |
74 | config FSL_LSCH3 | |
75 | bool | |
f534b8f5 YS |
76 | select SYS_FSL_SRDS_1 |
77 | select SYS_HAS_SERDES | |
fb2bf8c2 YS |
78 | |
79 | menu "Layerscape architecture" | |
80 | depends on FSL_LSCH2 || FSL_LSCH3 | |
4a444176 | 81 | |
19538f30 HZ |
82 | config FSL_PCIE_COMPAT |
83 | string "PCIe compatible of Kernel DT" | |
84 | depends on PCIE_LAYERSCAPE | |
85 | default "fsl,ls1012a-pcie" if ARCH_LS1012A | |
86 | default "fsl,ls1043a-pcie" if ARCH_LS1043A | |
87 | default "fsl,ls1046a-pcie" if ARCH_LS1046A | |
88 | default "fsl,ls2080a-pcie" if ARCH_LS2080A | |
89 | help | |
90 | This compatible is used to find pci controller node in Kernel DT | |
91 | to complete fixup. | |
92 | ||
fa18ed76 WS |
93 | config HAS_FEATURE_GIC64K_ALIGN |
94 | bool | |
95 | default y if ARCH_LS1043A | |
96 | ||
97 | ||
2d16a1a6 | 98 | menu "Layerscape PPA" |
99 | config FSL_LS_PPA | |
100 | bool "FSL Layerscape PPA firmware support" | |
df88cb3b | 101 | depends on !ARMV8_PSCI |
2d16a1a6 | 102 | depends on ARCH_LS1043A || ARCH_LS1046A |
103 | select FSL_PPA_ARMV8_PSCI | |
104 | help | |
105 | The FSL Primary Protected Application (PPA) is a software component | |
106 | which is loaded during boot stage, and then remains resident in RAM | |
107 | and runs in the TrustZone after boot. | |
108 | Say y to enable it. | |
109 | ||
110 | config FSL_PPA_ARMV8_PSCI | |
111 | bool "PSCI implementation in PPA firmware" | |
112 | depends on FSL_LS_PPA | |
113 | help | |
114 | This config enables the ARMv8 PSCI implementation in PPA firmware. | |
115 | This is a private PSCI implementation and different from those | |
116 | implemented under the common ARMv8 PSCI framework. | |
117 | endmenu | |
118 | ||
0a37cf8f YS |
119 | config SYS_FSL_ERRATUM_A010315 |
120 | bool "Workaround for PCIe erratum A010315" | |
0ea3671d HZ |
121 | |
122 | config SYS_FSL_ERRATUM_A010539 | |
123 | bool "Workaround for PIN MUX erratum A010539" | |
fb2bf8c2 | 124 | |
b4b60d06 YS |
125 | config MAX_CPUS |
126 | int "Maximum number of CPUs permitted for Layerscape" | |
127 | default 4 if ARCH_LS1043A | |
128 | default 4 if ARCH_LS1046A | |
129 | default 16 if ARCH_LS2080A | |
130 | default 1 | |
131 | help | |
132 | Set this number to the maximum number of possible CPUs in the SoC. | |
133 | SoCs may have multiple clusters with each cluster may have multiple | |
134 | ports. If some ports are reserved but higher ports are used for | |
135 | cores, count the reserved ports. This will allocate enough memory | |
136 | in spin table to properly handle all cores. | |
137 | ||
01f65d97 | 138 | config SECURE_BOOT |
9cfab06e | 139 | bool "Secure Boot" |
01f65d97 YS |
140 | help |
141 | Enable Freescale Secure Boot feature | |
142 | ||
dd2ad2f1 YY |
143 | config QSPI_AHB_INIT |
144 | bool "Init the QSPI AHB bus" | |
145 | help | |
146 | The default setting for QSPI AHB bus just support 3bytes addressing. | |
147 | But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB | |
148 | bus for those flashes to support the full QSPI flash size. | |
149 | ||
25af7dc1 YS |
150 | config SYS_FSL_IFC_BANK_COUNT |
151 | int "Maximum banks of Integrated flash controller" | |
152 | depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A | |
153 | default 4 if ARCH_LS1043A | |
154 | default 4 if ARCH_LS1046A | |
155 | default 8 if ARCH_LS2080A | |
156 | ||
fd638102 YS |
157 | config SYS_FSL_HAS_DP_DDR |
158 | bool | |
159 | ||
f534b8f5 YS |
160 | config SYS_FSL_SRDS_1 |
161 | bool | |
162 | ||
163 | config SYS_FSL_SRDS_2 | |
164 | bool | |
165 | ||
166 | config SYS_HAS_SERDES | |
167 | bool | |
168 | ||
fb2bf8c2 | 169 | endmenu |
ba1b6fb5 | 170 | |
904110c7 HZ |
171 | menu "Layerscape clock tree configuration" |
172 | depends on FSL_LSCH2 || FSL_LSCH3 | |
173 | ||
174 | config SYS_FSL_CLK | |
175 | bool "Enable clock tree initialization" | |
176 | default y | |
177 | ||
178 | config CLUSTER_CLK_FREQ | |
179 | int "Reference clock of core cluster" | |
180 | depends on ARCH_LS1012A | |
181 | default 100000000 | |
182 | help | |
183 | This number is the reference clock frequency of core PLL. | |
184 | For most platforms, the core PLL and Platform PLL have the same | |
185 | reference clock, but for some platforms, LS1012A for instance, | |
186 | they are provided sepatately. | |
187 | ||
188 | config SYS_FSL_PCLK_DIV | |
189 | int "Platform clock divider" | |
190 | default 1 if ARCH_LS1043A | |
191 | default 1 if ARCH_LS1046A | |
192 | default 2 | |
193 | help | |
194 | This is the divider that is used to derive Platform clock from | |
195 | Platform PLL, in another word: | |
196 | Platform_clk = Platform_PLL_freq / this_divider | |
197 | ||
198 | config SYS_FSL_DSPI_CLK_DIV | |
199 | int "DSPI clock divider" | |
200 | default 1 if ARCH_LS1043A | |
201 | default 2 | |
202 | help | |
203 | This is the divider that is used to derive DSPI clock from Platform | |
204 | PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. | |
205 | ||
206 | config SYS_FSL_DUART_CLK_DIV | |
207 | int "DUART clock divider" | |
208 | default 1 if ARCH_LS1043A | |
209 | default 2 | |
210 | help | |
211 | This is the divider that is used to derive DUART clock from Platform | |
212 | clock, in another word DUART_clk = Platform_clk / this_divider. | |
213 | ||
214 | config SYS_FSL_I2C_CLK_DIV | |
215 | int "I2C clock divider" | |
216 | default 1 if ARCH_LS1043A | |
217 | default 2 | |
218 | help | |
219 | This is the divider that is used to derive I2C clock from Platform | |
220 | clock, in another word I2C_clk = Platform_clk / this_divider. | |
221 | ||
222 | config SYS_FSL_IFC_CLK_DIV | |
223 | int "IFC clock divider" | |
224 | default 1 if ARCH_LS1043A | |
225 | default 2 | |
226 | help | |
227 | This is the divider that is used to derive IFC clock from Platform | |
228 | clock, in another word IFC_clk = Platform_clk / this_divider. | |
229 | ||
230 | config SYS_FSL_LPUART_CLK_DIV | |
231 | int "LPUART clock divider" | |
232 | default 1 if ARCH_LS1043A | |
233 | default 2 | |
234 | help | |
235 | This is the divider that is used to derive LPUART clock from Platform | |
236 | clock, in another word LPUART_clk = Platform_clk / this_divider. | |
237 | ||
238 | config SYS_FSL_SDHC_CLK_DIV | |
239 | int "SDHC clock divider" | |
240 | default 1 if ARCH_LS1043A | |
241 | default 1 if ARCH_LS1012A | |
242 | default 2 | |
243 | help | |
244 | This is the divider that is used to derive SDHC clock from Platform | |
245 | clock, in another word SDHC_clk = Platform_clk / this_divider. | |
246 | endmenu | |
247 | ||
ba1b6fb5 YS |
248 | config SYS_FSL_ERRATUM_A008336 |
249 | bool | |
250 | ||
251 | config SYS_FSL_ERRATUM_A008514 | |
252 | bool | |
253 | ||
254 | config SYS_FSL_ERRATUM_A008585 | |
255 | bool | |
256 | ||
257 | config SYS_FSL_ERRATUM_A008850 | |
258 | bool | |
259 | ||
260 | config SYS_FSL_ERRATUM_A009635 | |
261 | bool | |
262 | ||
263 | config SYS_FSL_ERRATUM_A009660 | |
264 | bool | |
265 | ||
266 | config SYS_FSL_ERRATUM_A009929 | |
267 | bool |