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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / cpu.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
2f78eae5 2/*
8976556a 3 * Copyright 2017-2021 NXP
9f3183d2 4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
2f78eae5
YS		 5 */
6
d678a59d 7#include <common.h>
2f8a6db5 8#include <clock_legacy.h>
b5981474 9#include <cpu_func.h>
3a7d5571 10#include <env.h>
9b4a205f 11#include <init.h>
db41d65a 12#include <hang.h>
f7ae49fc 13#include <log.h>
90526e9f 14#include <net.h>
2189d5f1 15#include <vsprintf.h>
90526e9f 16#include <asm/cache.h>
401d1c4f 17#include <asm/global_data.h>
2f78eae5 18#include <asm/io.h>
25a5818f 19#include <asm/ptrace.h>
cb14cc88 20#include <linux/arm-smccc.h>
1221ce45 21#include <linux/errno.h>
2f78eae5 22#include <asm/system.h>
9cce5663 23#include <fm_eth.h>
2f78eae5
YS		 24#include <asm/armv8/mmu.h>
25#include <asm/io.h>
9f3183d2
MH		 26#include <asm/arch/fsl_serdes.h>
27#include <asm/arch/soc.h>
28#include <asm/arch/cpu.h>
29#include <asm/arch/speed.h>
63b2316c 30#include <fsl_immap.h>
9f3183d2 31#include <asm/arch/mp.h>
78d57842 32#include <efi_loader.h>
7b3bd9a7 33#include <fsl-mc/fsl_mc.h>
8b06460e
YL		 34#ifdef CONFIG_FSL_ESDHC
35#include <fsl_esdhc.h>
36#endif
032d5bb4 37#include <asm/armv8/sec_firmware.h>
02fb2761 38#ifdef CONFIG_SYS_FSL_DDR
f9147d63 39#include <fsl_ddr_sdram.h>
02fb2761
SL		 40#include <fsl_ddr.h>
41#endif
6e2941d7 42#include <asm/arch/clock.h>
2db53cfe 43#include <hwconfig.h>
44262327 44#include <fsl_qbman.h>
2f78eae5 45
4c417384 46#ifdef CONFIG_TFABOOT
f3998fdc 47#include <env_internal.h>
2141d250
PG		 48#ifdef CONFIG_CHAIN_OF_TRUST
49#include <fsl_validate.h>
50#endif
4c417384 51#endif
68a6aa85 52#include <linux/mii.h>
8976556a 53#include <dm.h>
4c417384 54
2f78eae5
YS		 55DECLARE_GLOBAL_DATA_PTR;
56
d171c707
YS		 57static struct cpu_type cpu_type_list[] = {
58 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
59 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
60 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
61 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
62 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
63 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
64 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
65 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
66 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
67 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
ec88ff80 68 CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
d171c707 69 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
ec88ff80 70 CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
d171c707
YS		 71 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
72 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
73 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
74 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
6ed69523
YT		 75 CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
76 CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
77 CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
d4ad111d 78 CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
d171c707
YS		 79 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
80 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
81 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
82 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
4909b89e
PJ		 83 CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
84 CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
85 CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
3a187cff
MA		 86 CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
87 CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
88 CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
d171c707
YS		 89};
90
91#define EARLY_PGTABLE_SIZE 0x5000
92static struct mm_region early_map[] = {
93#ifdef CONFIG_FSL_LSCH3
6e7df1d1
TR		 94 { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
95 CFG_SYS_FSL_CCSR_SIZE,
d171c707
YS		 96 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
97 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
98 },
6cc04547 99 { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
d171c707
YS		 100 SYS_FSL_OCRAM_SPACE_SIZE,
101 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
102 },
6cc04547 103 { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
6e7df1d1 104 CFG_SYS_FSL_QSPI_SIZE1,
d171c707
YS		 105 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
106#ifdef CONFIG_FSL_IFC
107 /* For IFC Region #1, only the first 4MB is cache-enabled */
6e7df1d1
TR		 108 { CFG_SYS_FSL_IFC_BASE1, CFG_SYS_FSL_IFC_BASE1,
109 CFG_SYS_FSL_IFC_SIZE1_1,
d171c707
YS		 110 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
111 },
6e7df1d1
TR		 112 { CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1,
113 CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1,
114 CFG_SYS_FSL_IFC_SIZE1 - CFG_SYS_FSL_IFC_SIZE1_1,
d171c707
YS		 115 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
116 },
6e7df1d1
TR		 117 { CFG_SYS_FLASH_BASE, CFG_SYS_FSL_IFC_BASE1,
118 CFG_SYS_FSL_IFC_SIZE1,
d171c707
YS		 119 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
120 },
121#endif
6e7df1d1
TR		 122 { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
123 CFG_SYS_FSL_DRAM_SIZE1,
535d76a1
RB		 124#if defined(CONFIG_TFABOOT) || \
125 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
d171c707
YS		 126 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
127#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
128 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
129#endif
130 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
131 },
132#ifdef CONFIG_FSL_IFC
65cc0e2a 133 /* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
6e7df1d1
TR		 134 { CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2,
135 CFG_SYS_FLASH_BASE - CFG_SYS_FSL_IFC_BASE2,
d171c707
YS		 136 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
137 },
138#endif
6e7df1d1
TR		 139 { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
140 CFG_SYS_FSL_DCSR_SIZE,
d171c707
YS		 141 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
142 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
143 },
6e7df1d1
TR		 144 { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
145 CFG_SYS_FSL_DRAM_SIZE2,
d171c707
YS		 146 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
147 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
148 },
6e7df1d1
TR		 149#ifdef CFG_SYS_FSL_DRAM_BASE3
150 { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
151 CFG_SYS_FSL_DRAM_SIZE3,
d6fdec21
PJ		 152 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
153 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
154 },
155#endif
d171c707 156#elif defined(CONFIG_FSL_LSCH2)
6e7df1d1
TR		 157 { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
158 CFG_SYS_FSL_CCSR_SIZE,
d171c707
YS		 159 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
160 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
161 },
6cc04547 162 { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
d171c707
YS		 163 SYS_FSL_OCRAM_SPACE_SIZE,
164 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
165 },
6e7df1d1
TR		 166 { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
167 CFG_SYS_FSL_DCSR_SIZE,
d171c707
YS		 168 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
169 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
170 },
6cc04547 171 { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
6e7df1d1 172 CFG_SYS_FSL_QSPI_SIZE,
d171c707
YS		 173 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
174 },
175#ifdef CONFIG_FSL_IFC
6e7df1d1
TR		 176 { CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE,
177 CFG_SYS_FSL_IFC_SIZE,
d171c707
YS		 178 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
179 },
180#endif
6e7df1d1
TR		 181 { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
182 CFG_SYS_FSL_DRAM_SIZE1,
535d76a1
RB		 183#if defined(CONFIG_TFABOOT) || \
184 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
d171c707
YS		 185 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
186#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
187 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
188#endif
189 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
190 },
6e7df1d1
TR		 191 { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
192 CFG_SYS_FSL_DRAM_SIZE2,
d171c707
YS		 193 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
194 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
195 },
196#endif
197 {}, /* list terminator */
198};
199
200static struct mm_region final_map[] = {
201#ifdef CONFIG_FSL_LSCH3
6e7df1d1
TR		 202 { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
203 CFG_SYS_FSL_CCSR_SIZE,
d171c707
YS		 204 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
205 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
206 },
6cc04547 207 { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
d171c707
YS		 208 SYS_FSL_OCRAM_SPACE_SIZE,
209 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
210 },
6e7df1d1
TR		 211 { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
212 CFG_SYS_FSL_DRAM_SIZE1,
d171c707
YS		 213 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
214 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
215 },
6cc04547 216 { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
6e7df1d1 217 CFG_SYS_FSL_QSPI_SIZE1,
d171c707
YS		 218 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
219 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
220 },
6cc04547 221 { CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
6e7df1d1 222 CFG_SYS_FSL_QSPI_SIZE2,
d171c707
YS		 223 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
224 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
225 },
226#ifdef CONFIG_FSL_IFC
6e7df1d1
TR		 227 { CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2,
228 CFG_SYS_FSL_IFC_SIZE2,
d171c707
YS		 229 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
230 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
231 },
232#endif
6e7df1d1
TR		 233 { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
234 CFG_SYS_FSL_DCSR_SIZE,
d171c707
YS		 235 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
236 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
237 },
6e7df1d1
TR		 238 { CFG_SYS_FSL_MC_BASE, CFG_SYS_FSL_MC_BASE,
239 CFG_SYS_FSL_MC_SIZE,
d171c707
YS		 240 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
241 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
242 },
6e7df1d1
TR		 243 { CFG_SYS_FSL_NI_BASE, CFG_SYS_FSL_NI_BASE,
244 CFG_SYS_FSL_NI_SIZE,
d171c707
YS		 245 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
246 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
247 },
248 /* For QBMAN portal, only the first 64MB is cache-enabled */
6e7df1d1
TR		 249 { CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE,
250 CFG_SYS_FSL_QBMAN_SIZE_1,
d171c707
YS		 251 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
252 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
253 },
6e7df1d1
TR		 254 { CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1,
255 CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1,
256 CFG_SYS_FSL_QBMAN_SIZE - CFG_SYS_FSL_QBMAN_SIZE_1,
d171c707
YS		 257 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
258 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
259 },
ecc8d425
TR		 260 { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
261 CFG_SYS_PCIE1_PHYS_SIZE,
d171c707
YS		 262 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
263 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
264 },
ecc8d425
TR		 265 { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
266 CFG_SYS_PCIE2_PHYS_SIZE,
d171c707
YS		 267 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
268 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
269 },
ecc8d425
TR		 270#ifdef CFG_SYS_PCIE3_PHYS_ADDR
271 { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
272 CFG_SYS_PCIE3_PHYS_SIZE,
d171c707
YS		 273 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
274 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
275 },
d4ad111d 276#endif
ecc8d425
TR		 277#ifdef CFG_SYS_PCIE4_PHYS_ADDR
278 { CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR,
279 CFG_SYS_PCIE4_PHYS_SIZE,
d171c707
YS		 280 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
281 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
282 },
059d9422
HZ		 283#endif
284#ifdef SYS_PCIE5_PHYS_ADDR
285 { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
286 SYS_PCIE5_PHYS_SIZE,
287 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
288 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
289 },
290#endif
291#ifdef SYS_PCIE6_PHYS_ADDR
292 { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
293 SYS_PCIE6_PHYS_SIZE,
294 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
295 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
296 },
d171c707 297#endif
6e7df1d1
TR		 298 { CFG_SYS_FSL_WRIOP1_BASE, CFG_SYS_FSL_WRIOP1_BASE,
299 CFG_SYS_FSL_WRIOP1_SIZE,
d171c707
YS		 300 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
301 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
302 },
6e7df1d1
TR		 303 { CFG_SYS_FSL_AIOP1_BASE, CFG_SYS_FSL_AIOP1_BASE,
304 CFG_SYS_FSL_AIOP1_SIZE,
d171c707
YS		 305 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
306 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
307 },
6e7df1d1
TR		 308 { CFG_SYS_FSL_PEBUF_BASE, CFG_SYS_FSL_PEBUF_BASE,
309 CFG_SYS_FSL_PEBUF_SIZE,
d171c707
YS		 310 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
311 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
312 },
6e7df1d1
TR		 313 { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
314 CFG_SYS_FSL_DRAM_SIZE2,
d171c707
YS		 315 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
316 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
317 },
6e7df1d1
TR		 318#ifdef CFG_SYS_FSL_DRAM_BASE3
319 { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
320 CFG_SYS_FSL_DRAM_SIZE3,
d6fdec21
PJ		 321 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
322 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
323 },
324#endif
d171c707
YS		 325#elif defined(CONFIG_FSL_LSCH2)
326 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
327 CONFIG_SYS_FSL_BOOTROM_SIZE,
328 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
329 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
330 },
6e7df1d1
TR		 331 { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
332 CFG_SYS_FSL_CCSR_SIZE,
d171c707
YS		 333 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
334 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
335 },
6cc04547 336 { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
d171c707
YS		 337 SYS_FSL_OCRAM_SPACE_SIZE,
338 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
339 },
6e7df1d1
TR		 340 { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
341 CFG_SYS_FSL_DCSR_SIZE,
d171c707
YS		 342 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
343 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
344 },
6cc04547 345 { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
6e7df1d1 346 CFG_SYS_FSL_QSPI_SIZE,
d171c707
YS		 347 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
348 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
349 },
350#ifdef CONFIG_FSL_IFC
6e7df1d1
TR		 351 { CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE,
352 CFG_SYS_FSL_IFC_SIZE,
d171c707
YS		 353 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
354 },
355#endif
6e7df1d1
TR		 356 { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
357 CFG_SYS_FSL_DRAM_SIZE1,
d171c707
YS		 358 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
359 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
360 },
6e7df1d1
TR		 361 { CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE,
362 CFG_SYS_FSL_QBMAN_SIZE,
d171c707
YS		 363 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
364 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
365 },
6e7df1d1
TR		 366 { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
367 CFG_SYS_FSL_DRAM_SIZE2,
d171c707
YS		 368 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
369 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
370 },
ecc8d425
TR		 371 { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
372 CFG_SYS_PCIE1_PHYS_SIZE,
d171c707
YS		 373 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
374 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
375 },
ecc8d425
TR		 376 { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
377 CFG_SYS_PCIE2_PHYS_SIZE,
d171c707
YS		 378 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
379 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
380 },
ecc8d425
TR		 381#ifdef CFG_SYS_PCIE3_PHYS_ADDR
382 { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
383 CFG_SYS_PCIE3_PHYS_SIZE,
d171c707
YS		 384 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
385 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
386 },
d4ad111d 387#endif
6e7df1d1
TR		 388 { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
389 CFG_SYS_FSL_DRAM_SIZE3,
d171c707
YS		 390 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
391 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
392 },
393#endif
65cc0e2a 394#ifdef CFG_SYS_MEM_RESERVE_SECURE
d171c707
YS		 395 {}, /* space holder for secure mem */
396#endif
397 {},
398};
399
5ad5823d 400struct mm_region *mem_map = early_map;
7985cdf7 401
22629665
PK		 402void cpu_name(char *name)
403{
6cc04547 404 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
22629665
PK		 405 unsigned int i, svr, ver;
406
9f3183d2 407 svr = gur_in32(&gur->svr);
22629665
PK		 408 ver = SVR_SOC_VER(svr);
409
410 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
411 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
412 strcpy(name, cpu_type_list[i].name);
3a187cff 413#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
4909b89e
PJ		 414 if (IS_C_PROCESSOR(svr))
415 strcat(name, "C");
416#endif
22629665
PK		 417
418 if (IS_E_PROCESSOR(svr))
419 strcat(name, "E");
5d1a7a9d
WS		 420
421 sprintf(name + strlen(name), " Rev%d.%d",
422 SVR_MAJ(svr), SVR_MIN(svr));
22629665
PK		 423 break;
424 }
425
426 if (i == ARRAY_SIZE(cpu_type_list))
427 strcpy(name, "unknown");
428}
429
10015025 430#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
99799220
AW		 431/*
432 * To start MMU before DDR is available, we create MMU table in SRAM.
6cc04547 433 * The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three
99799220
AW		 434 * levels of translation tables here to cover 40-bit address space.
435 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
5ad5823d
YS		 436 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
437 * Note, the debug print in cache_v8.c is not usable for debugging
438 * these early MMU tables because UART is not yet available.
99799220
AW		 439 */
440static inline void early_mmu_setup(void)
441{
5ad5823d 442 unsigned int el = current_el();
99799220 443
5ad5823d 444 /* global data is already setup, no allocation yet */
e3506480 445 if (el == 3)
6cc04547 446 gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
e3506480 447 else
65cc0e2a 448 gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
5ad5823d
YS		 449 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
450 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
99799220 451
5ad5823d
YS		 452 /* Create early page tables */
453 setup_pgtables();
9f3183d2 454
5ad5823d
YS		 455 /* point TTBR to the new table */
456 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
ce9c579e 457 get_tcr(NULL, NULL) &
5ad5823d 458 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
9f3183d2 459 MEMORY_ATTRIBUTES);
c107c0c0 460
5ad5823d 461 set_sctlr(get_sctlr() | CR_M);
c107c0c0 462}
c107c0c0 463
3d8553f0
HZ		 464static void fix_pcie_mmu_map(void)
465{
4a3ab193 466#ifdef CONFIG_ARCH_LS2080A
3d8553f0
HZ		 467 unsigned int i;
468 u32 svr, ver;
6cc04547 469 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
3d8553f0
HZ		 470
471 svr = gur_in32(&gur->svr);
472 ver = SVR_SOC_VER(svr);
473
474 /* Fix PCIE base and size for LS2088A */
475 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
e809e747
PJ		 476 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
477 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
3d8553f0
HZ		 478 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
479 switch (final_map[i].phys) {
ecc8d425 480 case CFG_SYS_PCIE1_PHYS_ADDR:
3d8553f0
HZ		 481 final_map[i].phys = 0x2000000000ULL;
482 final_map[i].virt = 0x2000000000ULL;
483 final_map[i].size = 0x800000000ULL;
484 break;
ecc8d425 485 case CFG_SYS_PCIE2_PHYS_ADDR:
3d8553f0
HZ		 486 final_map[i].phys = 0x2800000000ULL;
487 final_map[i].virt = 0x2800000000ULL;
488 final_map[i].size = 0x800000000ULL;
489 break;
ecc8d425
TR		 490#ifdef CFG_SYS_PCIE3_PHYS_ADDR
491 case CFG_SYS_PCIE3_PHYS_ADDR:
3d8553f0
HZ		 492 final_map[i].phys = 0x3000000000ULL;
493 final_map[i].virt = 0x3000000000ULL;
494 final_map[i].size = 0x800000000ULL;
495 break;
d4ad111d 496#endif
ecc8d425
TR		 497#ifdef CFG_SYS_PCIE4_PHYS_ADDR
498 case CFG_SYS_PCIE4_PHYS_ADDR:
3d8553f0
HZ		 499 final_map[i].phys = 0x3800000000ULL;
500 final_map[i].virt = 0x3800000000ULL;
501 final_map[i].size = 0x800000000ULL;
502 break;
8348e798 503#endif
3d8553f0
HZ		 504 default:
505 break;
506 }
507 }
508 }
509#endif
510}
511
2f78eae5 512/*
99799220
AW		 513 * The final tables look similar to early tables, but different in detail.
514 * These tables are in DRAM. Sub tables are added to enable cache for
515 * QBMan and OCRAM.
516 *
e61a7534
YS		 517 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
518 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
2f78eae5
YS		 519 */
520static inline void final_mmu_setup(void)
521{
5ad5823d 522 u64 tlb_addr_save = gd->arch.tlb_addr;
c107c0c0 523 unsigned int el = current_el();
5ad5823d 524 int index;
2f78eae5 525
3d8553f0
HZ		 526 /* fix the final_map before filling in the block entries */
527 fix_pcie_mmu_map();
528
5ad5823d 529 mem_map = final_map;
2f78eae5 530
24f55496
YS		 531 /* Update mapping for DDR to actual size */
532 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
533 /*
534 * Find the entry for DDR mapping and update the address and
535 * size. Zero-sized mapping will be skipped when creating MMU
536 * table.
537 */
538 switch (final_map[index].virt) {
6e7df1d1 539 case CFG_SYS_FSL_DRAM_BASE1:
24f55496
YS		 540 final_map[index].virt = gd->bd->bi_dram[0].start;
541 final_map[index].phys = gd->bd->bi_dram[0].start;
542 final_map[index].size = gd->bd->bi_dram[0].size;
543 break;
6e7df1d1
TR		 544#ifdef CFG_SYS_FSL_DRAM_BASE2
545 case CFG_SYS_FSL_DRAM_BASE2:
24f55496
YS		 546#if (CONFIG_NR_DRAM_BANKS >= 2)
547 final_map[index].virt = gd->bd->bi_dram[1].start;
548 final_map[index].phys = gd->bd->bi_dram[1].start;
549 final_map[index].size = gd->bd->bi_dram[1].size;
550#else
551 final_map[index].size = 0;
552#endif
553 break;
554#endif
6e7df1d1
TR		 555#ifdef CFG_SYS_FSL_DRAM_BASE3
556 case CFG_SYS_FSL_DRAM_BASE3:
24f55496
YS		 557#if (CONFIG_NR_DRAM_BANKS >= 3)
558 final_map[index].virt = gd->bd->bi_dram[2].start;
559 final_map[index].phys = gd->bd->bi_dram[2].start;
560 final_map[index].size = gd->bd->bi_dram[2].size;
561#else
562 final_map[index].size = 0;
563#endif
564 break;
565#endif
566 default:
567 break;
568 }
569 }
570
65cc0e2a 571#ifdef CFG_SYS_MEM_RESERVE_SECURE
5ad5823d
YS		 572 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
573 if (el == 3) {
574 /*
575 * Only use gd->arch.secure_ram if the address is
576 * recalculated. Align to 4KB for MMU table.
577 */
578 /* put page tables in secure ram */
579 index = ARRAY_SIZE(final_map) - 2;
580 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
581 final_map[index].virt = gd->arch.secure_ram & ~0x3;
582 final_map[index].phys = final_map[index].virt;
65cc0e2a 583 final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
5ad5823d 584 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
e61a7534 585 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
5ad5823d 586 tlb_addr_save = gd->arch.tlb_addr;
c107c0c0 587 } else {
5ad5823d
YS		 588 /* Use allocated (board_f.c) memory for TLB */
589 tlb_addr_save = gd->arch.tlb_allocated;
590 gd->arch.tlb_addr = tlb_addr_save;
c107c0c0
YS		 591 }
592 }
593#endif
2f78eae5 594
5ad5823d
YS		 595 /* Reset the fill ptr */
596 gd->arch.tlb_fillptr = tlb_addr_save;
597
598 /* Create normal system page tables */
599 setup_pgtables();
600
601 /* Create emergency page tables */
602 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
603 gd->arch.tlb_emerg = gd->arch.tlb_addr;
604 setup_pgtables();
605 gd->arch.tlb_addr = tlb_addr_save;
606
a045a0c3
YS		 607 /* Disable cache and MMU */
608 dcache_disable(); /* TLBs are invalidated */
609 invalidate_icache_all();
2f78eae5
YS		 610
611 /* point TTBR to the new table */
ce9c579e 612 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
db14f11d 613 MEMORY_ATTRIBUTES);
a045a0c3 614
ed7a3943 615 set_sctlr(get_sctlr() | CR_M);
2f78eae5
YS		 616}
617
c05016ab
AG		 618u64 get_page_table_size(void)
619{
620 return 0x10000;
621}
622
2f78eae5
YS		 623int arch_cpu_init(void)
624{
399e2bb6
YS		 625 /*
626 * This function is called before U-Boot relocates itself to speed up
627 * on system running. It is not necessary to run if performance is not
628 * critical. Skip if MMU is already enabled by SPL or other means.
629 */
630 if (get_sctlr() & CR_M)
631 return 0;
632
2f78eae5
YS		 633 icache_enable();
634 __asm_invalidate_dcache_all();
635 __asm_invalidate_tlb_all();
636 early_mmu_setup();
637 set_sctlr(get_sctlr() | CR_C);
638 return 0;
639}
640
85cdf38e
HZ		 641void mmu_setup(void)
642{
643 final_mmu_setup();
644}
645
2f78eae5 646/*
85cdf38e
HZ		 647 * This function is called from common/board_r.c.
648 * It recreates MMU table in main memory.
2f78eae5
YS		 649 */
650void enable_caches(void)
651{
85cdf38e 652 mmu_setup();
2f78eae5 653 __asm_invalidate_tlb_all();
85cdf38e
HZ		 654 icache_enable();
655 dcache_enable();
2f78eae5 656}
10015025 657#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
4c417384
RB		 658
659#ifdef CONFIG_TFABOOT
660enum boot_src __get_boot_src(u32 porsr1)
661{
662 enum boot_src src = BOOT_SOURCE_RESERVED;
663 u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
d6fdec21 664#if !defined(CONFIG_NXP_LSCH3_2)
4c417384
RB		 665 u32 val;
666#endif
667 debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
668
669#if defined(CONFIG_FSL_LSCH3)
d6fdec21 670#if defined(CONFIG_NXP_LSCH3_2)
4c417384
RB		 671 switch (rcw_src) {
672 case RCW_SRC_SDHC1_VAL:
673 src = BOOT_SOURCE_SD_MMC;
674 break;
675 case RCW_SRC_SDHC2_VAL:
676 src = BOOT_SOURCE_SD_MMC2;
677 break;
678 case RCW_SRC_I2C1_VAL:
679 src = BOOT_SOURCE_I2C1_EXTENDED;
680 break;
681 case RCW_SRC_FLEXSPI_NAND2K_VAL:
682 src = BOOT_SOURCE_XSPI_NAND;
683 break;
684 case RCW_SRC_FLEXSPI_NAND4K_VAL:
685 src = BOOT_SOURCE_XSPI_NAND;
686 break;
687 case RCW_SRC_RESERVED_1_VAL:
688 src = BOOT_SOURCE_RESERVED;
689 break;
690 case RCW_SRC_FLEXSPI_NOR_24B:
691 src = BOOT_SOURCE_XSPI_NOR;
692 break;
693 default:
694 src = BOOT_SOURCE_RESERVED;
695 }
696#else
697 val = rcw_src & RCW_SRC_TYPE_MASK;
698 if (val == RCW_SRC_NOR_VAL) {
699 val = rcw_src & NOR_TYPE_MASK;
700
701 switch (val) {
702 case NOR_16B_VAL:
703 case NOR_32B_VAL:
704 src = BOOT_SOURCE_IFC_NOR;
705 break;
706 default:
707 src = BOOT_SOURCE_RESERVED;
708 }
709 } else {
710 /* RCW SRC Serial Flash */
711 val = rcw_src & RCW_SRC_SERIAL_MASK;
712 switch (val) {
713 case RCW_SRC_QSPI_VAL:
714 /* RCW SRC Serial NOR (QSPI) */
715 src = BOOT_SOURCE_QSPI_NOR;
716 break;
717 case RCW_SRC_SD_CARD_VAL:
718 /* RCW SRC SD Card */
719 src = BOOT_SOURCE_SD_MMC;
720 break;
721 case RCW_SRC_EMMC_VAL:
722 /* RCW SRC EMMC */
d23da2ae 723 src = BOOT_SOURCE_SD_MMC;
4c417384
RB		 724 break;
725 case RCW_SRC_I2C1_VAL:
726 /* RCW SRC I2C1 Extended */
727 src = BOOT_SOURCE_I2C1_EXTENDED;
728 break;
729 default:
730 src = BOOT_SOURCE_RESERVED;
731 }
732 }
2f78eae5 733#endif
4c417384
RB		 734#elif defined(CONFIG_FSL_LSCH2)
735 /* RCW SRC NAND */
736 val = rcw_src & RCW_SRC_NAND_MASK;
737 if (val == RCW_SRC_NAND_VAL) {
738 val = rcw_src & NAND_RESERVED_MASK;
739 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
740 src = BOOT_SOURCE_IFC_NAND;
741
742 } else {
743 /* RCW SRC NOR */
744 val = rcw_src & RCW_SRC_NOR_MASK;
745 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
746 src = BOOT_SOURCE_IFC_NOR;
747 } else {
748 switch (rcw_src) {
749 case QSPI_VAL1:
750 case QSPI_VAL2:
751 src = BOOT_SOURCE_QSPI_NOR;
752 break;
753 case SD_VAL:
754 src = BOOT_SOURCE_SD_MMC;
755 break;
756 default:
757 src = BOOT_SOURCE_RESERVED;
758 }
759 }
760 }
761#endif
56db948b 762
e7ec875d 763 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010539) && !rcw_src)
56db948b
YS		 764 src = BOOT_SOURCE_QSPI_NOR;
765
4c417384
RB		 766 debug("%s: src 0x%x\n", __func__, src);
767 return src;
768}
769
770enum boot_src get_boot_src(void)
771{
cb14cc88 772 struct arm_smccc_res res;
56db948b 773 u32 porsr1 = 0;
4c417384
RB		 774
775#if defined(CONFIG_FSL_LSCH3)
776 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
4c417384 777#elif defined(CONFIG_FSL_LSCH2)
6cc04547 778 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
56db948b
YS		 779#endif
780
781 if (current_el() == 2) {
cb14cc88
MW		 782 arm_smccc_smc(SIP_SVC_RCW, 0, 0, 0, 0, 0, 0, 0, &res);
783 if (!res.a0)
784 porsr1 = res.a1;
56db948b
YS		 785 }
786
787 if (current_el() == 3 || !porsr1) {
788#ifdef CONFIG_FSL_LSCH3
789 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
790#elif defined(CONFIG_FSL_LSCH2)
791 porsr1 = in_be32(&gur->porsr1);
4c417384 792#endif
56db948b
YS		 793 }
794
4c417384
RB		 795 debug("%s: porsr1 0x%x\n", __func__, porsr1);
796
797 return __get_boot_src(porsr1);
798}
799
800#ifdef CONFIG_ENV_IS_IN_MMC
801int mmc_get_env_dev(void)
802{
803 enum boot_src src = get_boot_src();
804 int dev = CONFIG_SYS_MMC_ENV_DEV;
805
806 switch (src) {
807 case BOOT_SOURCE_SD_MMC:
808 dev = 0;
809 break;
810 case BOOT_SOURCE_SD_MMC2:
811 dev = 1;
812 break;
813 default:
814 break;
815 }
816
817 return dev;
818}
819#endif
820
dfb6da55 821enum env_location arch_env_get_location(enum env_operation op, int prio)
4c417384
RB		 822{
823 enum boot_src src = get_boot_src();
824 enum env_location env_loc = ENVL_NOWHERE;
825
826 if (prio)
827 return ENVL_UNKNOWN;
828
d9532e80
UA		 829#ifdef CONFIG_ENV_IS_NOWHERE
830 return env_loc;
2141d250
PG		 831#endif
832
4c417384
RB		 833 switch (src) {
834 case BOOT_SOURCE_IFC_NOR:
835 env_loc = ENVL_FLASH;
836 break;
837 case BOOT_SOURCE_QSPI_NOR:
838 /* FALLTHROUGH */
839 case BOOT_SOURCE_XSPI_NOR:
840 env_loc = ENVL_SPI_FLASH;
841 break;
842 case BOOT_SOURCE_IFC_NAND:
843 /* FALLTHROUGH */
844 case BOOT_SOURCE_QSPI_NAND:
845 /* FALLTHROUGH */
846 case BOOT_SOURCE_XSPI_NAND:
847 env_loc = ENVL_NAND;
848 break;
849 case BOOT_SOURCE_SD_MMC:
850 /* FALLTHROUGH */
851 case BOOT_SOURCE_SD_MMC2:
852 env_loc = ENVL_MMC;
853 break;
854 case BOOT_SOURCE_I2C1_EXTENDED:
855 /* FALLTHROUGH */
856 default:
857 break;
858 }
859
860 return env_loc;
861}
862#endif /* CONFIG_TFABOOT */
2f78eae5 863
e87c673c 864u32 initiator_type(u32 cluster, int init_id)
2f78eae5 865{
6cc04547 866 struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
2f78eae5 867 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
9f3183d2 868 u32 type = 0;
2f78eae5 869
9f3183d2 870 type = gur_in32(&gur->tp_ityp[idx]);
2f78eae5
YS		 871 if (type & TP_ITYP_AV)
872 return type;
873
874 return 0;
875}
876
ef9a5fd8
YS		 877u32 cpu_pos_mask(void)
878{
6cc04547 879 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
ef9a5fd8
YS		 880 int i = 0;
881 u32 cluster, type, mask = 0;
882
883 do {
884 int j;
885
886 cluster = gur_in32(&gur->tp_cluster[i].lower);
887 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
888 type = initiator_type(cluster, j);
889 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
890 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
891 }
892 i++;
893 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
894
895 return mask;
896}
897
2f78eae5
YS		 898u32 cpu_mask(void)
899{
6cc04547 900 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
2f78eae5
YS		 901 int i = 0, count = 0;
902 u32 cluster, type, mask = 0;
903
904 do {
905 int j;
9f3183d2
MH		 906
907 cluster = gur_in32(&gur->tp_cluster[i].lower);
2f78eae5
YS		 908 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
909 type = initiator_type(cluster, j);
910 if (type) {
911 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
912 mask |= 1 << count;
913 count++;
914 }
915 }
916 i++;
9f3183d2 917 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
2f78eae5
YS		 918
919 return mask;
920}
921
922/*
923 * Return the number of cores on this SOC.
924 */
925int cpu_numcores(void)
926{
927 return hweight32(cpu_mask());
928}
929
930int fsl_qoriq_core_to_cluster(unsigned int core)
931{
932 struct ccsr_gur __iomem *gur =
6cc04547 933 (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
2f78eae5
YS		 934 int i = 0, count = 0;
935 u32 cluster;
936
937 do {
938 int j;
9f3183d2
MH		 939
940 cluster = gur_in32(&gur->tp_cluster[i].lower);
2f78eae5
YS		 941 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
942 if (initiator_type(cluster, j)) {
943 if (count == core)
944 return i;
945 count++;
946 }
947 }
948 i++;
9f3183d2 949 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
2f78eae5
YS		 950
951 return -1; /* cannot identify the cluster */
952}
953
954u32 fsl_qoriq_core_to_type(unsigned int core)
955{
956 struct ccsr_gur __iomem *gur =
6cc04547 957 (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
2f78eae5
YS		 958 int i = 0, count = 0;
959 u32 cluster, type;
960
961 do {
962 int j;
9f3183d2
MH		 963
964 cluster = gur_in32(&gur->tp_cluster[i].lower);
2f78eae5
YS		 965 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
966 type = initiator_type(cluster, j);
967 if (type) {
968 if (count == core)
969 return type;
970 count++;
971 }
972 }
973 i++;
9f3183d2 974 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
2f78eae5
YS		 975
976 return -1; /* cannot identify the cluster */
977}
978
f6a70b3a 979#ifndef CONFIG_FSL_LSCH3
6fb522dc
SD		 980uint get_svr(void)
981{
6cc04547 982 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
6fb522dc
SD		 983
984 return gur_in32(&gur->svr);
985}
f6a70b3a 986#endif
6fb522dc 987
2f78eae5
YS		 988#ifdef CONFIG_DISPLAY_CPUINFO
989int print_cpuinfo(void)
990{
6cc04547 991 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
2f78eae5
YS		 992 struct sys_info sysinfo;
993 char buf[32];
994 unsigned int i, core;
3c1d218a 995 u32 type, rcw, svr = gur_in32(&gur->svr);
2f78eae5 996
22629665
PK		 997 puts("SoC: ");
998
999 cpu_name(buf);
3c1d218a 1000 printf(" %s (0x%x)\n", buf, svr);
22629665 1001 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
2f78eae5
YS		 1002 get_sys_info(&sysinfo);
1003 puts("Clock Configuration:");
1004 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
1005 if (!(i % 3))
1006 puts("\n ");
1007 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
1008 printf("CPU%d(%s):%-4s MHz ", core,
1009 type == TY_ITYP_VER_A7 ? "A7 " :
1010 (type == TY_ITYP_VER_A53 ? "A53" :
79119a4d
AW		 1011 (type == TY_ITYP_VER_A57 ? "A57" :
1012 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
2f78eae5
YS		 1013 strmhz(buf, sysinfo.freq_processor[core]));
1014 }
904110c7 1015 /* Display platform clock as Bus frequency. */
2f78eae5 1016 printf("\n Bus: %-4s MHz ",
904110c7 1017 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
d4c711f0 1018 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
e8297341
SX		 1019#ifdef CONFIG_SYS_DPAA_FMAN
1020 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1021#endif
44937214 1022#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
3c1d218a
YS		 1023 if (soc_has_dp_ddr()) {
1024 printf(" DP-DDR: %-4s MT/s",
1025 strmhz(buf, sysinfo.freq_ddrbus2));
1026 }
9f3183d2 1027#endif
2f78eae5
YS		 1028 puts("\n");
1029
9f3183d2
MH		 1030 /*
1031 * Display the RCW, so that no one gets confused as to what RCW
d27bf906
BS		 1032 * we're actually using for this boot.
1033 */
1034 puts("Reset Configuration Word (RCW):");
1035 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
9f3183d2 1036 rcw = gur_in32(&gur->rcwsr[i]);
d27bf906 1037 if ((i % 4) == 0)
9f3183d2 1038 printf("\n %08x:", i * 4);
d27bf906
BS		 1039 printf(" %08x", rcw);
1040 }
1041 puts("\n");
1042
2f78eae5
YS		 1043 return 0;
1044}
1045#endif
b940ca64 1046
8b06460e 1047#ifdef CONFIG_FSL_ESDHC
b75d8dc5 1048int cpu_mmc_init(struct bd_info *bis)
8b06460e
YL		 1049{
1050 return fsl_esdhc_mmc_init(bis);
1051}
1052#endif
1053
b75d8dc5 1054int cpu_eth_init(struct bd_info *bis)
b940ca64
GR		 1055{
1056 int error = 0;
1057
1f55a938 1058#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
a2a55e51 1059 error = fsl_mc_ldpaa_init(bis);
b940ca64
GR		 1060#endif
1061 return error;
1062}
40f8dec5 1063
84c2e044 1064int check_psci(void)
40f8dec5 1065{
026f30ec 1066 unsigned int psci_ver;
b4017364 1067
026f30ec
YT		 1068 psci_ver = sec_firmware_support_psci_version();
1069 if (psci_ver == PSCI_INVALID_VER)
1070 return 1;
1071
1072 return 0;
1073}
1074
2db53cfe
PK		 1075static void config_core_prefetch(void)
1076{
1077 char *buf = NULL;
1078 char buffer[HWCONFIG_BUFFER_SIZE];
1079 const char *prefetch_arg = NULL;
cb14cc88 1080 struct arm_smccc_res res;
2db53cfe
PK		 1081 size_t arglen;
1082 unsigned int mask;
2db53cfe
PK		 1083
1084 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1085 buf = buffer;
812ff53c
PB		 1086 else
1087 return;
2db53cfe
PK		 1088
1089 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1090 &arglen, buf);
1091
1092 if (prefetch_arg) {
1093 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1094 if (mask & 0x1) {
1095 printf("Core0 prefetch can't be disabled\n");
1096 return;
1097 }
1098
1099#define SIP_PREFETCH_DISABLE_64 0xC200FF13
cb14cc88
MW		 1100 arm_smccc_smc(SIP_PREFETCH_DISABLE_64, mask, 0, 0, 0, 0, 0, 0,
1101 &res);
2db53cfe 1102
cb14cc88 1103 if (res.a0)
2db53cfe
PK		 1104 printf("Prefetch disable config failed for mask ");
1105 else
1106 printf("Prefetch disable config passed for mask ");
1107 printf("0x%x\n", mask);
1108 }
1109}
1110
3499dd03
AM		 1111#ifdef CONFIG_PCIE_ECAM_GENERIC
1112__weak void set_ecam_icids(void)
1113{
1114}
1115#endif
1116
026f30ec
YT		 1117int arch_early_init_r(void)
1118{
b4017364 1119#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
eea1cb77
PJ		 1120 u32 svr_dev_id;
1121 /*
1122 * erratum A009635 is valid only for LS2080A SoC and
1123 * its personalitiesi
1124 */
a8f33034
W		 1125 svr_dev_id = get_svr();
1126 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
eea1cb77 1127 erratum_a009635();
b4017364 1128#endif
02fb2761
SL		 1129#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1130 erratum_a009942_check_cpo();
1131#endif
026f30ec
YT		 1132 if (check_psci()) {
1133 debug("PSCI: PSCI does not exist.\n");
1134
1135 /* if PSCI does not exist, boot secondary cores here */
1136 if (fsl_layerscape_wake_seconday_cores())
032d5bb4
HZ		 1137 printf("Did not wake secondary cores\n");
1138 }
40f8dec5 1139
2db53cfe
PK		 1140 config_core_prefetch();
1141
31d34c6c
ML		 1142#ifdef CONFIG_SYS_HAS_SERDES
1143 fsl_serdes_init();
e8297341 1144#endif
2e53759d
PB		 1145#ifdef CONFIG_SYS_FSL_HAS_RGMII
1146 /* some dpmacs in armv8a based freescale layerscape SOCs can be
77b11f76 1147 * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
2e53759d
PB		 1148 * EC*_PMUX(rgmii) bits in RCW.
1149 * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1150 * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
c760095a
RIC		 1151 * Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes
1152 * precedence over SerDes protocol. i.e. in LX2160A if we select serdes
1153 * protocol that configures dpmac17 as SGMII and set the EC1_PMUX as
1154 * RGMII, then the dpmac is RGMII and not SGMII.
2e53759d 1155 *
c760095a
RIC		 1156 * Therefore, even thought fsl_rgmii_init is after fsl_serdes_init
1157 * function of SOC, the dpmac will be enabled as RGMII even if it was
1158 * also enabled before as SGMII. If ECx_PMUX is not configured for
1159 * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
2e53759d
PB		 1160 */
1161 fsl_rgmii_init();
1162#endif
e8297341 1163#ifdef CONFIG_FMAN_ENET
6eb32a03 1164#ifndef CONFIG_DM_ETH
e8297341 1165 fman_enet_init();
44262327 1166#endif
6eb32a03 1167#endif
44262327
AM		 1168#ifdef CONFIG_SYS_DPAA_QBMAN
1169 setup_qbman_portals();
3499dd03
AM		 1170#endif
1171#ifdef CONFIG_PCIE_ECAM_GENERIC
1172 set_ecam_icids();
31d34c6c 1173#endif
40f8dec5
YS		 1174 return 0;
1175}
207774b2
YS		 1176
1177int timer_init(void)
1178{
6cc04547 1179 u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
9f3183d2 1180#ifdef CONFIG_FSL_LSCH3
6cc04547 1181 u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR;
9f3183d2 1182#endif
0490cab5
TS		 1183#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1184 defined(CONFIG_ARCH_LS1028A)
a758177f 1185 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
f6b96ff6 1186 u32 svr_dev_id;
a758177f 1187#endif
207774b2
YS		 1188#ifdef COUNTER_FREQUENCY_REAL
1189 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1190
1191 /* Update with accurate clock frequency */
399e2bb6
YS		 1192 if (current_el() == 3)
1193 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
207774b2
YS		 1194#endif
1195
9f3183d2 1196#ifdef CONFIG_FSL_LSCH3
207774b2
YS		 1197 /* Enable timebase for all clusters.
1198 * It is safe to do so even some clusters are not enabled.
1199 */
1200 out_le32(cltbenr, 0xf);
9f3183d2 1201#endif
207774b2 1202
0490cab5
TS		 1203#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1204 defined(CONFIG_ARCH_LS1028A)
a758177f
YC		 1205 /*
1206 * In certain Layerscape SoCs, the clock for each core's
1207 * has an enable bit in the PMU Physical Core Time Base Enable
1208 * Register (PCTBENR), which allows the watchdog to operate.
1209 */
1210 setbits_le32(pctbenr, 0xff);
f6b96ff6
PJ		 1211 /*
1212 * For LS2080A SoC and its personalities, timer controller
1213 * offset is different
1214 */
a8f33034
W		 1215 svr_dev_id = get_svr();
1216 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
f6b96ff6
PJ		 1217 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1218
a758177f
YC		 1219#endif
1220
207774b2
YS		 1221 /* Enable clock for timer
1222 * This is a global setting.
1223 */
1224 out_le32(cntcr, 0x1);
1225
1226 return 0;
1227}
05d2e21b 1228
8fd11135 1229#if !CONFIG_IS_ENABLED(SYSRESET)
6cc04547 1230__efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
78d57842 1231
35b65dd8 1232void __efi_runtime reset_cpu(void)
05d2e21b 1233{
3a187cff 1234#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
d31f3a1b
MA		 1235 /* clear the RST_REQ_MSK and SW_RST_REQ */
1236 out_le32(rstcr, 0x0);
1237
1238 /* initiate the sw reset request */
1239 out_le32(rstcr, 0x1);
4909b89e 1240#else
d31f3a1b
MA		 1241 u32 val;
1242
05d2e21b 1243 /* Raise RESET_REQ_B */
9f3183d2 1244 val = scfg_in32(rstcr);
05d2e21b 1245 val |= 0x02;
9f3183d2 1246 scfg_out32(rstcr, val);
4909b89e 1247#endif
05d2e21b 1248}
8fd11135 1249#endif
c0492141 1250
28f9393b 1251#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
78d57842
AG		 1252
1253void __efi_runtime EFIAPI efi_reset_system(
1254 enum efi_reset_type reset_type,
1255 efi_status_t reset_status,
1256 unsigned long data_size, void *reset_data)
1257{
1258 switch (reset_type) {
1259 case EFI_RESET_COLD:
1260 case EFI_RESET_WARM:
482fc90c 1261 case EFI_RESET_PLATFORM_SPECIFIC:
35b65dd8 1262 reset_cpu();
78d57842
AG		 1263 break;
1264 case EFI_RESET_SHUTDOWN:
1265 /* Nothing we can do */
1266 break;
1267 }
1268
1269 while (1) { }
1270}
1271
22c793e6 1272efi_status_t efi_reset_system_init(void)
78d57842 1273{
22c793e6 1274 return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
78d57842
AG		 1275}
1276
1277#endif
1278
e9303a41
YS		 1279/*
1280 * Calculate reserved memory with given memory bank
1281 * Return aligned memory size on success
1282 * Return (ram_size + needed size) for failure
1283 */
c0492141
YS		 1284phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1285{
1286 phys_size_t ram_top = ram_size;
1287
1f55a938 1288#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
e9303a41
YS		 1289 ram_top = mc_get_dram_block_size();
1290 if (ram_top > ram_size)
1291 return ram_size + ram_top;
1292
1293 ram_top = ram_size - ram_top;
36cc0de0 1294 /* The start address of MC reserved memory needs to be aligned. */
c0492141
YS		 1295 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1296#endif
1297
36cc0de0
YS		 1298 return ram_size - ram_top;
1299}
1300
1301phys_size_t get_effective_memsize(void)
1302{
1303 phys_size_t ea_size, rem = 0;
1304
1305 /*
1306 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
710d0cd7
SG		 1307 * first region is 2GB space at 0x8000_0000. Secure memory needs to
1308 * allocated from first region. If the memory extends to the second
1309 * region (or the third region if applicable), Management Complex (MC)
1310 * memory should be put into the highest region, i.e. the end of DDR
1d457dbb 1311 * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so
710d0cd7
SG		 1312 * U-Boot doesn't relocate itself into higher address. Should DDR be
1313 * configured to skip the first region, this function needs to be
1314 * adjusted.
36cc0de0 1315 */
1d457dbb
TR		 1316 if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
1317 ea_size = CFG_MAX_MEM_MAPPED;
36cc0de0
YS		 1318 rem = gd->ram_size - ea_size;
1319 } else {
1320 ea_size = gd->ram_size;
1321 }
1322
65cc0e2a 1323#ifdef CFG_SYS_MEM_RESERVE_SECURE
36cc0de0 1324 /* Check if we have enough space for secure memory */
65cc0e2a
TR		 1325 if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
1326 ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
710d0cd7
SG		 1327 else
1328 printf("Error: No enough space for secure memory.\n");
36cc0de0
YS		 1329#endif
1330 /* Check if we have enough memory for MC */
1331 if (rem < board_reserve_ram_top(rem)) {
1332 /* Not enough memory in high region to reserve */
e9303a41
YS		 1333 if (ea_size > board_reserve_ram_top(ea_size))
1334 ea_size -= board_reserve_ram_top(ea_size);
36cc0de0
YS		 1335 else
1336 printf("Error: No enough space for reserved memory.\n");
1337 }
1338
1339 return ea_size;
1340}
1341
681d489e
RB		 1342#ifdef CONFIG_TFABOOT
1343phys_size_t tfa_get_dram_size(void)
1344{
cb14cc88 1345 struct arm_smccc_res res;
681d489e 1346
cb14cc88
MW		 1347 arm_smccc_smc(SMC_DRAM_BANK_INFO, -1, 0, 0, 0, 0, 0, 0, &res);
1348 if (res.a0)
681d489e
RB		 1349 return 0;
1350
cb14cc88 1351 return res.a1;
681d489e
RB		 1352}
1353
1354static int tfa_dram_init_banksize(void)
1355{
1356 int i = 0, ret = 0;
681d489e 1357 phys_size_t dram_size = tfa_get_dram_size();
cb14cc88 1358 struct arm_smccc_res res;
681d489e
RB		 1359
1360 debug("dram_size %llx\n", dram_size);
1361
1362 if (!dram_size)
1363 return -EINVAL;
1364
1365 do {
cb14cc88
MW		 1366 arm_smccc_smc(SMC_DRAM_BANK_INFO, i, 0, 0, 0, 0, 0, 0, &res);
1367 if (res.a0) {
681d489e
RB		 1368 ret = -EINVAL;
1369 break;
1370 }
1371
cb14cc88
MW		 1372 debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2);
1373 gd->bd->bi_dram[i].start = res.a1;
1374 gd->bd->bi_dram[i].size = res.a2;
681d489e
RB		 1375
1376 dram_size -= gd->bd->bi_dram[i].size;
1377
1378 i++;
1379 } while (dram_size);
1380
1381 if (i > 0)
1382 ret = 0;
1383
6ebd4883 1384#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
681d489e
RB		 1385 /* Assign memory for MC */
1386#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1387 if (gd->bd->bi_dram[2].size >=
1388 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1389 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1390 gd->bd->bi_dram[2].size -
1391 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1392 } else
1393#endif
1394 {
1395 if (gd->bd->bi_dram[1].size >=
1396 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1397 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1398 gd->bd->bi_dram[1].size -
1399 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1400 } else if (gd->bd->bi_dram[0].size >
1401 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1402 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1403 gd->bd->bi_dram[0].size -
1404 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1405 }
1406 }
6ebd4883 1407#endif /* CONFIG_RESV_RAM */
681d489e
RB		 1408
1409 return ret;
1410}
1411#endif
1412
76b00aca 1413int dram_init_banksize(void)
36cc0de0
YS		 1414{
1415#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1416 phys_size_t dp_ddr_size;
1417#endif
1418
681d489e
RB		 1419#ifdef CONFIG_TFABOOT
1420 if (!tfa_dram_init_banksize())
1421 return 0;
1422#endif
36cc0de0
YS		 1423 /*
1424 * gd->ram_size has the total size of DDR memory, less reserved secure
1425 * memory. The DDR extends from low region to high region(s) presuming
1426 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1427 * the location of secure memory. gd->arch.resv_ram tracks the location
7eb40f0f
YS		 1428 * of reserved memory for Management Complex (MC). Because gd->ram_size
1429 * is reduced by this function if secure memory is reserved, checking
1430 * gd->arch.secure_ram should be done to avoid running it repeatedly.
36cc0de0 1431 */
7eb40f0f 1432
65cc0e2a 1433#ifdef CFG_SYS_MEM_RESERVE_SECURE
7eb40f0f
YS		 1434 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1435 debug("No need to run again, skip %s\n", __func__);
1436
1437 return 0;
1438 }
1439#endif
1440
aa6e94de 1441 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
65cc0e2a
TR		 1442 if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
1443 gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
1444 gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
36cc0de0 1445 gd->bd->bi_dram[1].size = gd->ram_size -
65cc0e2a 1446 CFG_SYS_DDR_BLOCK1_SIZE;
36cc0de0
YS		 1447#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1448 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1449 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1450 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1451 CONFIG_SYS_DDR_BLOCK2_SIZE;
1452 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1453 }
1454#endif
1455 } else {
1456 gd->bd->bi_dram[0].size = gd->ram_size;
1457 }
65cc0e2a 1458#ifdef CFG_SYS_MEM_RESERVE_SECURE
710d0cd7 1459 if (gd->bd->bi_dram[0].size >
65cc0e2a 1460 CFG_SYS_MEM_RESERVE_SECURE) {
710d0cd7 1461 gd->bd->bi_dram[0].size -=
65cc0e2a 1462 CFG_SYS_MEM_RESERVE_SECURE;
710d0cd7
SG		 1463 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1464 gd->bd->bi_dram[0].size;
36cc0de0 1465 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
65cc0e2a 1466 gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
36cc0de0 1467 }
65cc0e2a 1468#endif /* CFG_SYS_MEM_RESERVE_SECURE */
36cc0de0 1469
6ebd4883 1470#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
36cc0de0
YS		 1471 /* Assign memory for MC */
1472#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1473 if (gd->bd->bi_dram[2].size >=
1474 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1475 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1476 gd->bd->bi_dram[2].size -
1477 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1478 } else
1479#endif
1480 {
1481 if (gd->bd->bi_dram[1].size >=
1482 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1483 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1484 gd->bd->bi_dram[1].size -
1485 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1486 } else if (gd->bd->bi_dram[0].size >
1487 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1488 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1489 gd->bd->bi_dram[0].size -
1490 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1491 }
1492 }
6ebd4883 1493#endif /* CONFIG_RESV_RAM */
36cc0de0
YS		 1494
1495#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1496#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1497#error "This SoC shouldn't have DP DDR"
1498#endif
1499 if (soc_has_dp_ddr()) {
1500 /* initialize DP-DDR here */
1501 puts("DP-DDR: ");
1502 /*
1503 * DDR controller use 0 as the base address for binding.
1504 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1505 */
1506 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1507 CONFIG_DP_DDR_CTRL,
1508 CONFIG_DP_DDR_NUM_CTRLS,
1509 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1510 NULL, NULL, NULL);
1511 if (dp_ddr_size) {
1512 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1513 gd->bd->bi_dram[2].size = dp_ddr_size;
1514 } else {
1515 puts("Not detected");
1516 }
1517 }
1518#endif
76b00aca 1519
65cc0e2a 1520#ifdef CFG_SYS_MEM_RESERVE_SECURE
7eb40f0f
YS		 1521 debug("%s is called. gd->ram_size is reduced to %lu\n",
1522 __func__, (ulong)gd->ram_size);
1523#endif
1524
76b00aca 1525 return 0;
36cc0de0
YS		 1526}
1527
9b5e6396 1528#if CONFIG_IS_ENABLED(EFI_LOADER)
36cc0de0
YS		 1529void efi_add_known_memory(void)
1530{
1531 int i;
714497e3 1532 phys_addr_t ram_start;
36cc0de0 1533 phys_size_t ram_size;
36cc0de0
YS		 1534
1535 /* Add RAM */
1536 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1537#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1538#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1539#error "This SoC shouldn't have DP DDR"
1540#endif
1541 if (i == 2)
1542 continue; /* skip DP-DDR */
1543#endif
1544 ram_start = gd->bd->bi_dram[i].start;
1545 ram_size = gd->bd->bi_dram[i].size;
1546#ifdef CONFIG_RESV_RAM
1547 if (gd->arch.resv_ram >= ram_start &&
1548 gd->arch.resv_ram < ram_start + ram_size)
1549 ram_size = gd->arch.resv_ram - ram_start;
1550#endif
714497e3
MW		 1551 efi_add_memory_map(ram_start, ram_size,
1552 EFI_CONVENTIONAL_MEMORY);
36cc0de0 1553 }
c0492141 1554}
36cc0de0 1555#endif
4961eafc
YS		 1556
1557/*
1558 * Before DDR size is known, early MMU table have DDR mapped as device memory
1559 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1560 * needs to be set for these mappings.
1561 * If a special case configures DDR with holes in the mapping, the holes need
1562 * to be marked as invalid. This is not implemented in this function.
1563 */
1564void update_early_mmu_table(void)
1565{
1566 if (!gd->arch.tlb_addr)
1567 return;
1568
6e7df1d1 1569 if (gd->ram_size <= CFG_SYS_FSL_DRAM_SIZE1) {
4961eafc 1570 mmu_change_region_attr(
aa6e94de 1571 CFG_SYS_SDRAM_BASE,
4961eafc
YS		 1572 gd->ram_size,
1573 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1574 PTE_BLOCK_OUTER_SHARE |
1575 PTE_BLOCK_NS |
1576 PTE_TYPE_VALID);
1577 } else {
1578 mmu_change_region_attr(
aa6e94de 1579 CFG_SYS_SDRAM_BASE,
65cc0e2a 1580 CFG_SYS_DDR_BLOCK1_SIZE,
4961eafc
YS		 1581 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1582 PTE_BLOCK_OUTER_SHARE |
1583 PTE_BLOCK_NS |
1584 PTE_TYPE_VALID);
1585#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1586#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1587#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1588#endif
65cc0e2a 1589 if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
4961eafc
YS		 1590 CONFIG_SYS_DDR_BLOCK2_SIZE) {
1591 mmu_change_region_attr(
65cc0e2a 1592 CFG_SYS_DDR_BLOCK2_BASE,
4961eafc
YS		 1593 CONFIG_SYS_DDR_BLOCK2_SIZE,
1594 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1595 PTE_BLOCK_OUTER_SHARE |
1596 PTE_BLOCK_NS |
1597 PTE_TYPE_VALID);
1598 mmu_change_region_attr(
1599 CONFIG_SYS_DDR_BLOCK3_BASE,
1600 gd->ram_size -
65cc0e2a 1601 CFG_SYS_DDR_BLOCK1_SIZE -
4961eafc
YS		 1602 CONFIG_SYS_DDR_BLOCK2_SIZE,
1603 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1604 PTE_BLOCK_OUTER_SHARE |
1605 PTE_BLOCK_NS |
1606 PTE_TYPE_VALID);
1607 } else
1608#endif
1609 {
1610 mmu_change_region_attr(
65cc0e2a 1611 CFG_SYS_DDR_BLOCK2_BASE,
4961eafc 1612 gd->ram_size -
65cc0e2a 1613 CFG_SYS_DDR_BLOCK1_SIZE,
4961eafc
YS		 1614 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1615 PTE_BLOCK_OUTER_SHARE |
1616 PTE_BLOCK_NS |
1617 PTE_TYPE_VALID);
1618 }
1619 }
1620}
1621
1622__weak int dram_init(void)
1623{
f9147d63 1624#ifdef CONFIG_SYS_FSL_DDR
3eace37e 1625 fsl_initdram();
535d76a1
RB		 1626#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1627 defined(CONFIG_SPL_BUILD)
4961eafc
YS		 1628 /* This will break-before-make MMU for DDR */
1629 update_early_mmu_table();
f9147d63 1630#endif
4961eafc
YS		 1631#endif
1632
1633 return 0;
1634}
0d9d557d
AM		 1635
1636#ifdef CONFIG_ARCH_MISC_INIT
1637__weak int serdes_misc_init(void)
1638{
1639 return 0;
1640}
1641
1642int arch_misc_init(void)
1643{
8976556a
GJ		 1644 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
1645 struct udevice *dev;
1646 int ret;
1647
1648 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
1649 if (ret)
cda8f873 1650 printf("Failed to initialize caam_jr: %d\n", ret);
8976556a 1651 }
0d9d557d
AM		 1652 serdes_misc_init();
1653
1654 return 0;
1655}
1656#endif
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