[thirdparty/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / fsl_lsch3_speed.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2014-2015, Freescale Semiconductor, Inc.
 * Copyright 2019-2020 NXP
 *
 * Derived from arch/power/cpu/mpc85xx/speed.c
 */

#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <asm/global_data.h>
#include <linux/compiler.h>
#include <fsl_ifc.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include "cpu.h"

DECLARE_GLOBAL_DATA_PTR;

void get_sys_info(struct sys_info *sys_info)
{
	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
	struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
		(void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR),
		(void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR)
	};
	struct ccsr_clk_ctrl __iomem *clk_ctrl =
		(void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR);
	unsigned int cpu;
	const u8 core_cplx_pll[16] = {
		[0] = 0,	/* CC1 PPL / 1 */
		[1] = 0,	/* CC1 PPL / 2 */
		[2] = 0,	/* CC1 PPL / 4 */
		[4] = 1,	/* CC2 PPL / 1 */
		[5] = 1,	/* CC2 PPL / 2 */
		[6] = 1,	/* CC2 PPL / 4 */
		[8] = 2,	/* CC3 PPL / 1 */
		[9] = 2,	/* CC3 PPL / 2 */
		[10] = 2,	/* CC3 PPL / 4 */
		[12] = 3,	/* CC4 PPL / 1 */
		[13] = 3,	/* CC4 PPL / 2 */
		[14] = 3,	/* CC4 PPL / 4 */
	};

	const u8 core_cplx_pll_div[16] = {
		[0] = 1,	/* CC1 PPL / 1 */
		[1] = 2,	/* CC1 PPL / 2 */
		[2] = 4,	/* CC1 PPL / 4 */
		[4] = 1,	/* CC2 PPL / 1 */
		[5] = 2,	/* CC2 PPL / 2 */
		[6] = 4,	/* CC2 PPL / 4 */
		[8] = 1,	/* CC3 PPL / 1 */
		[9] = 2,	/* CC3 PPL / 2 */
		[10] = 4,	/* CC3 PPL / 4 */
		[12] = 1,	/* CC4 PPL / 1 */
		[13] = 2,	/* CC4 PPL / 2 */
		[14] = 4,	/* CC4 PPL / 4 */
	};

	uint i, cluster;
#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
	uint rcw_tmp;
#endif
	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
	unsigned long sysclk = get_board_sys_clk();
	int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
	u32 c_pll_sel, cplx_pll;
	void *offset;

	sys_info->freq_systembus = sysclk;
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
	sys_info->freq_ddrbus = get_board_ddr_clk();
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	sys_info->freq_ddrbus2 = get_board_ddr_clk();
#endif
#else
	sys_info->freq_ddrbus = sysclk;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	sys_info->freq_ddrbus2 = sysclk;
#endif
#endif

	/* The freq_systembus is used to record frequency of platform PLL */
	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (soc_has_dp_ddr()) {
		sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
	} else {
		sys_info->freq_ddrbus2 = 0;
	}
#endif

	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
		/*
		 * fixme: prefer to combine the following into one line, but
		 * cannot pass compiling without warning about in_le32.
		 */
		offset = (void *)((size_t)clk_grp[i/3] +
			 offsetof(struct ccsr_clk_cluster_group,
				  pllngsr[i%3].gsr));
		ratio[i] = (in_le32(offset) >> 1) & 0x3f;
		freq_c_pll[i] = sysclk * ratio[i];
	}

	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		cluster = fsl_qoriq_core_to_cluster(cpu);
		c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
			    & 0xf;
		cplx_pll = core_cplx_pll[c_pll_sel];
		cplx_pll += cc_group[cluster] - 1;
		sys_info->freq_processor[cpu] =
			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
	}

#if defined(CONFIG_FSL_IFC)
	sys_info->freq_localbus = sys_info->freq_systembus /
						CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif

#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
#define HWA_CGA_M2_CLK_SEL      0x00380000
#define HWA_CGA_M2_CLK_SHIFT    19
	rcw_tmp = in_le32(&gur->rcwsr[5]);
	switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
	case 1:
		sys_info->freq_cga_m2 = freq_c_pll[1];
		break;
	case 2:
		sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
		break;
	case 3:
		sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
		break;
	case 4:
		sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
		break;
	case 6:
		sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
		break;
	case 7:
		sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
		break;
	default:
		printf("Error: Unknown peripheral clock select!\n");
		break;
	}
#endif
}

int get_clocks(void)
{
	struct sys_info sys_info;
#ifdef CONFIG_FSL_ESDHC
	u32 clock = 0;
#endif
	get_sys_info(&sys_info);
	gd->cpu_clk = sys_info.freq_processor[0];
	gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
	gd->mem_clk = sys_info.freq_ddrbus;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#endif

#ifdef CONFIG_FSL_ESDHC
#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
	clock = sys_info.freq_cga_m2;
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
	clock = sys_info.freq_systembus;
#endif
	gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
	gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
#endif

	if (gd->cpu_clk != 0)
		return 0;
	else
		return 1;
}

/********************************************
 * get_bus_freq
 * return platform clock in Hz
 *********************************************/
ulong get_bus_freq(ulong dummy)
{
	if (!gd->bus_clk)
		get_clocks();

	return gd->bus_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq(ulong ctrl_num)
{
	if (!gd->mem_clk)
		get_clocks();

	/*
	 * DDR controller 0 & 1 are on memory complex 0
	 * DDR controller 2 is on memory complext 1
	 */
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (ctrl_num >= 2)
		return gd->arch.mem2_clk;
#endif

	return gd->mem_clk;
}

int get_i2c_freq(ulong dummy)
{
	return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
}

int get_dspi_freq(ulong dummy)
{
	return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
}

int get_serial_clock(void)
{
	return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
}

unsigned int mxc_get_clock(enum mxc_clock clk)
{
	switch (clk) {
	case MXC_I2C_CLK:
		return get_i2c_freq(0);
	case MXC_DSPI_CLK:
		return get_dspi_freq(0);
	default:
		printf("Unsupported clock\n");
	}
	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
2f78eae5	2	/*
9f3183d2	3	* Copyright 2014-2015, Freescale Semiconductor, Inc.
3a187cff	4	* Copyright 2019-2020 NXP
2f78eae5	5	*
2f78eae5 YS	6	* Derived from arch/power/cpu/mpc85xx/speed.c
	7	*/
	8
d678a59d	9	#include <common.h>
d96c2604	10	#include <clock_legacy.h>
b5981474	11	#include <cpu_func.h>
401d1c4f	12	#include <asm/global_data.h>
2f78eae5 YS	13	#include <linux/compiler.h>
	14	#include <fsl_ifc.h>
	15	#include <asm/processor.h>
	16	#include <asm/io.h>
44937214	17	#include <asm/arch-fsl-layerscape/immap_lsch3.h>
2f78eae5	18	#include <asm/arch/clock.h>
9f3183d2	19	#include <asm/arch/soc.h>
2f78eae5 YS	20	#include "cpu.h"
	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
2f78eae5 YS	24	void get_sys_info(struct sys_info *sys_info)
2f78eae5 YS	25	{
6cc04547	26	struct ccsr_gur __iomem gur = (void )(CFG_SYS_FSL_GUTS_ADDR);
2f78eae5	27	struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
6cc04547 TR	28	(void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR),
6cc04547 TR	29	(void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR)
2f78eae5 YS	30	};
2f78eae5 YS	31	struct ccsr_clk_ctrl __iomem *clk_ctrl =
6cc04547	32	(void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR);
2f78eae5 YS	33	unsigned int cpu;
	34	const u8 core_cplx_pll[16] = {
	35	[0] = 0, /* CC1 PPL / 1 */
	36	[1] = 0, /* CC1 PPL / 2 */
	37	[2] = 0, /* CC1 PPL / 4 */
	38	[4] = 1, /* CC2 PPL / 1 */
	39	[5] = 1, /* CC2 PPL / 2 */
	40	[6] = 1, /* CC2 PPL / 4 */
	41	[8] = 2, /* CC3 PPL / 1 */
	42	[9] = 2, /* CC3 PPL / 2 */
	43	[10] = 2, /* CC3 PPL / 4 */
	44	[12] = 3, /* CC4 PPL / 1 */
	45	[13] = 3, /* CC4 PPL / 2 */
	46	[14] = 3, /* CC4 PPL / 4 */
	47	};
	48
	49	const u8 core_cplx_pll_div[16] = {
	50	[0] = 1, /* CC1 PPL / 1 */
	51	[1] = 2, /* CC1 PPL / 2 */
	52	[2] = 4, /* CC1 PPL / 4 */
	53	[4] = 1, /* CC2 PPL / 1 */
	54	[5] = 2, /* CC2 PPL / 2 */
	55	[6] = 4, /* CC2 PPL / 4 */
	56	[8] = 1, /* CC3 PPL / 1 */
	57	[9] = 2, /* CC3 PPL / 2 */
	58	[10] = 4, /* CC3 PPL / 4 */
	59	[12] = 1, /* CC4 PPL / 1 */
	60	[13] = 2, /* CC4 PPL / 2 */
	61	[14] = 4, /* CC4 PPL / 4 */
	62	};
	63
	64	uint i, cluster;
065ee175	65	#if defined(CONFIG_ARCH_LS1028A) \|\| defined(CONFIG_ARCH_LS1088A)
24cb6f22 YZ	66	uint rcw_tmp;
24cb6f22 YZ	67	#endif
2f78eae5 YS	68	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
2f78eae5 YS	69	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
2f8a6db5	70	unsigned long sysclk = get_board_sys_clk();
6cc04547	71	int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
2f78eae5 YS	72	u32 c_pll_sel, cplx_pll;
	73	void *offset;
	74
	75	sys_info->freq_systembus = sysclk;
efb5dab7 TR	76	#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) \|\| defined(CONFIG_STATIC_DDR_CLK_FREQ)
efb5dab7 TR	77	sys_info->freq_ddrbus = get_board_ddr_clk();
44937214	78	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
efb5dab7	79	sys_info->freq_ddrbus2 = get_board_ddr_clk();
44937214	80	#endif
2f78eae5 YS	81	#else
2f78eae5 YS	82	sys_info->freq_ddrbus = sysclk;
44937214	83	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
b87e6f88	84	sys_info->freq_ddrbus2 = sysclk;
44937214	85	#endif
2f78eae5 YS	86	#endif
2f78eae5 YS	87
3564208e	88	/* The freq_systembus is used to record frequency of platform PLL */
9f3183d2	89	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
2f78eae5 YS	90	FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
2f78eae5 YS	91	FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
9f3183d2	92	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
2f78eae5 YS	93	FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
2f78eae5 YS	94	FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
44937214	95	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
3c1d218a YS	96	if (soc_has_dp_ddr()) {
3c1d218a YS	97	sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
b87e6f88 YS	98	FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
b87e6f88 YS	99	FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
3c1d218a YS	100	} else {
	101	sys_info->freq_ddrbus2 = 0;
	102	}
44937214	103	#endif
2f78eae5 YS	104
	105	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
	106	/*
	107	* fixme: prefer to combine the following into one line, but
	108	* cannot pass compiling without warning about in_le32.
	109	*/
	110	offset = (void *)((size_t)clk_grp[i/3] +
	111	offsetof(struct ccsr_clk_cluster_group,
	112	pllngsr[i%3].gsr));
	113	ratio[i] = (in_le32(offset) >> 1) & 0x3f;
19f91750	114	freq_c_pll[i] = sysclk * ratio[i];
2f78eae5 YS	115	}
	116
	117	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
	118	cluster = fsl_qoriq_core_to_cluster(cpu);
	119	c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
	120	& 0xf;
	121	cplx_pll = core_cplx_pll[c_pll_sel];
	122	cplx_pll += cc_group[cluster] - 1;
	123	sys_info->freq_processor[cpu] =
	124	freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
	125	}
	126
	127	#if defined(CONFIG_FSL_IFC)
8e63ed51 PK	128	sys_info->freq_localbus = sys_info->freq_systembus /
8e63ed51 PK	129	CONFIG_SYS_FSL_IFC_CLK_DIV;
2f78eae5	130	#endif
2f78eae5	131
065ee175	132	#if defined(CONFIG_ARCH_LS1028A) \|\| defined(CONFIG_ARCH_LS1088A)
24cb6f22 YZ	133	#define HWA_CGA_M2_CLK_SEL 0x00380000
	134	#define HWA_CGA_M2_CLK_SHIFT 19
	135	rcw_tmp = in_le32(&gur->rcwsr[5]);
	136	switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
	137	case 1:
	138	sys_info->freq_cga_m2 = freq_c_pll[1];
	139	break;
	140	case 2:
	141	sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
	142	break;
	143	case 3:
	144	sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
	145	break;
	146	case 4:
	147	sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
	148	break;
	149	case 6:
	150	sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
	151	break;
	152	case 7:
	153	sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
	154	break;
	155	default:
	156	printf("Error: Unknown peripheral clock select!\n");
	157	break;
	158	}
	159	#endif
24cb6f22	160	}
2f78eae5 YS	161
	162	int get_clocks(void)
	163	{
	164	struct sys_info sys_info;
f1bce084 YL	165	#ifdef CONFIG_FSL_ESDHC
	166	u32 clock = 0;
	167	#endif
2f78eae5 YS	168	get_sys_info(&sys_info);
2f78eae5 YS	169	gd->cpu_clk = sys_info.freq_processor[0];
3564208e	170	gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
2f78eae5	171	gd->mem_clk = sys_info.freq_ddrbus;
44937214	172	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
b87e6f88	173	gd->arch.mem2_clk = sys_info.freq_ddrbus2;
44937214	174	#endif
f1bce084 YL	175
	176	#ifdef CONFIG_FSL_ESDHC
	177	#if defined(CONFIG_ARCH_LS1028A) \|\| defined(CONFIG_ARCH_LS1088A)
	178	clock = sys_info.freq_cga_m2;
3a187cff	179	#elif defined(CONFIG_ARCH_LX2160A) \|\| defined(CONFIG_ARCH_LS2080A) \|\| defined(CONFIG_ARCH_LX2162A)
f1bce084	180	clock = sys_info.freq_systembus;
24cb6f22	181	#endif
f1bce084	182	gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
3564208e	183	gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
24cb6f22	184	#endif
2f78eae5 YS	185
	186	if (gd->cpu_clk != 0)
	187	return 0;
	188	else
	189	return 1;
	190	}
	191
	192	/********************************************
	193	* get_bus_freq
3564208e	194	* return platform clock in Hz
2f78eae5 YS	195	*********************************************/
	196	ulong get_bus_freq(ulong dummy)
	197	{
	198	if (!gd->bus_clk)
	199	get_clocks();
	200
	201	return gd->bus_clk;
	202	}
	203
	204	/********************************************
	205	* get_ddr_freq
	206	* return ddr bus freq in Hz
	207	*********************************************/
b87e6f88	208	ulong get_ddr_freq(ulong ctrl_num)
2f78eae5 YS	209	{
	210	if (!gd->mem_clk)
	211	get_clocks();
	212
b87e6f88 YS	213	/*
b87e6f88 YS	214	* DDR controller 0 & 1 are on memory complex 0
1cc0a9f4	215	* DDR controller 2 is on memory complext 1
b87e6f88	216	*/
44937214	217	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
b87e6f88 YS	218	if (ctrl_num >= 2)
b87e6f88 YS	219	return gd->arch.mem2_clk;
44937214	220	#endif
b87e6f88	221
2f78eae5 YS	222	return gd->mem_clk;
	223	}
	224
3564208e HZ	225	int get_i2c_freq(ulong dummy)
	226	{
	227	return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
	228	}
	229
	230	int get_dspi_freq(ulong dummy)
	231	{
	232	return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
	233	}
	234
	235	int get_serial_clock(void)
	236	{
	237	return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
	238	}
	239
2f78eae5 YS	240	unsigned int mxc_get_clock(enum mxc_clock clk)
	241	{
	242	switch (clk) {
	243	case MXC_I2C_CLK:
3564208e	244	return get_i2c_freq(0);
b0e209dc	245	case MXC_DSPI_CLK:
3564208e	246	return get_dspi_freq(0);
2f78eae5 YS	247	default:
	248	printf("Unsupported clock\n");
	249	}
	250	return 0;
	251	}