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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / soc.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
b991b981 2/*
9f3183d2 3 * Copyright 2014-2015 Freescale Semiconductor
390c73b4 4 * Copyright 2019-2021 NXP
b991b981
SW		 5 */
6
d678a59d 7#include <common.h>
d96c2604 8#include <clock_legacy.h>
f40b120e 9#include <cpu_func.h>
9fb625ce 10#include <env.h>
63b2316c 11#include <fsl_immap.h>
b991b981 12#include <fsl_ifc.h>
5255932f 13#include <init.h>
f40b120e 14#include <linux/sizes.h>
f7ae49fc 15#include <log.h>
b392a6d4 16#include <asm/arch/fsl_serdes.h>
9f3183d2 17#include <asm/arch/soc.h>
90526e9f 18#include <asm/cache.h>
d746fef4 19#include <asm/io.h>
b2d5ac59 20#include <asm/global_data.h>
b4017364 21#include <asm/arch-fsl-layerscape/config.h>
9add5a4b 22#include <asm/arch-fsl-layerscape/ns_access.h>
3cb4fe65 23#include <asm/arch-fsl-layerscape/fsl_icid.h>
f40b120e 24#include <asm/gic-v3.h>
b392a6d4 25#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
341238fd 26#include <fsl_csu.h>
b392a6d4 27#endif
b7f2bbff 28#ifdef CONFIG_SYS_FSL_DDR
074596c0
SL		 29#include <fsl_ddr_sdram.h>
30#include <fsl_ddr.h>
b7f2bbff 31#endif
d0412885
AB		 32#ifdef CONFIG_CHAIN_OF_TRUST
33#include <fsl_validate.h>
34#endif
6d9b82d0 35#include <fsl_immap.h>
223c1907 36#include <dm.h>
e1f306c0 37#include <dm/device_compat.h>
223c1907 38#include <linux/err.h>
cbf77d20 39#ifdef CONFIG_GIC_V3_ITS
2141d250
PG		 40DECLARE_GLOBAL_DATA_PTR;
41#endif
b2d5ac59 42
f40b120e 43#ifdef CONFIG_GIC_V3_ITS
60b9b47d
MW		 44#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
45#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
46#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
47 PROPTABLE_MAX_SZ, SZ_1M)
48static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
49{
50 int err;
51 struct fdt_memory gic_rd_tables;
52
53 gic_rd_tables.start = base;
54 gic_rd_tables.end = base + size - 1;
55 err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
56 NULL, 0, NULL, 0);
57 if (err < 0)
58 debug("%s: failed to add reserved memory: %d\n", __func__, err);
59
60 return err;
61}
62
f40b120e
HZ		 63int ls_gic_rd_tables_init(void *blob)
64{
60b9b47d 65 u64 gic_lpi_base;
a84cea06 66 int ret;
f40b120e 67
60b9b47d
MW		 68 gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
69 ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
70 if (ret)
71 return ret;
72
73 ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
f40b120e
HZ		 74 if (ret)
75 debug("%s: failed to init gic-lpi-tables\n", __func__);
76
77 return ret;
78}
79#endif
80
3c1d218a
YS		 81bool soc_has_dp_ddr(void)
82{
6cc04547 83 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
3c1d218a
YS		 84 u32 svr = gur_in32(&gur->svr);
85
9ae836cd
PJ		 86 /* LS2085A, LS2088A, LS2048A has DP_DDR */
87 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
88 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
89 (SVR_SOC_VER(svr) == SVR_LS2048A))
3c1d218a
YS		 90 return true;
91
92 return false;
93}
94
95bool soc_has_aiop(void)
96{
6cc04547 97 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
3c1d218a
YS		 98 u32 svr = gur_in32(&gur->svr);
99
100 /* LS2085A has AIOP */
49cdce16 101 if (SVR_SOC_VER(svr) == SVR_LS2085A)
3c1d218a
YS		 102 return true;
103
104 return false;
105}
106
2ab1553f
RW		 107static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
108{
109 scfg_clrsetbits32(scfg + offset / 4,
110 0xF << 6,
111 SCFG_USB_TXVREFTUNE << 6);
112}
113
114static void erratum_a009008(void)
115{
116#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
117 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
2a8a3539 118
819163c4
RW		 119#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
120 defined(CONFIG_ARCH_LS1012A)
2ab1553f 121 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
819163c4 122#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
2ab1553f
RW		 123 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
124 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
819163c4 125#endif
2ab1553f
RW		 126#elif defined(CONFIG_ARCH_LS2080A)
127 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
128#endif
129#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
130}
131
2a8a3539
RW		 132static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
133{
134 scfg_clrbits32(scfg + offset / 4,
135 SCFG_USB_SQRXTUNE_MASK << 23);
136}
137
138static void erratum_a009798(void)
139{
140#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
141 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
142
819163c4
RW		 143#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
144 defined(CONFIG_ARCH_LS1012A)
2a8a3539 145 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
819163c4 146#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
2a8a3539
RW		 147 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
148 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
819163c4 149#endif
2a8a3539
RW		 150#elif defined(CONFIG_ARCH_LS2080A)
151 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
152#endif
153#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
154}
155
819163c4
RW		 156#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
157 defined(CONFIG_ARCH_LS1012A)
9d1cd910
RW		 158static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
159{
160 scfg_clrsetbits32(scfg + offset / 4,
161 0x7F << 9,
162 SCFG_USB_PCSTXSWINGFULL << 9);
163}
164#endif
165
166static void erratum_a008997(void)
167{
168#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
819163c4
RW		 169#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
170 defined(CONFIG_ARCH_LS1012A)
9d1cd910
RW		 171 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
172
173 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
819163c4 174#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
9d1cd910
RW		 175 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
176 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
177#endif
3458a419
RW		 178#elif defined(CONFIG_ARCH_LS1028A)
179 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
180 0x7F << 11,
181 DCSR_USB_PCSTXSWINGFULL << 11);
819163c4 182#endif
9d1cd910
RW		 183#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
184}
185
819163c4
RW		 186#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
187 defined(CONFIG_ARCH_LS1012A)
15d59b53
RW		 188
189#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
190 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
191 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
192 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
193 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
194
123fbbbe 195#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
3a187cff
MA		 196 defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
197 defined(CONFIG_ARCH_LX2162A)
15d59b53
RW		 198
199#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
200 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
201 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
202 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
203 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
204
205#endif
206
207static void erratum_a009007(void)
208{
9c18c695
SA		 209 if (!IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A009007))
210 return;
211
819163c4
RW		 212#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
213 defined(CONFIG_ARCH_LS1012A)
15d59b53
RW		 214 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
215
216 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
819163c4 217#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
15d59b53
RW		 218 usb_phy = (void __iomem *)SCFG_USB_PHY2;
219 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
220
221 usb_phy = (void __iomem *)SCFG_USB_PHY3;
222 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
819163c4 223#endif
123fbbbe
YZ		 224#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
225 defined(CONFIG_ARCH_LS1028A)
15d59b53
RW		 226 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
227
228 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
229 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
230#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
231}
232
40836e21 233#if defined(CONFIG_FSL_LSCH3)
390c73b4 234static void erratum_a050204(void)
0cfa00cd 235{
3a187cff 236#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
0cfa00cd
RW		 237 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
238
239 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
240 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
241#endif
242}
000f4e76
YY		 243/*
244 * This erratum requires setting a value to eddrtqcr1 to
245 * optimal the DDR performance.
246 */
247static void erratum_a008336(void)
248{
40836e21 249#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
000f4e76
YY		 250 u32 *eddrtqcr1;
251
6cc04547
TR		 252#ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
253 eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
1a87c24f
SL		 254 if (fsl_ddr_get_version(0) == 0x50200)
255 out_le32(eddrtqcr1, 0x63b30002);
000f4e76 256#endif
6cc04547
TR		 257#ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
258 eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
1a87c24f
SL		 259 if (fsl_ddr_get_version(0) == 0x50200)
260 out_le32(eddrtqcr1, 0x63b30002);
000f4e76
YY		 261#endif
262#endif
263}
264
265/*
266 * This erratum requires a register write before being Memory
267 * controller 3 being enabled.
268 */
269static void erratum_a008514(void)
270{
40836e21 271#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
000f4e76
YY		 272 u32 *eddrtqcr1;
273
6cc04547
TR		 274#ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
275 eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
000f4e76
YY		 276 out_le32(eddrtqcr1, 0x63b20002);
277#endif
278#endif
279}
b4017364
PK		 280#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
281#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
282
283static unsigned long get_internval_val_mhz(void)
284{
00caae6d 285 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
b4017364
PK		 286 /*
287 * interval is the number of platform cycles(MHz) between
288 * wake up events generated by EPU.
289 */
290 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
291
292 if (interval)
0b1284eb 293 interval_mhz = dectoul(interval, NULL);
b4017364
PK		 294
295 return interval_mhz;
296}
297
298void erratum_a009635(void)
299{
300 u32 val;
301 unsigned long interval_mhz = get_internval_val_mhz();
302
303 if (!interval_mhz)
304 return;
305
306 val = in_le32(DCSR_CGACRE5);
307 writel(val | 0x00000200, DCSR_CGACRE5);
308
309 val = in_le32(EPU_EPCMPR5);
310 writel(interval_mhz, EPU_EPCMPR5);
311 val = in_le32(EPU_EPCCR5);
312 writel(val | 0x82820000, EPU_EPCCR5);
313 val = in_le32(EPU_EPSMCR5);
314 writel(val | 0x002f0000, EPU_EPSMCR5);
315 val = in_le32(EPU_EPECR5);
316 writel(val | 0x20000000, EPU_EPECR5);
317 val = in_le32(EPU_EPGCR);
318 writel(val | 0x80000000, EPU_EPGCR);
319}
320#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
321
b2d5ac59
SW		 322static void erratum_rcw_src(void)
323{
faed6bde 324#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
b2d5ac59
SW		 325 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
326 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
327 u32 val;
328
329 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
330 val &= ~DCFG_PORSR1_RCW_SRC;
331 val |= DCFG_PORSR1_RCW_SRC_NOR;
332 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
333#endif
334}
335
ab10d73d
YS		 336#define I2C_DEBUG_REG 0x6
337#define I2C_GLITCH_EN 0x8
338/*
339 * This erratum requires setting glitch_en bit to enable
340 * digital glitch filter to improve clock stability.
341 */
dd48f0bf 342#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
ab10d73d
YS		 343static void erratum_a009203(void)
344{
55dabcc8 345#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
0d7f1ae0 346 u8 __iomem *ptr;
ab10d73d
YS		 347#ifdef I2C1_BASE_ADDR
348 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
349
350 writeb(I2C_GLITCH_EN, ptr);
351#endif
352#ifdef I2C2_BASE_ADDR
353 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
354
355 writeb(I2C_GLITCH_EN, ptr);
356#endif
357#ifdef I2C3_BASE_ADDR
358 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
359
360 writeb(I2C_GLITCH_EN, ptr);
361#endif
362#ifdef I2C4_BASE_ADDR
363 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
364
365 writeb(I2C_GLITCH_EN, ptr);
366#endif
367#endif
368}
dd48f0bf 369#endif
40836e21 370
4a97a0c9
SJ		 371void bypass_smmu(void)
372{
373 u32 val;
374 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
375 out_le32(SMMU_SCR0, val);
376 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
377 out_le32(SMMU_NSCR0, val);
378}
b991b981
SW		 379void fsl_lsch3_early_init_f(void)
380{
b2d5ac59 381 erratum_rcw_src();
e45ff0ce 382#ifdef CONFIG_FSL_IFC
b991b981 383 init_early_memctl_regs(); /* tighten IFC timing */
e45ff0ce 384#endif
dd48f0bf 385#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
ab10d73d 386 erratum_a009203();
dd48f0bf 387#endif
000f4e76
YY		 388 erratum_a008514();
389 erratum_a008336();
2ab1553f 390 erratum_a009008();
2a8a3539 391 erratum_a009798();
9d1cd910 392 erratum_a008997();
15d59b53 393 erratum_a009007();
390c73b4 394 erratum_a050204();
4a97a0c9
SJ		 395#ifdef CONFIG_CHAIN_OF_TRUST
396 /* In case of Secure Boot, the IBR configures the SMMU
397 * to allow only Secure transactions.
398 * SMMU must be reset in bypass mode.
399 * Set the ClientPD bit and Clear the USFCFG Bit
400 */
401 if (fsl_check_boot_mode_secure() == 1)
402 bypass_smmu();
403#endif
5c6dc6c9 404
e33938ac 405#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
3a187cff
MA		 406 defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
407 defined(CONFIG_ARCH_LX2162A)
5c6dc6c9
LT		 408 set_icids();
409#endif
b991b981 410}
8281c58f 411
a1f95ff7
RB		 412/* Get VDD in the unit mV from voltage ID */
413int get_core_volt_from_fuse(void)
414{
6cc04547 415 struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
a1f95ff7
RB		 416 int vdd;
417 u32 fusesr;
418 u8 vid;
419
420 /* get the voltage ID from fuse status register */
421 fusesr = in_le32(&gur->dcfg_fusesr);
422 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
423 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
424 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
425 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
426 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
427 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
428 }
429 debug("%s: VID = 0x%x\n", __func__, vid);
430 switch (vid) {
431 case 0x00: /* VID isn't supported */
432 vdd = -EINVAL;
433 debug("%s: The VID feature is not supported\n", __func__);
434 break;
435 case 0x08: /* 0.9V silicon */
436 vdd = 900;
437 break;
438 case 0x10: /* 1.0V silicon */
439 vdd = 1000;
440 break;
441 default: /* Other core voltage */
442 vdd = -EINVAL;
443 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
444 break;
445 }
446 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
447
448 return vdd;
449}
450
22a44d08 451#elif defined(CONFIG_FSL_LSCH2)
bbc8e053
MH		 452/*
453 * This erratum requires setting a value to eddrtqcr1 to optimal
454 * the DDR performance. The eddrtqcr1 register is in SCFG space
455 * of LS1043A and the offset is 0x157_020c.
456 */
457#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
458 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
459#error A009660 and A008514 can not be both enabled.
460#endif
461
462static void erratum_a009660(void)
463{
464#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
6cc04547 465 u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
bbc8e053
MH		 466 out_be32(eddrtqcr1, 0x63b20042);
467#endif
468}
469
074596c0
SL		 470static void erratum_a008850_early(void)
471{
472#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
473 /* part 1 of 2 */
63b2316c
AK		 474 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
475 CONFIG_SYS_CCI400_OFFSET);
6cc04547 476 struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
074596c0 477
399e2bb6
YS		 478 /* Skip if running at lower exception level */
479 if (current_el() < 3)
480 return;
481
074596c0
SL		 482 /* disables propagation of barrier transactions to DDRC from CCI400 */
483 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
484
485 /* disable the re-ordering in DDRC */
486 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
487#endif
488}
489
490void erratum_a008850_post(void)
491{
492#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
493 /* part 2 of 2 */
63b2316c
AK		 494 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
495 CONFIG_SYS_CCI400_OFFSET);
6cc04547 496 struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
074596c0
SL		 497 u32 tmp;
498
399e2bb6
YS		 499 /* Skip if running at lower exception level */
500 if (current_el() < 3)
501 return;
502
074596c0
SL		 503 /* enable propagation of barrier transactions to DDRC from CCI400 */
504 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
505
506 /* enable the re-ordering in DDRC */
507 tmp = ddr_in32(&ddr->eor);
508 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
509 ddr_out32(&ddr->eor, tmp);
510#endif
511}
512
b392a6d4
HZ		 513#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
514void erratum_a010315(void)
515{
516 int i;
517
518 for (i = PCIE1; i <= PCIE4; i++)
519 if (!is_serdes_configured(i)) {
520 debug("PCIe%d: disabled all R/W permission!\n", i);
521 set_pcie_ns_access(i, 0);
522 }
523}
524#endif
525
0ea3671d
HZ		 526static void erratum_a010539(void)
527{
528#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
6cc04547 529 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
0ea3671d
HZ		 530 u32 porsr1;
531
532 porsr1 = in_be32(&gur->porsr1);
533 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
65cc0e2a 534 out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
0ea3671d 535 porsr1);
6cc04547 536 out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
0ea3671d
HZ		 537#endif
538}
539
031acdba
HZ		 540/* Get VDD in the unit mV from voltage ID */
541int get_core_volt_from_fuse(void)
542{
6cc04547 543 struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
031acdba
HZ		 544 int vdd;
545 u32 fusesr;
546 u8 vid;
547
548 fusesr = in_be32(&gur->dcfg_fusesr);
549 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
550 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
551 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
552 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
553 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
554 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
555 }
556 debug("%s: VID = 0x%x\n", __func__, vid);
557 switch (vid) {
558 case 0x00: /* VID isn't supported */
559 vdd = -EINVAL;
560 debug("%s: The VID feature is not supported\n", __func__);
561 break;
562 case 0x08: /* 0.9V silicon */
563 vdd = 900;
564 break;
565 case 0x10: /* 1.0V silicon */
566 vdd = 1000;
567 break;
568 default: /* Other core voltage */
569 vdd = -EINVAL;
570 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
571 break;
572 }
573 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
574
575 return vdd;
576}
577
031acdba
HZ		 578static int setup_core_volt(u32 vdd)
579{
580 return board_setup_core_volt(vdd);
581}
582
583#ifdef CONFIG_SYS_FSL_DDR
584static void ddr_enable_0v9_volt(bool en)
585{
6cc04547 586 struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
031acdba
HZ		 587 u32 tmp;
588
589 tmp = ddr_in32(&ddr->ddr_cdr1);
590
591 if (en)
592 tmp |= DDR_CDR1_V0PT9_EN;
593 else
594 tmp &= ~DDR_CDR1_V0PT9_EN;
595
596 ddr_out32(&ddr->ddr_cdr1, tmp);
597}
598#endif
599
600int setup_chip_volt(void)
601{
602 int vdd;
603
604 vdd = get_core_volt_from_fuse();
605 /* Nothing to do for silicons doesn't support VID */
606 if (vdd < 0)
607 return vdd;
608
609 if (setup_core_volt(vdd))
610 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
611#ifdef CONFIG_SYS_HAS_SERDES
612 if (setup_serdes_volt(vdd))
613 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
614#endif
615
616#ifdef CONFIG_SYS_FSL_DDR
617 if (vdd == 900)
618 ddr_enable_0v9_volt(true);
619#endif
620
621 return 0;
622}
623
c4dc68b0
CJ		 624#ifdef CONFIG_FSL_PFE
625void init_pfe_scfg_dcfg_regs(void)
626{
6cc04547 627 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
c4dc68b0
CJ		 628 u32 ecccr2;
629
630 out_be32(&scfg->pfeasbcr,
631 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
632 out_be32(&scfg->pfebsbcr,
633 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
634
635 /* CCI-400 QoS settings for PFE */
636 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
637 | SCFG_WR_QOS1_PFE2_QOS));
638 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
639 | SCFG_RD_QOS1_PFE2_QOS));
640
65cc0e2a
TR		 641 ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
642 out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
c4dc68b0
CJ		 643 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
644}
645#endif
646
8281c58f
MH		 647void fsl_lsch2_early_init_f(void)
648{
63b2316c
AK		 649 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
650 CONFIG_SYS_CCI400_OFFSET);
6cc04547 651 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
293d75c0
PG		 652#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
653 enum boot_src src;
654#endif
8281c58f 655
341238fd
HZ		 656#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
657 enable_layerscape_ns_access();
658#endif
659
8281c58f
MH		 660#ifdef CONFIG_FSL_IFC
661 init_early_memctl_regs(); /* tighten IFC timing */
662#endif
663
293d75c0
PG		 664#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
665 src = get_boot_src();
666 if (src != BOOT_SOURCE_QSPI_NOR)
667 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
668#else
258b8c93 669#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
166ef1e9 670 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
293d75c0 671#endif
166ef1e9 672#endif
70f959c3 673 /* Make SEC reads and writes snoopable */
3d23b6c5
RW		 674#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
675 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
676 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
677 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
678 SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
679 SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
0c3eec2a 680 SCFG_SNPCNFGCR_SATAWRSNP | SCFG_SNPCNFGCR_EDMASNP);
d085c9ad
RW		 681#elif defined(CONFIG_ARCH_LS1012A)
682 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
683 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
684 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
685 SCFG_SNPCNFGCR_SATAWRSNP);
3d23b6c5 686#else
70f959c3 687 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
4de6ce15
TY		 688 SCFG_SNPCNFGCR_SECWRSNP |
689 SCFG_SNPCNFGCR_SATARDSNP |
690 SCFG_SNPCNFGCR_SATAWRSNP);
3d23b6c5 691#endif
70f959c3 692
8281c58f
MH		 693 /*
694 * Enable snoop requests and DVM message requests for
695 * Slave insterface S4 (A53 core cluster)
696 */
399e2bb6
YS		 697 if (current_el() == 3) {
698 out_le32(&cci->slave[4].snoop_ctrl,
699 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
700 }
0d6faf2b 701
9add5a4b
RW		 702 /*
703 * Program Central Security Unit (CSU) to grant access
704 * permission for USB 2.0 controller
705 */
706#if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
707 if (current_el() == 3)
708 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
709#endif
0d6faf2b 710 /* Erratum */
074596c0 711 erratum_a008850_early(); /* part 1 of 2 */
bbc8e053 712 erratum_a009660();
0ea3671d 713 erratum_a010539();
2ab1553f 714 erratum_a009008();
2a8a3539 715 erratum_a009798();
9d1cd910 716 erratum_a008997();
15d59b53 717 erratum_a009007();
3cb4fe65 718
dc29a4c1 719#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
3cb4fe65
LT		 720 set_icids();
721#endif
8281c58f 722}
9f3183d2 723#endif
b2d5ac59 724
ce3bead6
KS		 725#ifdef CONFIG_FSPI_AHB_EN_4BYTE
726int fspi_ahb_init(void)
727{
728 /* Enable 4bytes address support and fast read */
729 u32 *fspi_lut, lut_key, *fspi_key;
730
731 fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
732 fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
733
734 lut_key = in_be32(fspi_key);
735
736 if (lut_key == SYS_NXP_FSPI_LUTKEY) {
737 /* That means the register is BE */
738 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
739 /* Unlock the lut table */
740 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
741 /* Create READ LUT */
742 out_be32(fspi_lut, 0x0820040c);
743 out_be32(fspi_lut + 1, 0x24003008);
744 out_be32(fspi_lut + 2, 0x00000000);
745 /* Lock the lut table */
746 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
747 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
748 } else {
749 /* That means the register is LE */
750 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
751 /* Unlock the lut table */
752 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
753 /* Create READ LUT */
754 out_le32(fspi_lut, 0x0820040c);
755 out_le32(fspi_lut + 1, 0x24003008);
756 out_le32(fspi_lut + 2, 0x00000000);
757 /* Lock the lut table */
758 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
759 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
760 }
761
762 return 0;
763}
764#endif
765
dd2ad2f1
YY		 766#ifdef CONFIG_QSPI_AHB_INIT
767/* Enable 4bytes address support and fast read */
768int qspi_ahb_init(void)
769{
770 u32 *qspi_lut, lut_key, *qspi_key;
771
772 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
773 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
774
775 lut_key = in_be32(qspi_key);
776
777 if (lut_key == 0x5af05af0) {
778 /* That means the register is BE */
779 out_be32(qspi_key, 0x5af05af0);
780 /* Unlock the lut table */
781 out_be32(qspi_key + 1, 0x00000002);
782 out_be32(qspi_lut, 0x0820040c);
783 out_be32(qspi_lut + 1, 0x1c080c08);
784 out_be32(qspi_lut + 2, 0x00002400);
785 /* Lock the lut table */
786 out_be32(qspi_key, 0x5af05af0);
787 out_be32(qspi_key + 1, 0x00000001);
788 } else {
789 /* That means the register is LE */
790 out_le32(qspi_key, 0x5af05af0);
791 /* Unlock the lut table */
792 out_le32(qspi_key + 1, 0x00000002);
793 out_le32(qspi_lut, 0x0820040c);
794 out_le32(qspi_lut + 1, 0x1c080c08);
795 out_le32(qspi_lut + 2, 0x00002400);
796 /* Lock the lut table */
797 out_le32(qspi_key, 0x5af05af0);
798 out_le32(qspi_key + 1, 0x00000001);
799 }
800
801 return 0;
802}
803#endif
804
2141d250 805#ifdef CONFIG_TFABOOT
d23da2ae 806#define MAX_BOOTCMD_SIZE 512
2141d250 807
07164d0e 808__weak int fsl_setenv_bootcmd(void)
2141d250
PG		 809{
810 int ret;
811 enum boot_src src = get_boot_src();
812 char bootcmd_str[MAX_BOOTCMD_SIZE];
813
121696c9
ML		 814 bootcmd_str[0] = 0;
815
2141d250
PG		 816 switch (src) {
817#ifdef IFC_NOR_BOOTCOMMAND
818 case BOOT_SOURCE_IFC_NOR:
819 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
820 break;
821#endif
822#ifdef QSPI_NOR_BOOTCOMMAND
823 case BOOT_SOURCE_QSPI_NOR:
824 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
825 break;
826#endif
827#ifdef XSPI_NOR_BOOTCOMMAND
828 case BOOT_SOURCE_XSPI_NOR:
829 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
830 break;
831#endif
832#ifdef IFC_NAND_BOOTCOMMAND
833 case BOOT_SOURCE_IFC_NAND:
834 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
835 break;
836#endif
837#ifdef QSPI_NAND_BOOTCOMMAND
838 case BOOT_SOURCE_QSPI_NAND:
839 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
840 break;
841#endif
842#ifdef XSPI_NAND_BOOTCOMMAND
843 case BOOT_SOURCE_XSPI_NAND:
844 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
845 break;
846#endif
847#ifdef SD_BOOTCOMMAND
848 case BOOT_SOURCE_SD_MMC:
849 sprintf(bootcmd_str, SD_BOOTCOMMAND);
850 break;
851#endif
852#ifdef SD2_BOOTCOMMAND
853 case BOOT_SOURCE_SD_MMC2:
854 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
855 break;
856#endif
857 default:
858#ifdef QSPI_NOR_BOOTCOMMAND
859 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
860#endif
861 break;
862 }
863
121696c9
ML		 864 if (!bootcmd_str[0])
865 return 0;
866
2141d250
PG		 867 ret = env_set("bootcmd", bootcmd_str);
868 if (ret) {
869 printf("Failed to set bootcmd: ret = %d\n", ret);
870 return ret;
871 }
872 return 0;
873}
ade32bb4
PG		 874
875int fsl_setenv_mcinitcmd(void)
876{
877 int ret = 0;
878 enum boot_src src = get_boot_src();
879
880 switch (src) {
881#ifdef IFC_MC_INIT_CMD
882 case BOOT_SOURCE_IFC_NAND:
883 case BOOT_SOURCE_IFC_NOR:
884 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
885 break;
886#endif
887#ifdef QSPI_MC_INIT_CMD
888 case BOOT_SOURCE_QSPI_NAND:
889 case BOOT_SOURCE_QSPI_NOR:
890 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
891 break;
892#endif
893#ifdef XSPI_MC_INIT_CMD
894 case BOOT_SOURCE_XSPI_NAND:
895 case BOOT_SOURCE_XSPI_NOR:
896 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
897 break;
898#endif
899#ifdef SD_MC_INIT_CMD
900 case BOOT_SOURCE_SD_MMC:
901 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
902 break;
903#endif
904#ifdef SD2_MC_INIT_CMD
905 case BOOT_SOURCE_SD_MMC2:
906 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
907 break;
908#endif
909 default:
910#ifdef QSPI_MC_INIT_CMD
911 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
912#endif
913 break;
914 }
915
916 if (ret) {
917 printf("Failed to set mcinitcmd: ret = %d\n", ret);
918 return ret;
919 }
920 return 0;
921}
2141d250
PG		 922#endif
923
9f3183d2 924#ifdef CONFIG_BOARD_LATE_INIT
762ee522
MW		 925__weak int fsl_board_late_init(void)
926{
927 return 0;
928}
929
223c1907
RW		 930#define DWC3_GSBUSCFG0 0xc100
931#define DWC3_GSBUSCFG0_CACHETYPE_SHIFT 16
932#define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \
933 << DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
934
f53e102e 935static void enable_dwc3_snooping(void)
223c1907 936{
f53e102e
MW		 937 static const char * const compatibles[] = {
938 "fsl,layerscape-dwc3",
939 "fsl,ls1028a-dwc3",
940 };
223c1907 941 fdt_addr_t dwc3_base;
f53e102e
MW		 942 ofnode node;
943 u32 val;
944 int i;
223c1907 945
f53e102e
MW		 946 for (i = 0; i < ARRAY_SIZE(compatibles); i++) {
947 ofnode_for_each_compatible_node(node, compatibles[i]) {
948 dwc3_base = ofnode_get_addr(node);
949 if (dwc3_base == FDT_ADDR_T_NONE)
223c1907 950 continue;
f53e102e 951
223c1907
RW		 952 val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
953 val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
954 val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
955 writel(val, dwc3_base + DWC3_GSBUSCFG0);
956 }
957 }
958}
959
9f3183d2 960int board_late_init(void)
b2d5ac59 961{
d0412885
AB		 962#ifdef CONFIG_CHAIN_OF_TRUST
963 fsl_setenv_chain_of_trust();
964#endif
2141d250
PG		 965#ifdef CONFIG_TFABOOT
966 /*
b62c174e
WK		 967 * Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does
968 * not exists in env
d23da2ae 969 */
b62c174e
WK		 970 if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) {
971 // Set bootcmd and mcinitcmd as per boot source
d23da2ae
RB		 972 fsl_setenv_bootcmd();
973 fsl_setenv_mcinitcmd();
b62c174e
WK		 974 env_set("fsl_bootcmd_mcinitcmd_set", "y");
975 }
2141d250 976#endif
dd2ad2f1
YY		 977#ifdef CONFIG_QSPI_AHB_INIT
978 qspi_ahb_init();
979#endif
ce3bead6
KS		 980#ifdef CONFIG_FSPI_AHB_EN_4BYTE
981 fspi_ahb_init();
982#endif
989c5f0a 983
223c1907
RW		 984 if (IS_ENABLED(CONFIG_DM))
985 enable_dwc3_snooping();
986
762ee522 987 return fsl_board_late_init();
b2d5ac59
SW		 988}
989#endif
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