[people/ms/u-boot.git] / arch / arm / cpu / tegra30-common / clock.c

/*
 * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/* Tegra30 Clock control functions */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/timer.h>
#include <div64.h>
#include <fdtdec.h>

/*
 * Clock types that we can use as a source. The Tegra30 has muxes for the
 * peripheral clocks, and in most cases there are four options for the clock
 * source. This gives us a clock 'type' and exploits what commonality exists
 * in the device.
 *
 * Letters are obvious, except for T which means CLK_M, and S which means the
 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
 * datasheet) and PLL_M are different things. The former is the basic
 * clock supplied to the SOC from an external oscillator. The latter is the
 * memory clock PLL.
 *
 * See definitions in clock_id in the header file.
 */
enum clock_type_id {
	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
	CLOCK_TYPE_MCPA,	/* and so on */
	CLOCK_TYPE_MCPT,
	CLOCK_TYPE_PCM,
	CLOCK_TYPE_PCMT,
	CLOCK_TYPE_PCMT16,
	CLOCK_TYPE_PDCT,
	CLOCK_TYPE_ACPT,
	CLOCK_TYPE_ASPTE,
	CLOCK_TYPE_PMDACD2T,
	CLOCK_TYPE_PCST,

	CLOCK_TYPE_COUNT,
	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
};

enum {
	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
};

enum {
	MASK_BITS_31_30 = 2,    /* num of bits used to specify clock source */
	MASK_BITS_31_29,
	MASK_BITS_29_28,
};

/*
 * Clock source mux for each clock type. This just converts our enum into
 * a list of mux sources for use by the code.
 *
 * Note:
 *  The extra column in each clock source array is used to store the mask
 *  bits in its register for the source.
 */
#define CLK(x) CLOCK_ID_ ## x
static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
	{ CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),
		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
		MASK_BITS_31_30},
	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),
		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
		MASK_BITS_31_30},
	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
		MASK_BITS_31_30},
	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE),
		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
		MASK_BITS_31_30},
	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
		MASK_BITS_31_30},
	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
		MASK_BITS_31_30},
	{ CLK(PERIPH),  CLK(DISPLAY),   CLK(CGENERAL),  CLK(OSC),
		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
		MASK_BITS_31_30},
	{ CLK(AUDIO),   CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
		MASK_BITS_31_30},
	{ CLK(AUDIO),   CLK(SFROM32KHZ),	CLK(PERIPH),   CLK(OSC),
		CLK(EPCI),      CLK(NONE),      CLK(NONE),      CLK(NONE),
		MASK_BITS_31_29},
	{ CLK(PERIPH),  CLK(MEMORY),    CLK(DISPLAY),   CLK(AUDIO),
		CLK(CGENERAL),  CLK(DISPLAY2),  CLK(OSC),       CLK(NONE),
		MASK_BITS_31_29},
	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ), CLK(OSC),
		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
		MASK_BITS_29_28}
};

/*
 * Clock type for each peripheral clock source. We put the name in each
 * record just so it is easy to match things up
 */
#define TYPE(name, type) type
static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
	/* 0x00 */
	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
	TYPE(PERIPHC_I2S2,      CLOCK_TYPE_AXPT),
	TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
	TYPE(PERIPHC_SPDIF_IN,  CLOCK_TYPE_PCM),
	TYPE(PERIPHC_PWM,       CLOCK_TYPE_PCST),  /* only PWM uses b29:28 */
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_SBC2,      CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_SBC3,      CLOCK_TYPE_PCMT),

	/* 0x08 */
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_I2C1,      CLOCK_TYPE_PCMT16),
	TYPE(PERIPHC_DVC_I2C,   CLOCK_TYPE_PCMT16),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_SBC1,      CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PMDACD2T),
	TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PMDACD2T),

	/* 0x10 */
	TYPE(PERIPHC_CVE,       CLOCK_TYPE_PDCT),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_SDMMC1,    CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_G3D,	CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_G2D,	CLOCK_TYPE_MCPA),

	/* 0x18 */
	TYPE(PERIPHC_NDFLASH,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_VFIR,      CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_EPP,       CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_MPE,       CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_MIPI,      CLOCK_TYPE_PCMT),       /* MIPI base-band HSI */
	TYPE(PERIPHC_UART1,     CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_UART2,     CLOCK_TYPE_PCMT),

	/* 0x20 */
	TYPE(PERIPHC_HOST1X,    CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_TVO,       CLOCK_TYPE_PDCT),
	TYPE(PERIPHC_HDMI,      CLOCK_TYPE_PMDACD2T),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_TVDAC,     CLOCK_TYPE_PDCT),
	TYPE(PERIPHC_I2C2,      CLOCK_TYPE_PCMT16),
	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),

	/* 0x28 */
	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_SBC4,      CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_I2C3,      CLOCK_TYPE_PCMT16),
	TYPE(PERIPHC_SDMMC3,    CLOCK_TYPE_PCMT),

	/* 0x30 */
	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_OWR,       CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_NOR,       CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_CSITE,     CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_I2S0,      CLOCK_TYPE_AXPT),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),

	/* 0x38h */	     /* Jumps to reg offset 0x3B0h - new for T30 */
	TYPE(PERIPHC_G3D2,      CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_MSELECT,   CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_TSENSOR,   CLOCK_TYPE_PCST),       /* s/b PCTS */
	TYPE(PERIPHC_I2S3,      CLOCK_TYPE_AXPT),
	TYPE(PERIPHC_I2S4,      CLOCK_TYPE_AXPT),
	TYPE(PERIPHC_I2C4,      CLOCK_TYPE_PCMT16),
	TYPE(PERIPHC_SBC5,      CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_SBC6,      CLOCK_TYPE_PCMT),

	/* 0x40 */
	TYPE(PERIPHC_AUDIO,     CLOCK_TYPE_ACPT),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_DAM0,      CLOCK_TYPE_ACPT),
	TYPE(PERIPHC_DAM1,      CLOCK_TYPE_ACPT),
	TYPE(PERIPHC_DAM2,      CLOCK_TYPE_ACPT),
	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_ACTMON,    CLOCK_TYPE_PCST),       /* MASK 31:30 */
	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),

	/* 0x48 */
	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
	TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_I2CSLOW,   CLOCK_TYPE_PCST),       /* MASK 31:30 */
	TYPE(PERIPHC_SYS,       CLOCK_TYPE_NONE),
	TYPE(PERIPHC_SPEEDO,    CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),

	/* 0x50 */
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
	TYPE(PERIPHC_SATAOOB,   CLOCK_TYPE_PCMT),       /* offset 0x420h */
	TYPE(PERIPHC_SATA,      CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_HDA,       CLOCK_TYPE_PCMT),
};

/*
 * This array translates a periph_id to a periphc_internal_id
 *
 * Not present/matched up:
 *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
 *	SPDIF - which is both 0x08 and 0x0c
 *
 */
#define NONE(name) (-1)
#define OFFSET(name, value) PERIPHC_ ## name
static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
	/* Low word: 31:0 */
	NONE(CPU),
	NONE(COP),
	NONE(TRIGSYS),
	NONE(RESERVED3),
	NONE(RESERVED4),
	NONE(TMR),
	PERIPHC_UART1,
	PERIPHC_UART2,  /* and vfir 0x68 */

	/* 8 */
	NONE(GPIO),
	PERIPHC_SDMMC2,
	NONE(SPDIF),	    /* 0x08 and 0x0c, unclear which to use */
	PERIPHC_I2S1,
	PERIPHC_I2C1,
	PERIPHC_NDFLASH,
	PERIPHC_SDMMC1,
	PERIPHC_SDMMC4,

	/* 16 */
	NONE(RESERVED16),
	PERIPHC_PWM,
	PERIPHC_I2S2,
	PERIPHC_EPP,
	PERIPHC_VI,
	PERIPHC_G2D,
	NONE(USBD),
	NONE(ISP),

	/* 24 */
	PERIPHC_G3D,
	NONE(RESERVED25),
	PERIPHC_DISP2,
	PERIPHC_DISP1,
	PERIPHC_HOST1X,
	NONE(VCP),
	PERIPHC_I2S0,
	NONE(CACHE2),

	/* Middle word: 63:32 */
	NONE(MEM),
	NONE(AHBDMA),
	NONE(APBDMA),
	NONE(RESERVED35),
	NONE(RESERVED36),
	NONE(STAT_MON),
	NONE(RESERVED38),
	NONE(RESERVED39),

	/* 40 */
	NONE(KFUSE),
	NONE(SBC1),     /* SBC1, 0x34, is this SPI1? */
	PERIPHC_NOR,
	NONE(RESERVED43),
	PERIPHC_SBC2,
	NONE(RESERVED45),
	PERIPHC_SBC3,
	PERIPHC_DVC_I2C,

	/* 48 */
	NONE(DSI),
	PERIPHC_TVO,    /* also CVE 0x40 */
	PERIPHC_MIPI,
	PERIPHC_HDMI,
	NONE(CSI),
	PERIPHC_TVDAC,
	PERIPHC_I2C2,
	PERIPHC_UART3,

	/* 56 */
	NONE(RESERVED56),
	PERIPHC_EMC,
	NONE(USB2),
	NONE(USB3),
	PERIPHC_MPE,
	PERIPHC_VDE,
	NONE(BSEA),
	NONE(BSEV),

	/* Upper word 95:64 */
	PERIPHC_SPEEDO,
	PERIPHC_UART4,
	PERIPHC_UART5,
	PERIPHC_I2C3,
	PERIPHC_SBC4,
	PERIPHC_SDMMC3,
	NONE(PCIE),
	PERIPHC_OWR,

	/* 72 */
	NONE(AFI),
	PERIPHC_CSITE,
	NONE(PCIEXCLK),
	NONE(AVPUCQ),
	NONE(RESERVED76),
	NONE(RESERVED77),
	NONE(RESERVED78),
	NONE(DTV),

	/* 80 */
	PERIPHC_NANDSPEED,
	PERIPHC_I2CSLOW,
	NONE(DSIB),
	NONE(RESERVED83),
	NONE(IRAMA),
	NONE(IRAMB),
	NONE(IRAMC),
	NONE(IRAMD),

	/* 88 */
	NONE(CRAM2),
	NONE(RESERVED89),
	NONE(MDOUBLER),
	NONE(RESERVED91),
	NONE(SUSOUT),
	NONE(RESERVED93),
	NONE(RESERVED94),
	NONE(RESERVED95),

	/* V word: 31:0 */
	NONE(CPUG),
	NONE(CPULP),
	PERIPHC_G3D2,
	PERIPHC_MSELECT,
	PERIPHC_TSENSOR,
	PERIPHC_I2S3,
	PERIPHC_I2S4,
	PERIPHC_I2C4,

	/* 08 */
	PERIPHC_SBC5,
	PERIPHC_SBC6,
	PERIPHC_AUDIO,
	NONE(APBIF),
	PERIPHC_DAM0,
	PERIPHC_DAM1,
	PERIPHC_DAM2,
	PERIPHC_HDA2CODEC2X,

	/* 16 */
	NONE(ATOMICS),
	NONE(RESERVED17),
	NONE(RESERVED18),
	NONE(RESERVED19),
	NONE(RESERVED20),
	NONE(RESERVED21),
	NONE(RESERVED22),
	PERIPHC_ACTMON,

	/* 24 */
	NONE(RESERVED24),
	NONE(RESERVED25),
	NONE(RESERVED26),
	NONE(RESERVED27),
	PERIPHC_SATA,
	PERIPHC_HDA,
	NONE(RESERVED30),
	NONE(RESERVED31),

	/* W word: 31:0 */
	NONE(HDA2HDMICODEC),
	NONE(SATACOLD),
	NONE(RESERVED0_PCIERX0),
	NONE(RESERVED1_PCIERX1),
	NONE(RESERVED2_PCIERX2),
	NONE(RESERVED3_PCIERX3),
	NONE(RESERVED4_PCIERX4),
	NONE(RESERVED5_PCIERX5),

	/* 40 */
	NONE(CEC),
	NONE(RESERVED6_PCIE2),
	NONE(RESERVED7_EMC),
	NONE(RESERVED8_HDMI),
	NONE(RESERVED9_SATA),
	NONE(RESERVED10_MIPI),
	NONE(EX_RESERVED46),
	NONE(EX_RESERVED47),
};

/*
 * Get the oscillator frequency, from the corresponding hardware configuration
 * field. Note that T30 supports 3 new higher freqs, but we map back
 * to the old T20 freqs. Support for the higher oscillators is TBD.
 */
enum clock_osc_freq clock_get_osc_freq(void)
{
	struct clk_rst_ctlr *clkrst =
			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 reg;

	reg = readl(&clkrst->crc_osc_ctrl);
	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;

	if (reg & 1)			/* one of the newer freqs */
		printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);

	return reg >> 2;	/* Map to most common (T20) freqs */
}

/* Returns a pointer to the clock source register for a peripheral */
u32 *get_periph_source_reg(enum periph_id periph_id)
{
	struct clk_rst_ctlr *clkrst =
		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	enum periphc_internal_id internal_id;

	/* Coresight is a special case */
	if (periph_id == PERIPH_ID_CSI)
		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];

	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
	internal_id = periph_id_to_internal_id[periph_id];
	assert(internal_id != -1);
	if (internal_id >= PERIPHC_VW_FIRST) {
		internal_id -= PERIPHC_VW_FIRST;
		return &clkrst->crc_clk_src_vw[internal_id];
	} else
		return &clkrst->crc_clk_src[internal_id];
}

/**
 * Given a peripheral ID and the required source clock, this returns which
 * value should be programmed into the source mux for that peripheral.
 *
 * There is special code here to handle the one source type with 5 sources.
 *
 * @param periph_id	peripheral to start
 * @param source	PLL id of required parent clock
 * @param mux_bits	Set to number of bits in mux register: 2 or 4
 * @param divider_bits  Set to number of divider bits (8 or 16)
 * @return mux value (0-4, or -1 if not found)
 */
int get_periph_clock_source(enum periph_id periph_id,
	enum clock_id parent, int *mux_bits, int *divider_bits)
{
	enum clock_type_id type;
	enum periphc_internal_id internal_id;
	int mux;

	assert(clock_periph_id_isvalid(periph_id));

	internal_id = periph_id_to_internal_id[periph_id];
	assert(periphc_internal_id_isvalid(internal_id));

	type = clock_periph_type[internal_id];
	assert(clock_type_id_isvalid(type));

	*mux_bits = clock_source[type][CLOCK_MAX_MUX];

	if (type == CLOCK_TYPE_PCMT16)
		*divider_bits = 16;
	else
		*divider_bits = 8;

	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
		if (clock_source[type][mux] == parent)
			return mux;

	/* if we get here, either us or the caller has made a mistake */
	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
		parent);
	return -1;
}

void clock_set_enable(enum periph_id periph_id, int enable)
{
	struct clk_rst_ctlr *clkrst =
			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 *clk;
	u32 reg;

	/* Enable/disable the clock to this peripheral */
	assert(clock_periph_id_isvalid(periph_id));
	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
	else
		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
	reg = readl(clk);
	if (enable)
		reg |= PERIPH_MASK(periph_id);
	else
		reg &= ~PERIPH_MASK(periph_id);
	writel(reg, clk);
}

void reset_set_enable(enum periph_id periph_id, int enable)
{
	struct clk_rst_ctlr *clkrst =
			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 *reset;
	u32 reg;

	/* Enable/disable reset to the peripheral */
	assert(clock_periph_id_isvalid(periph_id));
	if (periph_id < PERIPH_ID_VW_FIRST)
		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
	else
		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
	reg = readl(reset);
	if (enable)
		reg |= PERIPH_MASK(periph_id);
	else
		reg &= ~PERIPH_MASK(periph_id);
	writel(reg, reset);
}

#ifdef CONFIG_OF_CONTROL
/*
 * Convert a device tree clock ID to our peripheral ID. They are mostly
 * the same but we are very cautious so we check that a valid clock ID is
 * provided.
 *
 * @param clk_id	Clock ID according to tegra30 device tree binding
 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
 */
enum periph_id clk_id_to_periph_id(int clk_id)
{
	if (clk_id > PERIPH_ID_COUNT)
		return PERIPH_ID_NONE;

	switch (clk_id) {
	case PERIPH_ID_RESERVED3:
	case PERIPH_ID_RESERVED4:
	case PERIPH_ID_RESERVED16:
	case PERIPH_ID_RESERVED24:
	case PERIPH_ID_RESERVED35:
	case PERIPH_ID_RESERVED43:
	case PERIPH_ID_RESERVED45:
	case PERIPH_ID_RESERVED56:
	case PERIPH_ID_RESERVED76:
	case PERIPH_ID_RESERVED77:
	case PERIPH_ID_RESERVED78:
	case PERIPH_ID_RESERVED83:
	case PERIPH_ID_RESERVED89:
	case PERIPH_ID_RESERVED91:
	case PERIPH_ID_RESERVED93:
	case PERIPH_ID_RESERVED94:
	case PERIPH_ID_RESERVED95:
		return PERIPH_ID_NONE;
	default:
		return clk_id;
	}
}
#endif /* CONFIG_OF_CONTROL */

void clock_early_init(void)
{
	/*
	 * PLLP output frequency set to 408Mhz
	 * PLLC output frequency set to 228Mhz
	 */
	switch (clock_get_osc_freq()) {
	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
		clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
		break;

	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
		break;

	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
		clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
		break;
	case CLOCK_OSC_FREQ_19_2:
	default:
		/*
		 * These are not supported. It is too early to print a
		 * message and the UART likely won't work anyway due to the
		 * oscillator being wrong.
		 */
		break;
	}
}
Commit	Line	Data
b2871037	1	/*
f29f086a	2	* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
b2871037 TW	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	/* Tegra30 Clock control functions */
	18
	19	#include <common.h>
	20	#include <asm/io.h>
	21	#include <asm/arch/clock.h>
	22	#include <asm/arch/tegra.h>
	23	#include <asm/arch-tegra/clk_rst.h>
	24	#include <asm/arch-tegra/timer.h>
	25	#include <div64.h>
	26	#include <fdtdec.h>
	27
	28	/*
f29f086a	29	* Clock types that we can use as a source. The Tegra30 has muxes for the
b2871037 TW	30	* peripheral clocks, and in most cases there are four options for the clock
	31	* source. This gives us a clock 'type' and exploits what commonality exists
	32	* in the device.
	33	*
	34	* Letters are obvious, except for T which means CLK_M, and S which means the
	35	* clock derived from 32KHz. Beware that CLK_M (also called OSC in the
	36	* datasheet) and PLL_M are different things. The former is the basic
	37	* clock supplied to the SOC from an external oscillator. The latter is the
	38	* memory clock PLL.
	39	*
	40	* See definitions in clock_id in the header file.
	41	*/
	42	enum clock_type_id {
	43	CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
	44	CLOCK_TYPE_MCPA, /* and so on */
	45	CLOCK_TYPE_MCPT,
	46	CLOCK_TYPE_PCM,
	47	CLOCK_TYPE_PCMT,
619bd99e	48	CLOCK_TYPE_PCMT16,
b2871037 TW	49	CLOCK_TYPE_PDCT,
	50	CLOCK_TYPE_ACPT,
	51	CLOCK_TYPE_ASPTE,
	52	CLOCK_TYPE_PMDACD2T,
	53	CLOCK_TYPE_PCST,
	54
	55	CLOCK_TYPE_COUNT,
f29f086a	56	CLOCK_TYPE_NONE = -1, /* invalid clock type */
b2871037 TW	57	};
b2871037 TW	58
b2871037	59	enum {
f29f086a	60	CLOCK_MAX_MUX = 8 /* number of source options for each clock */
b2871037 TW	61	};
	62
	63	enum {
f29f086a	64	MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
b2871037 TW	65	MASK_BITS_31_29,
	66	MASK_BITS_29_28,
	67	};
	68
	69	/*
	70	* Clock source mux for each clock type. This just converts our enum into
	71	* a list of mux sources for use by the code.
	72	*
	73	* Note:
	74	* The extra column in each clock source array is used to store the mask
	75	* bits in its register for the source.
	76	*/
	77	#define CLK(x) CLOCK_ID_ ## x
	78	static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
f29f086a TW	79	{ CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
f29f086a TW	80	CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
b2871037	81	MASK_BITS_31_30},
f29f086a TW	82	{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
f29f086a TW	83	CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
b2871037	84	MASK_BITS_31_30},
f29f086a TW	85	{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
f29f086a TW	86	CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
b2871037	87	MASK_BITS_31_30},
f29f086a TW	88	{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
f29f086a TW	89	CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
b2871037	90	MASK_BITS_31_30},
f29f086a TW	91	{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
f29f086a TW	92	CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
b2871037	93	MASK_BITS_31_30},
f29f086a TW	94	{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
f29f086a TW	95	CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
619bd99e	96	MASK_BITS_31_30},
f29f086a TW	97	{ CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
f29f086a TW	98	CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
b2871037	99	MASK_BITS_31_30},
f29f086a TW	100	{ CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
f29f086a TW	101	CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
b2871037	102	MASK_BITS_31_30},
f29f086a TW	103	{ CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
f29f086a TW	104	CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
b2871037	105	MASK_BITS_31_29},
f29f086a TW	106	{ CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
f29f086a TW	107	CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
b2871037	108	MASK_BITS_31_29},
f29f086a TW	109	{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
f29f086a TW	110	CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
b2871037 TW	111	MASK_BITS_29_28}
	112	};
	113
b2871037 TW	114	/*
	115	* Clock type for each peripheral clock source. We put the name in each
	116	* record just so it is easy to match things up
	117	*/
	118	#define TYPE(name, type) type
	119	static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
	120	/* 0x00 */
	121	TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
f29f086a TW	122	TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
	123	TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
	124	TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
	125	TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
	126	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	127	TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
	128	TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
b2871037 TW	129
b2871037 TW	130	/* 0x08 */
f29f086a TW	131	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	132	TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
	133	TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
	134	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	135	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	136	TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
	137	TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
	138	TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
b2871037 TW	139
b2871037 TW	140	/* 0x10 */
f29f086a TW	141	TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
f29f086a TW	142	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
b2871037	143	TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
f29f086a TW	144	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
f29f086a TW	145	TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
b2871037 TW	146	TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
	147	TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
	148	TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
	149
	150	/* 0x18 */
	151	TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
	152	TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
f29f086a TW	153	TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
	154	TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
	155	TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
	156	TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
	157	TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
	158	TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
b2871037 TW	159
b2871037 TW	160	/* 0x20 */
f29f086a TW	161	TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
	162	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	163	TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
	164	TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
	165	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	166	TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
	167	TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
b2871037 TW	168	TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
	169
	170	/* 0x28 */
	171	TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
	172	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	173	TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
f29f086a TW	174	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	175	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	176	TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
	177	TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
	178	TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
b2871037 TW	179
	180	/* 0x30 */
	181	TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
	182	TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
	183	TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
f29f086a TW	184	TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
	185	TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
	186	TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
	187	TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
	188	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	189
	190	/* 0x38h / / Jumps to reg offset 0x3B0h - new for T30 */
	191	TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
	192	TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
	193	TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
	194	TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
	195	TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
	196	TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
	197	TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
	198	TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
b2871037 TW	199
b2871037 TW	200	/* 0x40 */
f29f086a TW	201	TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
	202	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	203	TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
	204	TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
	205	TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
b2871037	206	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
f29f086a	207	TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
b2871037 TW	208	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
	209
	210	/* 0x48 */
	211	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
	212	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
f29f086a TW	213	TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
	214	TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
	215	TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
	216	TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
	217	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	218	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
b2871037 TW	219
b2871037 TW	220	/* 0x50 */
f29f086a TW	221	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	222	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	223	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	224	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	225	TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
	226	TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
	227	TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
b2871037 TW	228	};
	229
	230	/*
	231	* This array translates a periph_id to a periphc_internal_id
	232	*
	233	* Not present/matched up:
	234	* uint vi_sensor; _VI_SENSOR_0, 0x1A8
	235	* SPDIF - which is both 0x08 and 0x0c
	236	*
	237	*/
	238	#define NONE(name) (-1)
	239	#define OFFSET(name, value) PERIPHC_ ## name
	240	static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
	241	/* Low word: 31:0 */
	242	NONE(CPU),
	243	NONE(COP),
	244	NONE(TRIGSYS),
	245	NONE(RESERVED3),
	246	NONE(RESERVED4),
	247	NONE(TMR),
	248	PERIPHC_UART1,
f29f086a	249	PERIPHC_UART2, /* and vfir 0x68 */
b2871037 TW	250
	251	/* 8 */
	252	NONE(GPIO),
	253	PERIPHC_SDMMC2,
f29f086a	254	NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
b2871037 TW	255	PERIPHC_I2S1,
	256	PERIPHC_I2C1,
	257	PERIPHC_NDFLASH,
	258	PERIPHC_SDMMC1,
	259	PERIPHC_SDMMC4,
	260
	261	/* 16 */
	262	NONE(RESERVED16),
	263	PERIPHC_PWM,
	264	PERIPHC_I2S2,
	265	PERIPHC_EPP,
	266	PERIPHC_VI,
	267	PERIPHC_G2D,
	268	NONE(USBD),
	269	NONE(ISP),
	270
	271	/* 24 */
	272	PERIPHC_G3D,
	273	NONE(RESERVED25),
	274	PERIPHC_DISP2,
	275	PERIPHC_DISP1,
	276	PERIPHC_HOST1X,
	277	NONE(VCP),
	278	PERIPHC_I2S0,
	279	NONE(CACHE2),
	280
	281	/* Middle word: 63:32 */
	282	NONE(MEM),
	283	NONE(AHBDMA),
	284	NONE(APBDMA),
	285	NONE(RESERVED35),
	286	NONE(RESERVED36),
	287	NONE(STAT_MON),
	288	NONE(RESERVED38),
	289	NONE(RESERVED39),
	290
	291	/* 40 */
	292	NONE(KFUSE),
f29f086a	293	NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
b2871037 TW	294	PERIPHC_NOR,
	295	NONE(RESERVED43),
	296	PERIPHC_SBC2,
	297	NONE(RESERVED45),
	298	PERIPHC_SBC3,
	299	PERIPHC_DVC_I2C,
	300
	301	/* 48 */
	302	NONE(DSI),
f29f086a	303	PERIPHC_TVO, /* also CVE 0x40 */
b2871037 TW	304	PERIPHC_MIPI,
	305	PERIPHC_HDMI,
	306	NONE(CSI),
	307	PERIPHC_TVDAC,
	308	PERIPHC_I2C2,
	309	PERIPHC_UART3,
	310
	311	/* 56 */
	312	NONE(RESERVED56),
	313	PERIPHC_EMC,
	314	NONE(USB2),
	315	NONE(USB3),
	316	PERIPHC_MPE,
	317	PERIPHC_VDE,
	318	NONE(BSEA),
	319	NONE(BSEV),
	320
	321	/* Upper word 95:64 */
	322	PERIPHC_SPEEDO,
	323	PERIPHC_UART4,
	324	PERIPHC_UART5,
	325	PERIPHC_I2C3,
	326	PERIPHC_SBC4,
	327	PERIPHC_SDMMC3,
	328	NONE(PCIE),
	329	PERIPHC_OWR,
	330
	331	/* 72 */
	332	NONE(AFI),
	333	PERIPHC_CSITE,
	334	NONE(PCIEXCLK),
	335	NONE(AVPUCQ),
	336	NONE(RESERVED76),
	337	NONE(RESERVED77),
	338	NONE(RESERVED78),
	339	NONE(DTV),
	340
	341	/* 80 */
	342	PERIPHC_NANDSPEED,
	343	PERIPHC_I2CSLOW,
	344	NONE(DSIB),
	345	NONE(RESERVED83),
	346	NONE(IRAMA),
	347	NONE(IRAMB),
	348	NONE(IRAMC),
	349	NONE(IRAMD),
	350
	351	/* 88 */
	352	NONE(CRAM2),
	353	NONE(RESERVED89),
	354	NONE(MDOUBLER),
	355	NONE(RESERVED91),
	356	NONE(SUSOUT),
	357	NONE(RESERVED93),
	358	NONE(RESERVED94),
	359	NONE(RESERVED95),
	360
	361	/* V word: 31:0 */
	362	NONE(CPUG),
	363	NONE(CPULP),
	364	PERIPHC_G3D2,
	365	PERIPHC_MSELECT,
	366	PERIPHC_TSENSOR,
	367	PERIPHC_I2S3,
368	PERIPHC_I2S4,
369	PERIPHC_I2C4,
370
371	/* 08 */
372	PERIPHC_SBC5,
373	PERIPHC_SBC6,
374	PERIPHC_AUDIO,
375	NONE(APBIF),
376	PERIPHC_DAM0,
377	PERIPHC_DAM1,
378	PERIPHC_DAM2,
379	PERIPHC_HDA2CODEC2X,
380
381	/* 16 */
382	NONE(ATOMICS),
383	NONE(RESERVED17),
384	NONE(RESERVED18),
385	NONE(RESERVED19),
386	NONE(RESERVED20),
387	NONE(RESERVED21),
388	NONE(RESERVED22),
389	PERIPHC_ACTMON,
390
391	/* 24 */
392	NONE(RESERVED24),
393	NONE(RESERVED25),
394	NONE(RESERVED26),
395	NONE(RESERVED27),
396	PERIPHC_SATA,
397	PERIPHC_HDA,
398	NONE(RESERVED30),
399	NONE(RESERVED31),
400
401	/* W word: 31:0 */
402	NONE(HDA2HDMICODEC),
403	NONE(SATACOLD),
404	NONE(RESERVED0_PCIERX0),
405	NONE(RESERVED1_PCIERX1),
406	NONE(RESERVED2_PCIERX2),
407	NONE(RESERVED3_PCIERX3),
408	NONE(RESERVED4_PCIERX4),
409	NONE(RESERVED5_PCIERX5),
410
411	/* 40 */
412	NONE(CEC),
413	NONE(RESERVED6_PCIE2),
414	NONE(RESERVED7_EMC),
415	NONE(RESERVED8_HDMI),
416	NONE(RESERVED9_SATA),
417	NONE(RESERVED10_MIPI),
418	NONE(EX_RESERVED46),
419	NONE(EX_RESERVED47),
420	};
421
422	/*
423	* Get the oscillator frequency, from the corresponding hardware configuration
f29f086a TW	424	* field. Note that T30 supports 3 new higher freqs, but we map back
f29f086a TW	425	* to the old T20 freqs. Support for the higher oscillators is TBD.
b2871037 TW	426	*/
	427	enum clock_osc_freq clock_get_osc_freq(void)
	428	{
	429	struct clk_rst_ctlr *clkrst =
	430	(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	431	u32 reg;
	432
	433	reg = readl(&clkrst->crc_osc_ctrl);
f29f086a	434	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
b2871037	435
f29f086a TW	436	if (reg & 1) /* one of the newer freqs */
f29f086a TW	437	printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
b2871037	438
f29f086a	439	return reg >> 2; /* Map to most common (T20) freqs */
b2871037 TW	440	}
	441
	442	/* Returns a pointer to the clock source register for a peripheral */
f29f086a	443	u32 *get_periph_source_reg(enum periph_id periph_id)
b2871037 TW	444	{
b2871037 TW	445	struct clk_rst_ctlr *clkrst =
f29f086a	446	(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
b2871037 TW	447	enum periphc_internal_id internal_id;
	448
	449	/* Coresight is a special case */
	450	if (periph_id == PERIPH_ID_CSI)
	451	return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
	452
	453	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
	454	internal_id = periph_id_to_internal_id[periph_id];
	455	assert(internal_id != -1);
	456	if (internal_id >= PERIPHC_VW_FIRST) {
	457	internal_id -= PERIPHC_VW_FIRST;
	458	return &clkrst->crc_clk_src_vw[internal_id];
	459	} else
	460	return &clkrst->crc_clk_src[internal_id];
	461	}
	462
b2871037 TW	463	/**
	464	* Given a peripheral ID and the required source clock, this returns which
	465	* value should be programmed into the source mux for that peripheral.
	466	*
	467	* There is special code here to handle the one source type with 5 sources.
	468	*
	469	* @param periph_id peripheral to start
	470	* @param source PLL id of required parent clock
	471	* @param mux_bits Set to number of bits in mux register: 2 or 4
f29f086a	472	* @param divider_bits Set to number of divider bits (8 or 16)
b2871037 TW	473	* @return mux value (0-4, or -1 if not found)
b2871037 TW	474	*/
f29f086a TW	475	int get_periph_clock_source(enum periph_id periph_id,
f29f086a TW	476	enum clock_id parent, int mux_bits, int divider_bits)
b2871037 TW	477	{
	478	enum clock_type_id type;
	479	enum periphc_internal_id internal_id;
	480	int mux;
	481
	482	assert(clock_periph_id_isvalid(periph_id));
	483
	484	internal_id = periph_id_to_internal_id[periph_id];
	485	assert(periphc_internal_id_isvalid(internal_id));
	486
	487	type = clock_periph_type[internal_id];
	488	assert(clock_type_id_isvalid(type));
	489
	490	*mux_bits = clock_source[type][CLOCK_MAX_MUX];
	491
619bd99e TW	492	if (type == CLOCK_TYPE_PCMT16)
	493	*divider_bits = 16;
	494	else
	495	*divider_bits = 8;
	496
b2871037 TW	497	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
	498	if (clock_source[type][mux] == parent)
	499	return mux;
	500
	501	/* if we get here, either us or the caller has made a mistake */
	502	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
	503	parent);
	504	return -1;
	505	}
	506
b2871037 TW	507	void clock_set_enable(enum periph_id periph_id, int enable)
	508	{
	509	struct clk_rst_ctlr *clkrst =
	510	(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	511	u32 *clk;
	512	u32 reg;
	513
	514	/* Enable/disable the clock to this peripheral */
	515	assert(clock_periph_id_isvalid(periph_id));
	516	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
	517	clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
	518	else
	519	clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
	520	reg = readl(clk);
	521	if (enable)
	522	reg \|= PERIPH_MASK(periph_id);
	523	else
	524	reg &= ~PERIPH_MASK(periph_id);
	525	writel(reg, clk);
	526	}
	527
b2871037 TW	528	void reset_set_enable(enum periph_id periph_id, int enable)
	529	{
	530	struct clk_rst_ctlr *clkrst =
	531	(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	532	u32 *reset;
	533	u32 reg;
	534
	535	/* Enable/disable reset to the peripheral */
	536	assert(clock_periph_id_isvalid(periph_id));
	537	if (periph_id < PERIPH_ID_VW_FIRST)
	538	reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
	539	else
	540	reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
	541	reg = readl(reset);
	542	if (enable)
	543	reg \|= PERIPH_MASK(periph_id);
	544	else
	545	reg &= ~PERIPH_MASK(periph_id);
	546	writel(reg, reset);
	547	}
	548
b2871037 TW	549	#ifdef CONFIG_OF_CONTROL
	550	/*
	551	* Convert a device tree clock ID to our peripheral ID. They are mostly
	552	* the same but we are very cautious so we check that a valid clock ID is
	553	* provided.
	554	*
619bd99e	555	* @param clk_id Clock ID according to tegra30 device tree binding
b2871037 TW	556	* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
b2871037 TW	557	*/
f29f086a	558	enum periph_id clk_id_to_periph_id(int clk_id)
b2871037	559	{
619bd99e	560	if (clk_id > PERIPH_ID_COUNT)
b2871037 TW	561	return PERIPH_ID_NONE;
	562
	563	switch (clk_id) {
619bd99e TW	564	case PERIPH_ID_RESERVED3:
	565	case PERIPH_ID_RESERVED4:
	566	case PERIPH_ID_RESERVED16:
	567	case PERIPH_ID_RESERVED24:
	568	case PERIPH_ID_RESERVED35:
	569	case PERIPH_ID_RESERVED43:
	570	case PERIPH_ID_RESERVED45:
	571	case PERIPH_ID_RESERVED56:
	572	case PERIPH_ID_RESERVED76:
	573	case PERIPH_ID_RESERVED77:
	574	case PERIPH_ID_RESERVED78:
	575	case PERIPH_ID_RESERVED83:
	576	case PERIPH_ID_RESERVED89:
	577	case PERIPH_ID_RESERVED91:
	578	case PERIPH_ID_RESERVED93:
	579	case PERIPH_ID_RESERVED94:
	580	case PERIPH_ID_RESERVED95:
b2871037 TW	581	return PERIPH_ID_NONE;
	582	default:
	583	return clk_id;
	584	}
	585	}
b2871037 TW	586	#endif /* CONFIG_OF_CONTROL */
b2871037 TW	587
b2871037 TW	588	void clock_early_init(void)
	589	{
	590	/*
	591	* PLLP output frequency set to 408Mhz
	592	* PLLC output frequency set to 228Mhz
	593	*/
	594	switch (clock_get_osc_freq()) {
	595	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
	596	clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
	597	clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
	598	break;
	599
	600	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
	601	clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
	602	clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
	603	break;
	604
	605	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
	606	clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
	607	clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
	608	break;
	609	case CLOCK_OSC_FREQ_19_2:
	610	default:
	611	/*
	612	* These are not supported. It is too early to print a
	613	* message and the UART likely won't work anyway due to the
	614	* oscillator being wrong.
	615	*/
	616	break;
	617	}
	618	}