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e5520e18 M |
1 | /* |
2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | /dts-v1/; | |
9 | ||
10 | #include "dra74x.dtsi" | |
11 | #include <dt-bindings/gpio/gpio.h> | |
12 | ||
13 | / { | |
14 | model = "TI DRA742"; | |
15 | compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; | |
16 | ||
0935df65 M |
17 | chosen { |
18 | stdout-path = &uart1; | |
87a2127f | 19 | tick-timer = &timer2; |
0935df65 M |
20 | }; |
21 | ||
e5520e18 M |
22 | memory { |
23 | device_type = "memory"; | |
24 | reg = <0x80000000 0x60000000>; /* 1536 MB */ | |
25 | }; | |
26 | ||
27 | mmc2_3v3: fixedregulator-mmc2 { | |
28 | compatible = "regulator-fixed"; | |
29 | regulator-name = "mmc2_3v3"; | |
30 | regulator-min-microvolt = <3300000>; | |
31 | regulator-max-microvolt = <3300000>; | |
32 | }; | |
33 | ||
34 | extcon_usb1: extcon_usb1 { | |
35 | compatible = "linux,extcon-usb-gpio"; | |
36 | id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; | |
37 | }; | |
38 | ||
39 | extcon_usb2: extcon_usb2 { | |
40 | compatible = "linux,extcon-usb-gpio"; | |
41 | id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; | |
42 | }; | |
43 | ||
44 | vtt_fixed: fixedregulator-vtt { | |
45 | compatible = "regulator-fixed"; | |
46 | regulator-name = "vtt_fixed"; | |
47 | regulator-min-microvolt = <1350000>; | |
48 | regulator-max-microvolt = <1350000>; | |
49 | regulator-always-on; | |
50 | regulator-boot-on; | |
51 | enable-active-high; | |
52 | gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; | |
53 | }; | |
54 | }; | |
55 | ||
56 | &dra7_pmx_core { | |
57 | pinctrl-names = "default"; | |
58 | pinctrl-0 = <&vtt_pin>; | |
59 | ||
60 | vtt_pin: pinmux_vtt_pin { | |
61 | pinctrl-single,pins = < | |
62 | 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ | |
63 | >; | |
64 | }; | |
65 | ||
66 | i2c1_pins: pinmux_i2c1_pins { | |
67 | pinctrl-single,pins = < | |
68 | 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ | |
69 | 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ | |
70 | >; | |
71 | }; | |
72 | ||
73 | i2c2_pins: pinmux_i2c2_pins { | |
74 | pinctrl-single,pins = < | |
75 | 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ | |
76 | 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ | |
77 | >; | |
78 | }; | |
79 | ||
80 | i2c3_pins: pinmux_i2c3_pins { | |
81 | pinctrl-single,pins = < | |
82 | 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ | |
83 | 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ | |
84 | >; | |
85 | }; | |
86 | ||
87 | mcspi1_pins: pinmux_mcspi1_pins { | |
88 | pinctrl-single,pins = < | |
89 | 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */ | |
90 | 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */ | |
91 | 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */ | |
92 | 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ | |
93 | 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ | |
94 | 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ | |
95 | >; | |
96 | }; | |
97 | ||
98 | mcspi2_pins: pinmux_mcspi2_pins { | |
99 | pinctrl-single,pins = < | |
100 | 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */ | |
101 | 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ | |
102 | 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ | |
103 | 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ | |
104 | >; | |
105 | }; | |
106 | ||
107 | uart1_pins: pinmux_uart1_pins { | |
108 | pinctrl-single,pins = < | |
109 | 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ | |
110 | 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ | |
111 | 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ | |
112 | 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ | |
113 | >; | |
114 | }; | |
115 | ||
116 | uart2_pins: pinmux_uart2_pins { | |
117 | pinctrl-single,pins = < | |
118 | 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */ | |
119 | 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */ | |
120 | 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ | |
121 | 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ | |
122 | >; | |
123 | }; | |
124 | ||
125 | uart3_pins: pinmux_uart3_pins { | |
126 | pinctrl-single,pins = < | |
127 | 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ | |
128 | 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ | |
129 | >; | |
130 | }; | |
131 | ||
132 | qspi1_pins: pinmux_qspi1_pins { | |
133 | pinctrl-single,pins = < | |
134 | 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ | |
135 | 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ | |
136 | 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ | |
137 | 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ | |
138 | 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ | |
139 | 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ | |
140 | 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ | |
141 | 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ | |
142 | 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ | |
143 | 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ | |
144 | >; | |
145 | }; | |
146 | ||
147 | usb1_pins: pinmux_usb1_pins { | |
148 | pinctrl-single,pins = < | |
149 | 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ | |
150 | >; | |
151 | }; | |
152 | ||
153 | usb2_pins: pinmux_usb2_pins { | |
154 | pinctrl-single,pins = < | |
155 | 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ | |
156 | >; | |
157 | }; | |
158 | ||
159 | nand_flash_x16: nand_flash_x16 { | |
160 | /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch | |
161 | * So NAND flash requires following switch settings: | |
162 | * SW5.9 (GPMC_WPN) = LOW | |
163 | * SW5.1 (NAND_BOOTn) = HIGH */ | |
164 | pinctrl-single,pins = < | |
165 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ | |
166 | 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ | |
167 | 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ | |
168 | 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ | |
169 | 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ | |
170 | 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ | |
171 | 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ | |
172 | 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ | |
173 | 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ | |
174 | 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ | |
175 | 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ | |
176 | 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ | |
177 | 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ | |
178 | 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ | |
179 | 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ | |
180 | 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ | |
181 | 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ | |
182 | 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ | |
183 | 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ | |
184 | 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ | |
185 | 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ | |
186 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ | |
187 | >; | |
188 | }; | |
189 | ||
190 | cpsw_default: cpsw_default { | |
191 | pinctrl-single,pins = < | |
192 | /* Slave 1 */ | |
193 | 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ | |
194 | 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ | |
195 | 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ | |
196 | 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ | |
197 | 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ | |
198 | 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ | |
199 | 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ | |
200 | 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ | |
201 | 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ | |
202 | 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ | |
203 | 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ | |
204 | 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ | |
205 | ||
206 | /* Slave 2 */ | |
207 | 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ | |
208 | 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ | |
209 | 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ | |
210 | 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ | |
211 | 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ | |
212 | 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ | |
213 | 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ | |
214 | 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ | |
215 | 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ | |
216 | 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ | |
217 | 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ | |
218 | 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ | |
219 | >; | |
220 | ||
221 | }; | |
222 | ||
223 | cpsw_sleep: cpsw_sleep { | |
224 | pinctrl-single,pins = < | |
225 | /* Slave 1 */ | |
226 | 0x250 (MUX_MODE15) | |
227 | 0x254 (MUX_MODE15) | |
228 | 0x258 (MUX_MODE15) | |
229 | 0x25c (MUX_MODE15) | |
230 | 0x260 (MUX_MODE15) | |
231 | 0x264 (MUX_MODE15) | |
232 | 0x268 (MUX_MODE15) | |
233 | 0x26c (MUX_MODE15) | |
234 | 0x270 (MUX_MODE15) | |
235 | 0x274 (MUX_MODE15) | |
236 | 0x278 (MUX_MODE15) | |
237 | 0x27c (MUX_MODE15) | |
238 | ||
239 | /* Slave 2 */ | |
240 | 0x198 (MUX_MODE15) | |
241 | 0x19c (MUX_MODE15) | |
242 | 0x1a0 (MUX_MODE15) | |
243 | 0x1a4 (MUX_MODE15) | |
244 | 0x1a8 (MUX_MODE15) | |
245 | 0x1ac (MUX_MODE15) | |
246 | 0x1b0 (MUX_MODE15) | |
247 | 0x1b4 (MUX_MODE15) | |
248 | 0x1b8 (MUX_MODE15) | |
249 | 0x1bc (MUX_MODE15) | |
250 | 0x1c0 (MUX_MODE15) | |
251 | 0x1c4 (MUX_MODE15) | |
252 | >; | |
253 | }; | |
254 | ||
255 | davinci_mdio_default: davinci_mdio_default { | |
256 | pinctrl-single,pins = < | |
257 | 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ | |
258 | 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
259 | >; | |
260 | }; | |
261 | ||
262 | davinci_mdio_sleep: davinci_mdio_sleep { | |
263 | pinctrl-single,pins = < | |
264 | 0x23c (MUX_MODE15) | |
265 | 0x240 (MUX_MODE15) | |
266 | >; | |
267 | }; | |
268 | ||
269 | dcan1_pins_default: dcan1_pins_default { | |
270 | pinctrl-single,pins = < | |
271 | 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ | |
272 | 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ | |
273 | >; | |
274 | }; | |
275 | ||
276 | dcan1_pins_sleep: dcan1_pins_sleep { | |
277 | pinctrl-single,pins = < | |
278 | 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ | |
279 | 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ | |
280 | >; | |
281 | }; | |
282 | }; | |
283 | ||
284 | &i2c1 { | |
285 | status = "okay"; | |
286 | pinctrl-names = "default"; | |
287 | pinctrl-0 = <&i2c1_pins>; | |
288 | clock-frequency = <400000>; | |
289 | ||
290 | tps659038: tps659038@58 { | |
291 | compatible = "ti,tps659038"; | |
292 | reg = <0x58>; | |
293 | ||
294 | tps659038_pmic { | |
295 | compatible = "ti,tps659038-pmic"; | |
296 | ||
297 | regulators { | |
298 | smps123_reg: smps123 { | |
299 | /* VDD_MPU */ | |
300 | regulator-name = "smps123"; | |
301 | regulator-min-microvolt = < 850000>; | |
302 | regulator-max-microvolt = <1250000>; | |
303 | regulator-always-on; | |
304 | regulator-boot-on; | |
305 | }; | |
306 | ||
307 | smps45_reg: smps45 { | |
308 | /* VDD_DSPEVE */ | |
309 | regulator-name = "smps45"; | |
310 | regulator-min-microvolt = < 850000>; | |
311 | regulator-max-microvolt = <1150000>; | |
312 | regulator-always-on; | |
313 | regulator-boot-on; | |
314 | }; | |
315 | ||
316 | smps6_reg: smps6 { | |
317 | /* VDD_GPU - over VDD_SMPS6 */ | |
318 | regulator-name = "smps6"; | |
319 | regulator-min-microvolt = <850000>; | |
320 | regulator-max-microvolt = <1250000>; | |
321 | regulator-always-on; | |
322 | regulator-boot-on; | |
323 | }; | |
324 | ||
325 | smps7_reg: smps7 { | |
326 | /* CORE_VDD */ | |
327 | regulator-name = "smps7"; | |
328 | regulator-min-microvolt = <850000>; | |
329 | regulator-max-microvolt = <1060000>; | |
330 | regulator-always-on; | |
331 | regulator-boot-on; | |
332 | }; | |
333 | ||
334 | smps8_reg: smps8 { | |
335 | /* VDD_IVAHD */ | |
336 | regulator-name = "smps8"; | |
337 | regulator-min-microvolt = < 850000>; | |
338 | regulator-max-microvolt = <1250000>; | |
339 | regulator-always-on; | |
340 | regulator-boot-on; | |
341 | }; | |
342 | ||
343 | smps9_reg: smps9 { | |
344 | /* VDDS1V8 */ | |
345 | regulator-name = "smps9"; | |
346 | regulator-min-microvolt = <1800000>; | |
347 | regulator-max-microvolt = <1800000>; | |
348 | regulator-always-on; | |
349 | regulator-boot-on; | |
350 | }; | |
351 | ||
352 | ldo1_reg: ldo1 { | |
353 | /* LDO1_OUT --> SDIO */ | |
354 | regulator-name = "ldo1"; | |
355 | regulator-min-microvolt = <1800000>; | |
356 | regulator-max-microvolt = <3300000>; | |
357 | regulator-boot-on; | |
358 | }; | |
359 | ||
360 | ldo2_reg: ldo2 { | |
361 | /* VDD_RTCIO */ | |
362 | /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ | |
363 | regulator-name = "ldo2"; | |
364 | regulator-min-microvolt = <3300000>; | |
365 | regulator-max-microvolt = <3300000>; | |
366 | regulator-always-on; | |
367 | regulator-boot-on; | |
368 | }; | |
369 | ||
370 | ldo3_reg: ldo3 { | |
371 | /* VDDA_1V8_PHY */ | |
372 | regulator-name = "ldo3"; | |
373 | regulator-min-microvolt = <1800000>; | |
374 | regulator-max-microvolt = <1800000>; | |
375 | regulator-always-on; | |
376 | regulator-boot-on; | |
377 | }; | |
378 | ||
379 | ldo9_reg: ldo9 { | |
380 | /* VDD_RTC */ | |
381 | regulator-name = "ldo9"; | |
382 | regulator-min-microvolt = <1050000>; | |
383 | regulator-max-microvolt = <1050000>; | |
384 | regulator-always-on; | |
385 | regulator-boot-on; | |
386 | }; | |
387 | ||
388 | ldoln_reg: ldoln { | |
389 | /* VDDA_1V8_PLL */ | |
390 | regulator-name = "ldoln"; | |
391 | regulator-min-microvolt = <1800000>; | |
392 | regulator-max-microvolt = <1800000>; | |
393 | regulator-always-on; | |
394 | regulator-boot-on; | |
395 | }; | |
396 | ||
397 | ldousb_reg: ldousb { | |
398 | /* VDDA_3V_USB: VDDA_USBHS33 */ | |
399 | regulator-name = "ldousb"; | |
400 | regulator-min-microvolt = <3300000>; | |
401 | regulator-max-microvolt = <3300000>; | |
402 | regulator-boot-on; | |
403 | }; | |
404 | }; | |
405 | }; | |
406 | }; | |
407 | ||
408 | pcf_gpio_21: gpio@21 { | |
409 | compatible = "ti,pcf8575"; | |
410 | reg = <0x21>; | |
411 | lines-initial-states = <0x1408>; | |
412 | gpio-controller; | |
413 | #gpio-cells = <2>; | |
414 | interrupt-parent = <&gpio6>; | |
415 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; | |
416 | interrupt-controller; | |
417 | #interrupt-cells = <2>; | |
418 | }; | |
419 | ||
420 | }; | |
421 | ||
422 | &i2c2 { | |
423 | status = "okay"; | |
424 | pinctrl-names = "default"; | |
425 | pinctrl-0 = <&i2c2_pins>; | |
426 | clock-frequency = <400000>; | |
427 | }; | |
428 | ||
429 | &i2c3 { | |
430 | status = "okay"; | |
431 | pinctrl-names = "default"; | |
432 | pinctrl-0 = <&i2c3_pins>; | |
433 | clock-frequency = <400000>; | |
434 | }; | |
435 | ||
436 | &mcspi1 { | |
437 | status = "okay"; | |
438 | pinctrl-names = "default"; | |
439 | pinctrl-0 = <&mcspi1_pins>; | |
440 | }; | |
441 | ||
442 | &mcspi2 { | |
443 | status = "okay"; | |
444 | pinctrl-names = "default"; | |
445 | pinctrl-0 = <&mcspi2_pins>; | |
446 | }; | |
447 | ||
448 | &uart1 { | |
449 | status = "okay"; | |
450 | pinctrl-names = "default"; | |
451 | pinctrl-0 = <&uart1_pins>; | |
452 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
453 | <&dra7_pmx_core 0x3e0>; | |
454 | }; | |
455 | ||
456 | &uart2 { | |
457 | status = "okay"; | |
458 | pinctrl-names = "default"; | |
459 | pinctrl-0 = <&uart2_pins>; | |
460 | }; | |
461 | ||
462 | &uart3 { | |
463 | status = "okay"; | |
464 | pinctrl-names = "default"; | |
465 | pinctrl-0 = <&uart3_pins>; | |
466 | }; | |
467 | ||
468 | &mmc1 { | |
469 | status = "okay"; | |
470 | vmmc-supply = <&ldo1_reg>; | |
471 | bus-width = <4>; | |
472 | }; | |
473 | ||
474 | &mmc2 { | |
475 | status = "okay"; | |
476 | vmmc-supply = <&mmc2_3v3>; | |
477 | bus-width = <8>; | |
478 | }; | |
479 | ||
480 | &cpu0 { | |
481 | cpu0-supply = <&smps123_reg>; | |
482 | }; | |
483 | ||
484 | &qspi { | |
485 | status = "okay"; | |
486 | pinctrl-names = "default"; | |
487 | pinctrl-0 = <&qspi1_pins>; | |
488 | ||
489 | spi-max-frequency = <48000000>; | |
490 | m25p80@0 { | |
f7276c86 | 491 | compatible = "s25fl256s1","spi-flash"; |
e5520e18 M |
492 | spi-max-frequency = <48000000>; |
493 | reg = <0>; | |
494 | spi-tx-bus-width = <1>; | |
495 | spi-rx-bus-width = <4>; | |
496 | spi-cpol; | |
497 | spi-cpha; | |
498 | #address-cells = <1>; | |
499 | #size-cells = <1>; | |
500 | ||
501 | /* MTD partition table. | |
502 | * The ROM checks the first four physical blocks | |
503 | * for a valid file to boot and the flash here is | |
504 | * 64KiB block size. | |
505 | */ | |
506 | partition@0 { | |
507 | label = "QSPI.SPL"; | |
508 | reg = <0x00000000 0x000010000>; | |
509 | }; | |
510 | partition@1 { | |
511 | label = "QSPI.SPL.backup1"; | |
512 | reg = <0x00010000 0x00010000>; | |
513 | }; | |
514 | partition@2 { | |
515 | label = "QSPI.SPL.backup2"; | |
516 | reg = <0x00020000 0x00010000>; | |
517 | }; | |
518 | partition@3 { | |
519 | label = "QSPI.SPL.backup3"; | |
520 | reg = <0x00030000 0x00010000>; | |
521 | }; | |
522 | partition@4 { | |
523 | label = "QSPI.u-boot"; | |
524 | reg = <0x00040000 0x00100000>; | |
525 | }; | |
526 | partition@5 { | |
527 | label = "QSPI.u-boot-spl-os"; | |
528 | reg = <0x00140000 0x00080000>; | |
529 | }; | |
530 | partition@6 { | |
531 | label = "QSPI.u-boot-env"; | |
532 | reg = <0x001c0000 0x00010000>; | |
533 | }; | |
534 | partition@7 { | |
535 | label = "QSPI.u-boot-env.backup1"; | |
536 | reg = <0x001d0000 0x0010000>; | |
537 | }; | |
538 | partition@8 { | |
539 | label = "QSPI.kernel"; | |
540 | reg = <0x001e0000 0x0800000>; | |
541 | }; | |
542 | partition@9 { | |
543 | label = "QSPI.file-system"; | |
544 | reg = <0x009e0000 0x01620000>; | |
545 | }; | |
546 | }; | |
547 | }; | |
548 | ||
549 | &omap_dwc3_1 { | |
550 | extcon = <&extcon_usb1>; | |
551 | }; | |
552 | ||
553 | &omap_dwc3_2 { | |
554 | extcon = <&extcon_usb2>; | |
555 | }; | |
556 | ||
557 | &usb1 { | |
558 | dr_mode = "peripheral"; | |
559 | pinctrl-names = "default"; | |
560 | pinctrl-0 = <&usb1_pins>; | |
561 | }; | |
562 | ||
563 | &usb2 { | |
564 | dr_mode = "host"; | |
565 | pinctrl-names = "default"; | |
566 | pinctrl-0 = <&usb2_pins>; | |
567 | }; | |
568 | ||
569 | &elm { | |
570 | status = "okay"; | |
571 | }; | |
572 | ||
573 | &gpmc { | |
574 | status = "okay"; | |
575 | pinctrl-names = "default"; | |
576 | pinctrl-0 = <&nand_flash_x16>; | |
577 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ | |
578 | nand@0,0 { | |
579 | reg = <0 0 4>; /* device IO registers */ | |
580 | ti,nand-ecc-opt = "bch8"; | |
581 | ti,elm-id = <&elm>; | |
582 | nand-bus-width = <16>; | |
583 | gpmc,device-width = <2>; | |
584 | gpmc,sync-clk-ps = <0>; | |
585 | gpmc,cs-on-ns = <0>; | |
586 | gpmc,cs-rd-off-ns = <80>; | |
587 | gpmc,cs-wr-off-ns = <80>; | |
588 | gpmc,adv-on-ns = <0>; | |
589 | gpmc,adv-rd-off-ns = <60>; | |
590 | gpmc,adv-wr-off-ns = <60>; | |
591 | gpmc,we-on-ns = <10>; | |
592 | gpmc,we-off-ns = <50>; | |
593 | gpmc,oe-on-ns = <4>; | |
594 | gpmc,oe-off-ns = <40>; | |
595 | gpmc,access-ns = <40>; | |
596 | gpmc,wr-access-ns = <80>; | |
597 | gpmc,rd-cycle-ns = <80>; | |
598 | gpmc,wr-cycle-ns = <80>; | |
599 | gpmc,bus-turnaround-ns = <0>; | |
600 | gpmc,cycle2cycle-delay-ns = <0>; | |
601 | gpmc,clk-activation-ns = <0>; | |
602 | gpmc,wait-monitoring-ns = <0>; | |
603 | gpmc,wr-data-mux-bus-ns = <0>; | |
604 | /* MTD partition table */ | |
605 | /* All SPL-* partitions are sized to minimal length | |
606 | * which can be independently programmable. For | |
607 | * NAND flash this is equal to size of erase-block */ | |
608 | #address-cells = <1>; | |
609 | #size-cells = <1>; | |
610 | partition@0 { | |
611 | label = "NAND.SPL"; | |
612 | reg = <0x00000000 0x000020000>; | |
613 | }; | |
614 | partition@1 { | |
615 | label = "NAND.SPL.backup1"; | |
616 | reg = <0x00020000 0x00020000>; | |
617 | }; | |
618 | partition@2 { | |
619 | label = "NAND.SPL.backup2"; | |
620 | reg = <0x00040000 0x00020000>; | |
621 | }; | |
622 | partition@3 { | |
623 | label = "NAND.SPL.backup3"; | |
624 | reg = <0x00060000 0x00020000>; | |
625 | }; | |
626 | partition@4 { | |
627 | label = "NAND.u-boot-spl-os"; | |
628 | reg = <0x00080000 0x00040000>; | |
629 | }; | |
630 | partition@5 { | |
631 | label = "NAND.u-boot"; | |
632 | reg = <0x000c0000 0x00100000>; | |
633 | }; | |
634 | partition@6 { | |
635 | label = "NAND.u-boot-env"; | |
636 | reg = <0x001c0000 0x00020000>; | |
637 | }; | |
638 | partition@7 { | |
639 | label = "NAND.u-boot-env.backup1"; | |
640 | reg = <0x001e0000 0x00020000>; | |
641 | }; | |
642 | partition@8 { | |
643 | label = "NAND.kernel"; | |
644 | reg = <0x00200000 0x00800000>; | |
645 | }; | |
646 | partition@9 { | |
647 | label = "NAND.file-system"; | |
648 | reg = <0x00a00000 0x0f600000>; | |
649 | }; | |
650 | }; | |
651 | }; | |
652 | ||
653 | &usb2_phy1 { | |
654 | phy-supply = <&ldousb_reg>; | |
655 | }; | |
656 | ||
657 | &usb2_phy2 { | |
658 | phy-supply = <&ldousb_reg>; | |
659 | }; | |
660 | ||
661 | &gpio7 { | |
662 | ti,no-reset-on-init; | |
663 | ti,no-idle-on-init; | |
664 | }; | |
665 | ||
666 | &mac { | |
667 | status = "okay"; | |
668 | pinctrl-names = "default", "sleep"; | |
669 | pinctrl-0 = <&cpsw_default>; | |
670 | pinctrl-1 = <&cpsw_sleep>; | |
671 | dual_emac; | |
672 | }; | |
673 | ||
674 | &cpsw_emac0 { | |
675 | phy_id = <&davinci_mdio>, <2>; | |
676 | phy-mode = "rgmii"; | |
677 | dual_emac_res_vlan = <1>; | |
678 | }; | |
679 | ||
680 | &cpsw_emac1 { | |
681 | phy_id = <&davinci_mdio>, <3>; | |
682 | phy-mode = "rgmii"; | |
683 | dual_emac_res_vlan = <2>; | |
684 | }; | |
685 | ||
686 | &davinci_mdio { | |
687 | pinctrl-names = "default", "sleep"; | |
688 | pinctrl-0 = <&davinci_mdio_default>; | |
689 | pinctrl-1 = <&davinci_mdio_sleep>; | |
690 | }; | |
691 | ||
692 | &dcan1 { | |
693 | status = "ok"; | |
694 | pinctrl-names = "default", "sleep", "active"; | |
695 | pinctrl-0 = <&dcan1_pins_sleep>; | |
696 | pinctrl-1 = <&dcan1_pins_sleep>; | |
697 | pinctrl-2 = <&dcan1_pins_default>; | |
698 | }; |