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57cd681b
TR		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
57cd681b
TR		 13#define MAX_SOURCES 400
14
15/ {
7aa1a408
LV		 16 #address-cells = <2>;
17 #size-cells = <2>;
57cd681b
TR		 18
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&crossbar_mpu>;
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 serial6 = &uart7;
35 serial7 = &uart8;
36 serial8 = &uart9;
37 serial9 = &uart10;
38 ethernet0 = &cpsw_emac0;
39 ethernet1 = &cpsw_emac1;
40 d_can0 = &dcan1;
41 d_can1 = &dcan2;
6145ef74 42 spi0 = &qspi;
57cd681b
TR		 43 };
44
45 timer {
46 compatible = "arm,armv7-timer";
47 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
51 interrupt-parent = <&gic>;
52 };
53
54 gic: interrupt-controller@48211000 {
55 compatible = "arm,cortex-a15-gic";
56 interrupt-controller;
57 #interrupt-cells = <3>;
7aa1a408
LV		 58 reg = <0x0 0x48211000 0x0 0x1000>,
59 <0x0 0x48212000 0x0 0x1000>,
60 <0x0 0x48214000 0x0 0x2000>,
61 <0x0 0x48216000 0x0 0x2000>;
57cd681b
TR		 62 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
63 interrupt-parent = <&gic>;
64 };
65
66 wakeupgen: interrupt-controller@48281000 {
67 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
68 interrupt-controller;
69 #interrupt-cells = <3>;
7aa1a408 70 reg = <0x0 0x48281000 0x0 0x1000>;
57cd681b
TR		 71 interrupt-parent = <&gic>;
72 };
73
7aa1a408
LV		 74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: cpu@0 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a15";
81 reg = <0>;
82
83 operating-points = <
84 /* kHz uV */
85 1000000 1060000
86 1176000 1160000
87 >;
88
89 clocks = <&dpll_mpu_ck>;
90 clock-names = "cpu";
91
92 clock-latency = <300000>; /* From omap-cpufreq driver */
93
94 /* cooling options */
95 cooling-min-level = <0>;
96 cooling-max-level = <2>;
97 #cooling-cells = <2>; /* min followed by max */
98 };
99 };
100
57cd681b
TR		 101 /*
102 * The soc node represents the soc top level view. It is used for IPs
103 * that are not memory mapped in the MPU view or for the MPU itself.
104 */
105 soc {
106 compatible = "ti,omap-infra";
107 mpu {
108 compatible = "ti,omap5-mpu";
109 ti,hwmods = "mpu";
110 };
111 };
112
113 /*
114 * XXX: Use a flat representation of the SOC interconnect.
115 * The real OMAP interconnect network is quite complex.
116 * Since it will not bring real advantage to represent that in DT for
117 * the moment, just use a fake OCP bus entry to represent the whole bus
118 * hierarchy.
119 */
120 ocp {
121 compatible = "ti,dra7-l3-noc", "simple-bus";
122 #address-cells = <1>;
123 #size-cells = <1>;
7aa1a408 124 ranges = <0x0 0x0 0x0 0xc0000000>;
57cd681b 125 ti,hwmods = "l3_main_1", "l3_main_2";
7aa1a408
LV		 126 reg = <0x0 0x44000000 0x0 0x1000000>,
127 <0x0 0x45000000 0x0 0x1000>;
57cd681b
TR		 128 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
129 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
130
131 l4_cfg: l4@4a000000 {
132 compatible = "ti,dra7-l4-cfg", "simple-bus";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 ranges = <0 0x4a000000 0x22c000>;
136
137 scm: scm@2000 {
138 compatible = "ti,dra7-scm-core", "simple-bus";
139 reg = <0x2000 0x2000>;
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0 0x2000 0x2000>;
143
144 scm_conf: scm_conf@0 {
7aa1a408 145 compatible = "syscon", "simple-bus";
57cd681b
TR		 146 reg = <0x0 0x1400>;
147 #address-cells = <1>;
148 #size-cells = <1>;
7aa1a408 149 ranges = <0 0x0 0x1400>;
57cd681b 150
7aa1a408
LV		 151 pbias_regulator: pbias_regulator@e00 {
152 compatible = "ti,pbias-dra7", "ti,pbias-omap";
57cd681b
TR		 153 reg = <0xe00 0x4>;
154 syscon = <&scm_conf>;
155 pbias_mmc_reg: pbias_mmc_omap5 {
156 regulator-name = "pbias_mmc_omap5";
157 regulator-min-microvolt = <1800000>;
158 regulator-max-microvolt = <3000000>;
159 };
160 };
161
162 scm_conf_clocks: clocks {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 };
166 };
167
168 dra7_pmx_core: pinmux@1400 {
169 compatible = "ti,dra7-padconf",
170 "pinctrl-single";
7aa1a408 171 reg = <0x1400 0x0468>;
57cd681b
TR		 172 #address-cells = <1>;
173 #size-cells = <0>;
174 #interrupt-cells = <1>;
175 interrupt-controller;
176 pinctrl-single,register-width = <32>;
177 pinctrl-single,function-mask = <0x3fffffff>;
178 };
7aa1a408
LV		 179
180 scm_conf1: scm_conf@1c04 {
181 compatible = "syscon";
182 reg = <0x1c04 0x0020>;
183 };
184
185 scm_conf_pcie: scm_conf@1c24 {
186 compatible = "syscon";
187 reg = <0x1c24 0x0024>;
188 };
189
190 sdma_xbar: dma-router@b78 {
191 compatible = "ti,dra7-dma-crossbar";
192 reg = <0xb78 0xfc>;
193 #dma-cells = <1>;
194 dma-requests = <205>;
195 ti,dma-safe-map = <0>;
196 dma-masters = <&sdma>;
197 };
198
199 edma_xbar: dma-router@c78 {
200 compatible = "ti,dra7-dma-crossbar";
201 reg = <0xc78 0x7c>;
202 #dma-cells = <2>;
203 dma-requests = <204>;
204 ti,dma-safe-map = <0>;
205 dma-masters = <&edma>;
206 };
57cd681b
TR		 207 };
208
209 cm_core_aon: cm_core_aon@5000 {
210 compatible = "ti,dra7-cm-core-aon";
211 reg = <0x5000 0x2000>;
212
213 cm_core_aon_clocks: clocks {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 };
217
218 cm_core_aon_clockdomains: clockdomains {
219 };
220 };
221
222 cm_core: cm_core@8000 {
223 compatible = "ti,dra7-cm-core";
224 reg = <0x8000 0x3000>;
225
226 cm_core_clocks: clocks {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 };
230
231 cm_core_clockdomains: clockdomains {
232 };
233 };
234 };
235
236 l4_wkup: l4@4ae00000 {
237 compatible = "ti,dra7-l4-wkup", "simple-bus";
238 #address-cells = <1>;
239 #size-cells = <1>;
240 ranges = <0 0x4ae00000 0x3f000>;
241
242 counter32k: counter@4000 {
243 compatible = "ti,omap-counter32k";
244 reg = <0x4000 0x40>;
245 ti,hwmods = "counter_32k";
246 };
247
248 prm: prm@6000 {
249 compatible = "ti,dra7-prm";
250 reg = <0x6000 0x3000>;
251 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
252
253 prm_clocks: clocks {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 };
257
258 prm_clockdomains: clockdomains {
259 };
260 };
7aa1a408
LV		 261
262 scm_wkup: scm_conf@c000 {
263 compatible = "syscon";
264 reg = <0xc000 0x1000>;
265 };
57cd681b
TR		 266 };
267
268 axi@0 {
269 compatible = "simple-bus";
270 #size-cells = <1>;
271 #address-cells = <1>;
272 ranges = <0x51000000 0x51000000 0x3000
273 0x0 0x20000000 0x10000000>;
7aa1a408 274 pcie1: pcie@51000000 {
57cd681b
TR		 275 compatible = "ti,dra7-pcie";
276 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
277 reg-names = "rc_dbics", "ti_conf", "config";
278 interrupts = <0 232 0x4>, <0 233 0x4>;
279 #address-cells = <3>;
280 #size-cells = <2>;
281 device_type = "pci";
282 ranges = <0x81000000 0 0 0x03000 0 0x00010000
283 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
284 #interrupt-cells = <1>;
285 num-lanes = <1>;
7aa1a408 286 linux,pci-domain = <0>;
57cd681b
TR		 287 ti,hwmods = "pcie1";
288 phys = <&pcie1_phy>;
289 phy-names = "pcie-phy0";
290 interrupt-map-mask = <0 0 0 7>;
291 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
292 <0 0 0 2 &pcie1_intc 2>,
293 <0 0 0 3 &pcie1_intc 3>,
294 <0 0 0 4 &pcie1_intc 4>;
295 pcie1_intc: interrupt-controller {
296 interrupt-controller;
297 #address-cells = <0>;
298 #interrupt-cells = <1>;
299 };
300 };
301 };
302
303 axi@1 {
304 compatible = "simple-bus";
305 #size-cells = <1>;
306 #address-cells = <1>;
307 ranges = <0x51800000 0x51800000 0x3000
308 0x0 0x30000000 0x10000000>;
309 status = "disabled";
7aa1a408 310 pcie@51800000 {
57cd681b
TR		 311 compatible = "ti,dra7-pcie";
312 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
313 reg-names = "rc_dbics", "ti_conf", "config";
314 interrupts = <0 355 0x4>, <0 356 0x4>;
315 #address-cells = <3>;
316 #size-cells = <2>;
317 device_type = "pci";
318 ranges = <0x81000000 0 0 0x03000 0 0x00010000
319 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
320 #interrupt-cells = <1>;
321 num-lanes = <1>;
7aa1a408 322 linux,pci-domain = <1>;
57cd681b
TR		 323 ti,hwmods = "pcie2";
324 phys = <&pcie2_phy>;
325 phy-names = "pcie-phy0";
326 interrupt-map-mask = <0 0 0 7>;
327 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
328 <0 0 0 2 &pcie2_intc 2>,
329 <0 0 0 3 &pcie2_intc 3>,
330 <0 0 0 4 &pcie2_intc 4>;
331 pcie2_intc: interrupt-controller {
332 interrupt-controller;
333 #address-cells = <0>;
334 #interrupt-cells = <1>;
335 };
336 };
337 };
338
7aa1a408
LV		 339 ocmcram1: ocmcram@40300000 {
340 compatible = "mmio-sram";
341 reg = <0x40300000 0x80000>;
342 ranges = <0x0 0x40300000 0x80000>;
343 #address-cells = <1>;
344 #size-cells = <1>;
345 /*
346 * This is a placeholder for an optional reserved
347 * region for use by secure software. The size
348 * of this region is not known until runtime so it
349 * is set as zero to either be updated to reserve
350 * space or left unchanged to leave all SRAM for use.
351 * On HS parts that that require the reserved region
352 * either the bootloader can update the size to
353 * the required amount or the node can be overridden
354 * from the board dts file for the secure platform.
355 */
356 sram-hs@0 {
357 compatible = "ti,secure-ram";
358 reg = <0x0 0x0>;
359 };
360 };
361
362 /*
363 * NOTE: ocmcram2 and ocmcram3 are not available on all
364 * DRA7xx and AM57xx variants. Confirm availability in
365 * the data manual for the exact part number in use
366 * before enabling these nodes in the board dts file.
367 */
368 ocmcram2: ocmcram@40400000 {
369 status = "disabled";
370 compatible = "mmio-sram";
371 reg = <0x40400000 0x100000>;
372 ranges = <0x0 0x40400000 0x100000>;
373 #address-cells = <1>;
374 #size-cells = <1>;
375 };
376
377 ocmcram3: ocmcram@40500000 {
378 status = "disabled";
379 compatible = "mmio-sram";
380 reg = <0x40500000 0x100000>;
381 ranges = <0x0 0x40500000 0x100000>;
382 #address-cells = <1>;
383 #size-cells = <1>;
384 };
385
57cd681b
TR		 386 bandgap: bandgap@4a0021e0 {
387 reg = <0x4a0021e0 0xc
388 0x4a00232c 0xc
389 0x4a002380 0x2c
390 0x4a0023C0 0x3c
391 0x4a002564 0x8
392 0x4a002574 0x50>;
393 compatible = "ti,dra752-bandgap";
394 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
395 #thermal-sensor-cells = <1>;
396 };
397
7aa1a408 398 dsp1_system: dsp_system@40d00000 {
57cd681b 399 compatible = "syscon";
7aa1a408 400 reg = <0x40d00000 0x100>;
57cd681b
TR		 401 };
402
403 sdma: dma-controller@4a056000 {
404 compatible = "ti,omap4430-sdma";
405 reg = <0x4a056000 0x1000>;
406 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
410 #dma-cells = <1>;
411 dma-channels = <32>;
412 dma-requests = <127>;
413 };
414
7aa1a408
LV		 415 edma: edma@43300000 {
416 compatible = "ti,edma3-tpcc";
417 ti,hwmods = "tpcc";
418 reg = <0x43300000 0x100000>;
419 reg-names = "edma3_cc";
420 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
423 interrupt-names = "edma3_ccint", "edma3_mperr",
424 "edma3_ccerrint";
425 dma-requests = <64>;
426 #dma-cells = <2>;
427
428 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
429
430 /*
431 * memcpy is disabled, can be enabled with:
432 * ti,edma-memcpy-channels = <20 21>;
433 * for example. Note that these channels need to be
434 * masked in the xbar as well.
435 */
436 };
437
438 edma_tptc0: tptc@43400000 {
439 compatible = "ti,edma3-tptc";
440 ti,hwmods = "tptc0";
441 reg = <0x43400000 0x100000>;
442 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-names = "edma3_tcerrint";
444 };
445
446 edma_tptc1: tptc@43500000 {
447 compatible = "ti,edma3-tptc";
448 ti,hwmods = "tptc1";
449 reg = <0x43500000 0x100000>;
450 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
451 interrupt-names = "edma3_tcerrint";
452 };
453
57cd681b
TR		 454 gpio1: gpio@4ae10000 {
455 compatible = "ti,omap4-gpio";
456 reg = <0x4ae10000 0x200>;
457 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
458 ti,hwmods = "gpio1";
459 gpio-controller;
460 #gpio-cells = <2>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
463 };
464
465 gpio2: gpio@48055000 {
466 compatible = "ti,omap4-gpio";
467 reg = <0x48055000 0x200>;
468 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
469 ti,hwmods = "gpio2";
470 gpio-controller;
471 #gpio-cells = <2>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 };
475
476 gpio3: gpio@48057000 {
477 compatible = "ti,omap4-gpio";
478 reg = <0x48057000 0x200>;
479 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
480 ti,hwmods = "gpio3";
481 gpio-controller;
482 #gpio-cells = <2>;
483 interrupt-controller;
484 #interrupt-cells = <2>;
485 };
486
487 gpio4: gpio@48059000 {
488 compatible = "ti,omap4-gpio";
489 reg = <0x48059000 0x200>;
490 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
491 ti,hwmods = "gpio4";
492 gpio-controller;
493 #gpio-cells = <2>;
494 interrupt-controller;
495 #interrupt-cells = <2>;
496 };
497
498 gpio5: gpio@4805b000 {
499 compatible = "ti,omap4-gpio";
500 reg = <0x4805b000 0x200>;
501 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
502 ti,hwmods = "gpio5";
503 gpio-controller;
504 #gpio-cells = <2>;
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 };
508
509 gpio6: gpio@4805d000 {
510 compatible = "ti,omap4-gpio";
511 reg = <0x4805d000 0x200>;
512 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
513 ti,hwmods = "gpio6";
514 gpio-controller;
515 #gpio-cells = <2>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
518 };
519
520 gpio7: gpio@48051000 {
521 compatible = "ti,omap4-gpio";
522 reg = <0x48051000 0x200>;
523 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
524 ti,hwmods = "gpio7";
525 gpio-controller;
526 #gpio-cells = <2>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
529 };
530
531 gpio8: gpio@48053000 {
532 compatible = "ti,omap4-gpio";
533 reg = <0x48053000 0x200>;
534 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
535 ti,hwmods = "gpio8";
536 gpio-controller;
537 #gpio-cells = <2>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
540 };
541
542 uart1: serial@4806a000 {
7aa1a408 543 compatible = "ti,dra742-uart", "ti,omap4-uart";
57cd681b 544 reg = <0x4806a000 0x100>;
85cf0e62 545 reg-shift = <2>;
57cd681b
TR		 546 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
547 ti,hwmods = "uart1";
548 clock-frequency = <48000000>;
549 status = "disabled";
7aa1a408 550 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
57cd681b
TR		 551 dma-names = "tx", "rx";
552 };
553
554 uart2: serial@4806c000 {
7aa1a408 555 compatible = "ti,dra742-uart", "ti,omap4-uart";
57cd681b 556 reg = <0x4806c000 0x100>;
85cf0e62 557 reg-shift = <2>;
57cd681b
TR		 558 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
559 ti,hwmods = "uart2";
560 clock-frequency = <48000000>;
561 status = "disabled";
7aa1a408 562 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
57cd681b
TR		 563 dma-names = "tx", "rx";
564 };
565
566 uart3: serial@48020000 {
7aa1a408 567 compatible = "ti,dra742-uart", "ti,omap4-uart";
57cd681b 568 reg = <0x48020000 0x100>;
85cf0e62 569 reg-shift = <2>;
57cd681b
TR		 570 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
571 ti,hwmods = "uart3";
572 clock-frequency = <48000000>;
573 status = "disabled";
7aa1a408 574 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
57cd681b
TR		 575 dma-names = "tx", "rx";
576 };
577
578 uart4: serial@4806e000 {
7aa1a408 579 compatible = "ti,dra742-uart", "ti,omap4-uart";
57cd681b 580 reg = <0x4806e000 0x100>;
85cf0e62 581 reg-shift = <2>;
57cd681b
TR		 582 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
583 ti,hwmods = "uart4";
584 clock-frequency = <48000000>;
585 status = "disabled";
7aa1a408 586 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
57cd681b
TR		 587 dma-names = "tx", "rx";
588 };
589
590 uart5: serial@48066000 {
7aa1a408 591 compatible = "ti,dra742-uart", "ti,omap4-uart";
57cd681b 592 reg = <0x48066000 0x100>;
85cf0e62 593 reg-shift = <2>;
57cd681b
TR		 594 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
595 ti,hwmods = "uart5";
596 clock-frequency = <48000000>;
597 status = "disabled";
7aa1a408 598 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
57cd681b
TR		 599 dma-names = "tx", "rx";
600 };
601
602 uart6: serial@48068000 {
7aa1a408 603 compatible = "ti,dra742-uart", "ti,omap4-uart";
57cd681b 604 reg = <0x48068000 0x100>;
85cf0e62 605 reg-shift = <2>;
57cd681b
TR		 606 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
607 ti,hwmods = "uart6";
608 clock-frequency = <48000000>;
609 status = "disabled";
7aa1a408 610 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
57cd681b
TR		 611 dma-names = "tx", "rx";
612 };
613
614 uart7: serial@48420000 {
7aa1a408 615 compatible = "ti,dra742-uart", "ti,omap4-uart";
57cd681b 616 reg = <0x48420000 0x100>;
85cf0e62 617 reg-shift = <2>;
57cd681b
TR		 618 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
619 ti,hwmods = "uart7";
620 clock-frequency = <48000000>;
621 status = "disabled";
622 };
623
624 uart8: serial@48422000 {
7aa1a408 625 compatible = "ti,dra742-uart", "ti,omap4-uart";
57cd681b 626 reg = <0x48422000 0x100>;
85cf0e62 627 reg-shift = <2>;
57cd681b
TR		 628 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
629 ti,hwmods = "uart8";
630 clock-frequency = <48000000>;
631 status = "disabled";
632 };
633
634 uart9: serial@48424000 {
7aa1a408 635 compatible = "ti,dra742-uart", "ti,omap4-uart";
57cd681b 636 reg = <0x48424000 0x100>;
85cf0e62 637 reg-shift = <2>;
57cd681b
TR		 638 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
639 ti,hwmods = "uart9";
640 clock-frequency = <48000000>;
641 status = "disabled";
642 };
643
644 uart10: serial@4ae2b000 {
7aa1a408 645 compatible = "ti,dra742-uart", "ti,omap4-uart";
57cd681b 646 reg = <0x4ae2b000 0x100>;
85cf0e62 647 reg-shift = <2>;
57cd681b
TR		 648 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
649 ti,hwmods = "uart10";
650 clock-frequency = <48000000>;
651 status = "disabled";
652 };
653
654 mailbox1: mailbox@4a0f4000 {
655 compatible = "ti,omap4-mailbox";
656 reg = <0x4a0f4000 0x200>;
657 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
660 ti,hwmods = "mailbox1";
661 #mbox-cells = <1>;
662 ti,mbox-num-users = <3>;
663 ti,mbox-num-fifos = <8>;
664 status = "disabled";
665 };
666
667 mailbox2: mailbox@4883a000 {
668 compatible = "ti,omap4-mailbox";
669 reg = <0x4883a000 0x200>;
670 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
674 ti,hwmods = "mailbox2";
675 #mbox-cells = <1>;
676 ti,mbox-num-users = <4>;
677 ti,mbox-num-fifos = <12>;
678 status = "disabled";
679 };
680
681 mailbox3: mailbox@4883c000 {
682 compatible = "ti,omap4-mailbox";
683 reg = <0x4883c000 0x200>;
684 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
688 ti,hwmods = "mailbox3";
689 #mbox-cells = <1>;
690 ti,mbox-num-users = <4>;
691 ti,mbox-num-fifos = <12>;
692 status = "disabled";
693 };
694
695 mailbox4: mailbox@4883e000 {
696 compatible = "ti,omap4-mailbox";
697 reg = <0x4883e000 0x200>;
698 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
702 ti,hwmods = "mailbox4";
703 #mbox-cells = <1>;
704 ti,mbox-num-users = <4>;
705 ti,mbox-num-fifos = <12>;
706 status = "disabled";
707 };
708
709 mailbox5: mailbox@48840000 {
710 compatible = "ti,omap4-mailbox";
711 reg = <0x48840000 0x200>;
712 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
716 ti,hwmods = "mailbox5";
717 #mbox-cells = <1>;
718 ti,mbox-num-users = <4>;
719 ti,mbox-num-fifos = <12>;
720 status = "disabled";
721 };
722
723 mailbox6: mailbox@48842000 {
724 compatible = "ti,omap4-mailbox";
725 reg = <0x48842000 0x200>;
726 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
730 ti,hwmods = "mailbox6";
731 #mbox-cells = <1>;
732 ti,mbox-num-users = <4>;
733 ti,mbox-num-fifos = <12>;
734 status = "disabled";
735 };
736
737 mailbox7: mailbox@48844000 {
738 compatible = "ti,omap4-mailbox";
739 reg = <0x48844000 0x200>;
740 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
744 ti,hwmods = "mailbox7";
745 #mbox-cells = <1>;
746 ti,mbox-num-users = <4>;
747 ti,mbox-num-fifos = <12>;
748 status = "disabled";
749 };
750
751 mailbox8: mailbox@48846000 {
752 compatible = "ti,omap4-mailbox";
753 reg = <0x48846000 0x200>;
754 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
758 ti,hwmods = "mailbox8";
759 #mbox-cells = <1>;
760 ti,mbox-num-users = <4>;
761 ti,mbox-num-fifos = <12>;
762 status = "disabled";
763 };
764
765 mailbox9: mailbox@4885e000 {
766 compatible = "ti,omap4-mailbox";
767 reg = <0x4885e000 0x200>;
768 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
772 ti,hwmods = "mailbox9";
773 #mbox-cells = <1>;
774 ti,mbox-num-users = <4>;
775 ti,mbox-num-fifos = <12>;
776 status = "disabled";
777 };
778
779 mailbox10: mailbox@48860000 {
780 compatible = "ti,omap4-mailbox";
781 reg = <0x48860000 0x200>;
782 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
786 ti,hwmods = "mailbox10";
787 #mbox-cells = <1>;
788 ti,mbox-num-users = <4>;
789 ti,mbox-num-fifos = <12>;
790 status = "disabled";
791 };
792
793 mailbox11: mailbox@48862000 {
794 compatible = "ti,omap4-mailbox";
795 reg = <0x48862000 0x200>;
796 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
797 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
798 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
799 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
800 ti,hwmods = "mailbox11";
801 #mbox-cells = <1>;
802 ti,mbox-num-users = <4>;
803 ti,mbox-num-fifos = <12>;
804 status = "disabled";
805 };
806
807 mailbox12: mailbox@48864000 {
808 compatible = "ti,omap4-mailbox";
809 reg = <0x48864000 0x200>;
810 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
814 ti,hwmods = "mailbox12";
815 #mbox-cells = <1>;
816 ti,mbox-num-users = <4>;
817 ti,mbox-num-fifos = <12>;
818 status = "disabled";
819 };
820
821 mailbox13: mailbox@48802000 {
822 compatible = "ti,omap4-mailbox";
823 reg = <0x48802000 0x200>;
824 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
826 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
828 ti,hwmods = "mailbox13";
829 #mbox-cells = <1>;
830 ti,mbox-num-users = <4>;
831 ti,mbox-num-fifos = <12>;
832 status = "disabled";
833 };
834
835 timer1: timer@4ae18000 {
836 compatible = "ti,omap5430-timer";
837 reg = <0x4ae18000 0x80>;
838 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
839 ti,hwmods = "timer1";
840 ti,timer-alwon;
841 };
842
843 timer2: timer@48032000 {
844 compatible = "ti,omap5430-timer";
845 reg = <0x48032000 0x80>;
846 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
847 ti,hwmods = "timer2";
848 };
849
850 timer3: timer@48034000 {
851 compatible = "ti,omap5430-timer";
852 reg = <0x48034000 0x80>;
853 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
854 ti,hwmods = "timer3";
855 };
856
857 timer4: timer@48036000 {
858 compatible = "ti,omap5430-timer";
859 reg = <0x48036000 0x80>;
860 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
861 ti,hwmods = "timer4";
862 };
863
864 timer5: timer@48820000 {
865 compatible = "ti,omap5430-timer";
866 reg = <0x48820000 0x80>;
867 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
868 ti,hwmods = "timer5";
869 };
870
871 timer6: timer@48822000 {
872 compatible = "ti,omap5430-timer";
873 reg = <0x48822000 0x80>;
874 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
875 ti,hwmods = "timer6";
876 };
877
878 timer7: timer@48824000 {
879 compatible = "ti,omap5430-timer";
880 reg = <0x48824000 0x80>;
881 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
882 ti,hwmods = "timer7";
883 };
884
885 timer8: timer@48826000 {
886 compatible = "ti,omap5430-timer";
887 reg = <0x48826000 0x80>;
888 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
889 ti,hwmods = "timer8";
890 };
891
892 timer9: timer@4803e000 {
893 compatible = "ti,omap5430-timer";
894 reg = <0x4803e000 0x80>;
895 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
896 ti,hwmods = "timer9";
897 };
898
899 timer10: timer@48086000 {
900 compatible = "ti,omap5430-timer";
901 reg = <0x48086000 0x80>;
902 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
903 ti,hwmods = "timer10";
904 };
905
906 timer11: timer@48088000 {
907 compatible = "ti,omap5430-timer";
908 reg = <0x48088000 0x80>;
909 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
910 ti,hwmods = "timer11";
911 };
912
7aa1a408
LV		 913 timer12: timer@4ae20000 {
914 compatible = "ti,omap5430-timer";
915 reg = <0x4ae20000 0x80>;
916 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
917 ti,hwmods = "timer12";
918 ti,timer-alwon;
919 ti,timer-secure;
920 };
921
57cd681b
TR		 922 timer13: timer@48828000 {
923 compatible = "ti,omap5430-timer";
924 reg = <0x48828000 0x80>;
925 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
926 ti,hwmods = "timer13";
57cd681b
TR		 927 };
928
929 timer14: timer@4882a000 {
930 compatible = "ti,omap5430-timer";
931 reg = <0x4882a000 0x80>;
932 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
933 ti,hwmods = "timer14";
57cd681b
TR		 934 };
935
936 timer15: timer@4882c000 {
937 compatible = "ti,omap5430-timer";
938 reg = <0x4882c000 0x80>;
939 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
940 ti,hwmods = "timer15";
57cd681b
TR		 941 };
942
943 timer16: timer@4882e000 {
944 compatible = "ti,omap5430-timer";
945 reg = <0x4882e000 0x80>;
946 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
947 ti,hwmods = "timer16";
57cd681b
TR		 948 };
949
950 wdt2: wdt@4ae14000 {
951 compatible = "ti,omap3-wdt";
952 reg = <0x4ae14000 0x80>;
953 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
954 ti,hwmods = "wd_timer2";
955 };
956
957 hwspinlock: spinlock@4a0f6000 {
958 compatible = "ti,omap4-hwspinlock";
959 reg = <0x4a0f6000 0x1000>;
960 ti,hwmods = "spinlock";
961 #hwlock-cells = <1>;
962 };
963
964 dmm@4e000000 {
965 compatible = "ti,omap5-dmm";
966 reg = <0x4e000000 0x800>;
967 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
968 ti,hwmods = "dmm";
969 };
970
971 i2c1: i2c@48070000 {
972 compatible = "ti,omap4-i2c";
973 reg = <0x48070000 0x100>;
974 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
975 #address-cells = <1>;
976 #size-cells = <0>;
977 ti,hwmods = "i2c1";
978 status = "disabled";
979 };
980
981 i2c2: i2c@48072000 {
982 compatible = "ti,omap4-i2c";
983 reg = <0x48072000 0x100>;
984 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
985 #address-cells = <1>;
986 #size-cells = <0>;
987 ti,hwmods = "i2c2";
988 status = "disabled";
989 };
990
991 i2c3: i2c@48060000 {
992 compatible = "ti,omap4-i2c";
993 reg = <0x48060000 0x100>;
994 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
995 #address-cells = <1>;
996 #size-cells = <0>;
997 ti,hwmods = "i2c3";
998 status = "disabled";
999 };
1000
1001 i2c4: i2c@4807a000 {
1002 compatible = "ti,omap4-i2c";
1003 reg = <0x4807a000 0x100>;
1004 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1007 ti,hwmods = "i2c4";
1008 status = "disabled";
1009 };
1010
1011 i2c5: i2c@4807c000 {
1012 compatible = "ti,omap4-i2c";
1013 reg = <0x4807c000 0x100>;
1014 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 ti,hwmods = "i2c5";
1018 status = "disabled";
1019 };
1020
1021 mmc1: mmc@4809c000 {
1022 compatible = "ti,omap4-hsmmc";
1023 reg = <0x4809c000 0x400>;
1024 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1025 ti,hwmods = "mmc1";
1026 ti,dual-volt;
1027 ti,needs-special-reset;
7aa1a408 1028 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
57cd681b
TR		 1029 dma-names = "tx", "rx";
1030 status = "disabled";
1031 pbias-supply = <&pbias_mmc_reg>;
1032 };
1033
1034 mmc2: mmc@480b4000 {
1035 compatible = "ti,omap4-hsmmc";
1036 reg = <0x480b4000 0x400>;
1037 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1038 ti,hwmods = "mmc2";
1039 ti,needs-special-reset;
7aa1a408 1040 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
57cd681b
TR		 1041 dma-names = "tx", "rx";
1042 status = "disabled";
1043 };
1044
1045 mmc3: mmc@480ad000 {
1046 compatible = "ti,omap4-hsmmc";
1047 reg = <0x480ad000 0x400>;
1048 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1049 ti,hwmods = "mmc3";
1050 ti,needs-special-reset;
7aa1a408 1051 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
57cd681b
TR		 1052 dma-names = "tx", "rx";
1053 status = "disabled";
1054 };
1055
1056 mmc4: mmc@480d1000 {
1057 compatible = "ti,omap4-hsmmc";
1058 reg = <0x480d1000 0x400>;
1059 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1060 ti,hwmods = "mmc4";
1061 ti,needs-special-reset;
7aa1a408 1062 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
57cd681b
TR		 1063 dma-names = "tx", "rx";
1064 status = "disabled";
1065 };
1066
7aa1a408
LV		 1067 mmu0_dsp1: mmu@40d01000 {
1068 compatible = "ti,dra7-dsp-iommu";
1069 reg = <0x40d01000 0x100>;
1070 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1071 ti,hwmods = "mmu0_dsp1";
1072 #iommu-cells = <0>;
1073 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1074 status = "disabled";
1075 };
1076
1077 mmu1_dsp1: mmu@40d02000 {
1078 compatible = "ti,dra7-dsp-iommu";
1079 reg = <0x40d02000 0x100>;
1080 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1081 ti,hwmods = "mmu1_dsp1";
1082 #iommu-cells = <0>;
1083 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1084 status = "disabled";
1085 };
1086
1087 mmu_ipu1: mmu@58882000 {
1088 compatible = "ti,dra7-iommu";
1089 reg = <0x58882000 0x100>;
1090 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1091 ti,hwmods = "mmu_ipu1";
1092 #iommu-cells = <0>;
1093 ti,iommu-bus-err-back;
1094 status = "disabled";
1095 };
1096
1097 mmu_ipu2: mmu@55082000 {
1098 compatible = "ti,dra7-iommu";
1099 reg = <0x55082000 0x100>;
1100 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1101 ti,hwmods = "mmu_ipu2";
1102 #iommu-cells = <0>;
1103 ti,iommu-bus-err-back;
1104 status = "disabled";
1105 };
1106
57cd681b
TR		 1107 abb_mpu: regulator-abb-mpu {
1108 compatible = "ti,abb-v3";
1109 regulator-name = "abb_mpu";
1110 #address-cells = <0>;
1111 #size-cells = <0>;
1112 clocks = <&sys_clkin1>;
1113 ti,settling-time = <50>;
1114 ti,clock-cycles = <16>;
1115
1116 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1117 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1118 <0x4ae0c158 0x4>;
1119 reg-names = "setup-address", "control-address",
1120 "int-address", "efuse-address",
1121 "ldo-address";
1122 ti,tranxdone-status-mask = <0x80>;
1123 /* LDOVBBMPU_FBB_MUX_CTRL */
1124 ti,ldovbb-override-mask = <0x400>;
1125 /* LDOVBBMPU_FBB_VSET_OUT */
1126 ti,ldovbb-vset-mask = <0x1F>;
1127
1128 /*
1129 * NOTE: only FBB mode used but actual vset will
1130 * determine final biasing
1131 */
1132 ti,abb_info = <
1133 /*uV ABB efuse rbb_m fbb_m vset_m*/
1134 1060000 0 0x0 0 0x02000000 0x01F00000
1135 1160000 0 0x4 0 0x02000000 0x01F00000
1136 1210000 0 0x8 0 0x02000000 0x01F00000
1137 >;
1138 };
1139
1140 abb_ivahd: regulator-abb-ivahd {
1141 compatible = "ti,abb-v3";
1142 regulator-name = "abb_ivahd";
1143 #address-cells = <0>;
1144 #size-cells = <0>;
1145 clocks = <&sys_clkin1>;
1146 ti,settling-time = <50>;
1147 ti,clock-cycles = <16>;
1148
1149 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1150 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1151 <0x4a002470 0x4>;
1152 reg-names = "setup-address", "control-address",
1153 "int-address", "efuse-address",
1154 "ldo-address";
1155 ti,tranxdone-status-mask = <0x40000000>;
1156 /* LDOVBBIVA_FBB_MUX_CTRL */
1157 ti,ldovbb-override-mask = <0x400>;
1158 /* LDOVBBIVA_FBB_VSET_OUT */
1159 ti,ldovbb-vset-mask = <0x1F>;
1160
1161 /*
1162 * NOTE: only FBB mode used but actual vset will
1163 * determine final biasing
1164 */
1165 ti,abb_info = <
1166 /*uV ABB efuse rbb_m fbb_m vset_m*/
1167 1055000 0 0x0 0 0x02000000 0x01F00000
1168 1150000 0 0x4 0 0x02000000 0x01F00000
1169 1250000 0 0x8 0 0x02000000 0x01F00000
1170 >;
1171 };
1172
1173 abb_dspeve: regulator-abb-dspeve {
1174 compatible = "ti,abb-v3";
1175 regulator-name = "abb_dspeve";
1176 #address-cells = <0>;
1177 #size-cells = <0>;
1178 clocks = <&sys_clkin1>;
1179 ti,settling-time = <50>;
1180 ti,clock-cycles = <16>;
1181
1182 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1183 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1184 <0x4a00246c 0x4>;
1185 reg-names = "setup-address", "control-address",
1186 "int-address", "efuse-address",
1187 "ldo-address";
1188 ti,tranxdone-status-mask = <0x20000000>;
1189 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1190 ti,ldovbb-override-mask = <0x400>;
1191 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1192 ti,ldovbb-vset-mask = <0x1F>;
1193
1194 /*
1195 * NOTE: only FBB mode used but actual vset will
1196 * determine final biasing
1197 */
1198 ti,abb_info = <
1199 /*uV ABB efuse rbb_m fbb_m vset_m*/
1200 1055000 0 0x0 0 0x02000000 0x01F00000
1201 1150000 0 0x4 0 0x02000000 0x01F00000
1202 1250000 0 0x8 0 0x02000000 0x01F00000
1203 >;
1204 };
1205
1206 abb_gpu: regulator-abb-gpu {
1207 compatible = "ti,abb-v3";
1208 regulator-name = "abb_gpu";
1209 #address-cells = <0>;
1210 #size-cells = <0>;
1211 clocks = <&sys_clkin1>;
1212 ti,settling-time = <50>;
1213 ti,clock-cycles = <16>;
1214
1215 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1216 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1217 <0x4ae0c154 0x4>;
1218 reg-names = "setup-address", "control-address",
1219 "int-address", "efuse-address",
1220 "ldo-address";
1221 ti,tranxdone-status-mask = <0x10000000>;
1222 /* LDOVBBGPU_FBB_MUX_CTRL */
1223 ti,ldovbb-override-mask = <0x400>;
1224 /* LDOVBBGPU_FBB_VSET_OUT */
1225 ti,ldovbb-vset-mask = <0x1F>;
1226
1227 /*
1228 * NOTE: only FBB mode used but actual vset will
1229 * determine final biasing
1230 */
1231 ti,abb_info = <
1232 /*uV ABB efuse rbb_m fbb_m vset_m*/
1233 1090000 0 0x0 0 0x02000000 0x01F00000
1234 1210000 0 0x4 0 0x02000000 0x01F00000
1235 1280000 0 0x8 0 0x02000000 0x01F00000
1236 >;
1237 };
1238
1239 mcspi1: spi@48098000 {
1240 compatible = "ti,omap4-mcspi";
1241 reg = <0x48098000 0x200>;
1242 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1243 #address-cells = <1>;
1244 #size-cells = <0>;
1245 ti,hwmods = "mcspi1";
1246 ti,spi-num-cs = <4>;
7aa1a408
LV		 1247 dmas = <&sdma_xbar 35>,
1248 <&sdma_xbar 36>,
1249 <&sdma_xbar 37>,
1250 <&sdma_xbar 38>,
1251 <&sdma_xbar 39>,
1252 <&sdma_xbar 40>,
1253 <&sdma_xbar 41>,
1254 <&sdma_xbar 42>;
57cd681b
TR		 1255 dma-names = "tx0", "rx0", "tx1", "rx1",
1256 "tx2", "rx2", "tx3", "rx3";
1257 status = "disabled";
1258 };
1259
1260 mcspi2: spi@4809a000 {
1261 compatible = "ti,omap4-mcspi";
1262 reg = <0x4809a000 0x200>;
1263 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1266 ti,hwmods = "mcspi2";
1267 ti,spi-num-cs = <2>;
7aa1a408
LV		 1268 dmas = <&sdma_xbar 43>,
1269 <&sdma_xbar 44>,
1270 <&sdma_xbar 45>,
1271 <&sdma_xbar 46>;
57cd681b
TR		 1272 dma-names = "tx0", "rx0", "tx1", "rx1";
1273 status = "disabled";
1274 };
1275
1276 mcspi3: spi@480b8000 {
1277 compatible = "ti,omap4-mcspi";
1278 reg = <0x480b8000 0x200>;
1279 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1282 ti,hwmods = "mcspi3";
1283 ti,spi-num-cs = <2>;
7aa1a408 1284 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
57cd681b
TR		 1285 dma-names = "tx0", "rx0";
1286 status = "disabled";
1287 };
1288
1289 mcspi4: spi@480ba000 {
1290 compatible = "ti,omap4-mcspi";
1291 reg = <0x480ba000 0x200>;
1292 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1295 ti,hwmods = "mcspi4";
1296 ti,spi-num-cs = <1>;
7aa1a408 1297 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
57cd681b
TR		 1298 dma-names = "tx0", "rx0";
1299 status = "disabled";
1300 };
1301
1302 qspi: qspi@4b300000 {
1303 compatible = "ti,dra7xxx-qspi";
830aba2c 1304 reg = <0x4b300000 0x100>,
7aa1a408
LV		 1305 <0x5c000000 0x4000000>;
1306 reg-names = "qspi_base", "qspi_mmap";
1307 syscon-chipselects = <&scm_conf 0x558>;
57cd681b
TR		 1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310 ti,hwmods = "qspi";
1311 clocks = <&qspi_gfclk_div>;
1312 clock-names = "fck";
1313 num-cs = <4>;
1314 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1315 status = "disabled";
1316 };
1317
57cd681b
TR		 1318 /* OCP2SCP3 */
1319 ocp2scp@4a090000 {
1320 compatible = "ti,omap-ocp2scp";
1321 #address-cells = <1>;
1322 #size-cells = <1>;
1323 ranges;
1324 reg = <0x4a090000 0x20>;
1325 ti,hwmods = "ocp2scp3";
1326 sata_phy: phy@4A096000 {
1327 compatible = "ti,phy-pipe3-sata";
1328 reg = <0x4A096000 0x80>, /* phy_rx */
1329 <0x4A096400 0x64>, /* phy_tx */
1330 <0x4A096800 0x40>; /* pll_ctrl */
1331 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
7aa1a408 1332 syscon-phy-power = <&scm_conf 0x374>;
57cd681b
TR		 1333 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1334 clock-names = "sysclk", "refclk";
7aa1a408 1335 syscon-pllreset = <&scm_conf 0x3fc>;
57cd681b
TR		 1336 #phy-cells = <0>;
1337 };
1338
1339 pcie1_phy: pciephy@4a094000 {
1340 compatible = "ti,phy-pipe3-pcie";
1341 reg = <0x4a094000 0x80>, /* phy_rx */
1342 <0x4a094400 0x64>; /* phy_tx */
1343 reg-names = "phy_rx", "phy_tx";
7aa1a408
LV		 1344 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1345 syscon-pcs = <&scm_conf_pcie 0x10>;
57cd681b
TR		 1346 clocks = <&dpll_pcie_ref_ck>,
1347 <&dpll_pcie_ref_m2ldo_ck>,
1348 <&optfclk_pciephy1_32khz>,
1349 <&optfclk_pciephy1_clk>,
1350 <&optfclk_pciephy1_div_clk>,
7aa1a408
LV		 1351 <&optfclk_pciephy_div>,
1352 <&sys_clkin1>;
57cd681b
TR		 1353 clock-names = "dpll_ref", "dpll_ref_m2",
1354 "wkupclk", "refclk",
7aa1a408 1355 "div-clk", "phy-div", "sysclk";
57cd681b
TR		 1356 #phy-cells = <0>;
1357 };
1358
1359 pcie2_phy: pciephy@4a095000 {
1360 compatible = "ti,phy-pipe3-pcie";
1361 reg = <0x4a095000 0x80>, /* phy_rx */
1362 <0x4a095400 0x64>; /* phy_tx */
1363 reg-names = "phy_rx", "phy_tx";
7aa1a408
LV		 1364 syscon-phy-power = <&scm_conf_pcie 0x20>;
1365 syscon-pcs = <&scm_conf_pcie 0x10>;
57cd681b
TR		 1366 clocks = <&dpll_pcie_ref_ck>,
1367 <&dpll_pcie_ref_m2ldo_ck>,
1368 <&optfclk_pciephy2_32khz>,
1369 <&optfclk_pciephy2_clk>,
1370 <&optfclk_pciephy2_div_clk>,
7aa1a408
LV		 1371 <&optfclk_pciephy_div>,
1372 <&sys_clkin1>;
57cd681b
TR		 1373 clock-names = "dpll_ref", "dpll_ref_m2",
1374 "wkupclk", "refclk",
7aa1a408 1375 "div-clk", "phy-div", "sysclk";
57cd681b
TR		 1376 #phy-cells = <0>;
1377 status = "disabled";
1378 };
1379 };
1380
1381 sata: sata@4a141100 {
1382 compatible = "snps,dwc-ahci";
1383 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1384 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1385 phys = <&sata_phy>;
1386 phy-names = "sata-phy";
1387 clocks = <&sata_ref_clk>;
1388 ti,hwmods = "sata";
1389 };
1390
57cd681b
TR		 1391 rtc: rtc@48838000 {
1392 compatible = "ti,am3352-rtc";
1393 reg = <0x48838000 0x100>;
1394 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1396 ti,hwmods = "rtcss";
1397 clocks = <&sys_32k_ck>;
1398 };
1399
57cd681b
TR		 1400 /* OCP2SCP1 */
1401 ocp2scp@4a080000 {
1402 compatible = "ti,omap-ocp2scp";
1403 #address-cells = <1>;
1404 #size-cells = <1>;
1405 ranges;
1406 reg = <0x4a080000 0x20>;
1407 ti,hwmods = "ocp2scp1";
1408
1409 usb2_phy1: phy@4a084000 {
7aa1a408 1410 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
57cd681b 1411 reg = <0x4a084000 0x400>;
7aa1a408 1412 syscon-phy-power = <&scm_conf 0x300>;
57cd681b
TR		 1413 clocks = <&usb_phy1_always_on_clk32k>,
1414 <&usb_otg_ss1_refclk960m>;
1415 clock-names = "wkupclk",
1416 "refclk";
1417 #phy-cells = <0>;
1418 };
1419
1420 usb2_phy2: phy@4a085000 {
7aa1a408
LV		 1421 compatible = "ti,dra7x-usb2-phy2",
1422 "ti,omap-usb2";
57cd681b 1423 reg = <0x4a085000 0x400>;
7aa1a408 1424 syscon-phy-power = <&scm_conf 0xe74>;
57cd681b
TR		 1425 clocks = <&usb_phy2_always_on_clk32k>,
1426 <&usb_otg_ss2_refclk960m>;
1427 clock-names = "wkupclk",
1428 "refclk";
1429 #phy-cells = <0>;
1430 };
1431
1432 usb3_phy1: phy@4a084400 {
1433 compatible = "ti,omap-usb3";
1434 reg = <0x4a084400 0x80>,
1435 <0x4a084800 0x64>,
1436 <0x4a084c00 0x40>;
1437 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
7aa1a408 1438 syscon-phy-power = <&scm_conf 0x370>;
57cd681b
TR		 1439 clocks = <&usb_phy3_always_on_clk32k>,
1440 <&sys_clkin1>,
1441 <&usb_otg_ss1_refclk960m>;
1442 clock-names = "wkupclk",
1443 "sysclk",
1444 "refclk";
1445 #phy-cells = <0>;
1446 };
1447 };
1448
1449 omap_dwc3_1: omap_dwc3_1@48880000 {
1450 compatible = "ti,dwc3";
1451 ti,hwmods = "usb_otg_ss1";
1452 reg = <0x48880000 0x10000>;
1453 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1454 #address-cells = <1>;
1455 #size-cells = <1>;
1456 utmi-mode = <2>;
1457 ranges;
1458 usb1: usb@48890000 {
1459 compatible = "snps,dwc3";
1460 reg = <0x48890000 0x17000>;
7aa1a408
LV		 1461 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1463 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1464 interrupt-names = "peripheral",
1465 "host",
1466 "otg";
57cd681b
TR		 1467 phys = <&usb2_phy1>, <&usb3_phy1>;
1468 phy-names = "usb2-phy", "usb3-phy";
57cd681b
TR		 1469 maximum-speed = "super-speed";
1470 dr_mode = "otg";
1471 snps,dis_u3_susphy_quirk;
1472 snps,dis_u2_susphy_quirk;
1473 };
1474 };
1475
1476 omap_dwc3_2: omap_dwc3_2@488c0000 {
1477 compatible = "ti,dwc3";
1478 ti,hwmods = "usb_otg_ss2";
1479 reg = <0x488c0000 0x10000>;
1480 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1481 #address-cells = <1>;
1482 #size-cells = <1>;
1483 utmi-mode = <2>;
1484 ranges;
1485 usb2: usb@488d0000 {
1486 compatible = "snps,dwc3";
1487 reg = <0x488d0000 0x17000>;
7aa1a408
LV		 1488 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1491 interrupt-names = "peripheral",
1492 "host",
1493 "otg";
57cd681b
TR		 1494 phys = <&usb2_phy2>;
1495 phy-names = "usb2-phy";
57cd681b
TR		 1496 maximum-speed = "high-speed";
1497 dr_mode = "otg";
1498 snps,dis_u3_susphy_quirk;
1499 snps,dis_u2_susphy_quirk;
1500 };
1501 };
1502
1503 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1504 omap_dwc3_3: omap_dwc3_3@48900000 {
1505 compatible = "ti,dwc3";
1506 ti,hwmods = "usb_otg_ss3";
1507 reg = <0x48900000 0x10000>;
1508 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1509 #address-cells = <1>;
1510 #size-cells = <1>;
1511 utmi-mode = <2>;
1512 ranges;
1513 status = "disabled";
1514 usb3: usb@48910000 {
1515 compatible = "snps,dwc3";
1516 reg = <0x48910000 0x17000>;
7aa1a408
LV		 1517 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1518 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1520 interrupt-names = "peripheral",
1521 "host",
1522 "otg";
57cd681b
TR		 1523 maximum-speed = "high-speed";
1524 dr_mode = "otg";
1525 snps,dis_u3_susphy_quirk;
1526 snps,dis_u2_susphy_quirk;
1527 };
1528 };
1529
1530 elm: elm@48078000 {
1531 compatible = "ti,am3352-elm";
1532 reg = <0x48078000 0xfc0>; /* device IO registers */
1533 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1534 ti,hwmods = "elm";
1535 status = "disabled";
1536 };
1537
1538 gpmc: gpmc@50000000 {
1539 compatible = "ti,am3352-gpmc";
1540 ti,hwmods = "gpmc";
1541 reg = <0x50000000 0x37c>; /* device IO registers */
1542 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
7aa1a408
LV		 1543 dmas = <&edma_xbar 4 0>;
1544 dma-names = "rxtx";
57cd681b
TR		 1545 gpmc,num-cs = <8>;
1546 gpmc,num-waitpins = <2>;
1547 #address-cells = <2>;
1548 #size-cells = <1>;
7aa1a408
LV		 1549 interrupt-controller;
1550 #interrupt-cells = <2>;
1551 gpio-controller;
1552 #gpio-cells = <2>;
57cd681b
TR		 1553 status = "disabled";
1554 };
1555
1556 atl: atl@4843c000 {
1557 compatible = "ti,dra7-atl";
1558 reg = <0x4843c000 0x3ff>;
1559 ti,hwmods = "atl";
1560 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1561 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1562 clocks = <&atl_gfclk_mux>;
1563 clock-names = "fck";
1564 status = "disabled";
1565 };
1566
7aa1a408
LV		 1567 mcasp1: mcasp@48460000 {
1568 compatible = "ti,dra7-mcasp-audio";
1569 ti,hwmods = "mcasp1";
1570 reg = <0x48460000 0x2000>,
1571 <0x45800000 0x1000>;
1572 reg-names = "mpu","dat";
1573 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1574 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1575 interrupt-names = "tx", "rx";
1576 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1577 dma-names = "tx", "rx";
1578 clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1579 <&mcasp1_ahclkr_mux>;
1580 clock-names = "fck", "ahclkx", "ahclkr";
1581 status = "disabled";
1582 };
1583
1584 mcasp2: mcasp@48464000 {
1585 compatible = "ti,dra7-mcasp-audio";
1586 ti,hwmods = "mcasp2";
1587 reg = <0x48464000 0x2000>,
1588 <0x45c00000 0x1000>;
1589 reg-names = "mpu","dat";
1590 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1591 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1592 interrupt-names = "tx", "rx";
1593 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1594 dma-names = "tx", "rx";
1595 clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1596 <&mcasp2_ahclkr_mux>;
1597 clock-names = "fck", "ahclkx", "ahclkr";
1598 status = "disabled";
1599 };
1600
1601 mcasp3: mcasp@48468000 {
1602 compatible = "ti,dra7-mcasp-audio";
1603 ti,hwmods = "mcasp3";
1604 reg = <0x48468000 0x2000>,
1605 <0x46000000 0x1000>;
1606 reg-names = "mpu","dat";
1607 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1608 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1609 interrupt-names = "tx", "rx";
1610 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1611 dma-names = "tx", "rx";
1612 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1613 clock-names = "fck", "ahclkx";
1614 status = "disabled";
1615 };
1616
1617 mcasp4: mcasp@4846c000 {
1618 compatible = "ti,dra7-mcasp-audio";
1619 ti,hwmods = "mcasp4";
1620 reg = <0x4846c000 0x2000>,
1621 <0x48436000 0x1000>;
1622 reg-names = "mpu","dat";
1623 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1624 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1625 interrupt-names = "tx", "rx";
1626 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1627 dma-names = "tx", "rx";
1628 clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1629 clock-names = "fck", "ahclkx";
1630 status = "disabled";
1631 };
1632
1633 mcasp5: mcasp@48470000 {
1634 compatible = "ti,dra7-mcasp-audio";
1635 ti,hwmods = "mcasp5";
1636 reg = <0x48470000 0x2000>,
1637 <0x4843a000 0x1000>;
1638 reg-names = "mpu","dat";
1639 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1640 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1641 interrupt-names = "tx", "rx";
1642 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1643 dma-names = "tx", "rx";
1644 clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1645 clock-names = "fck", "ahclkx";
1646 status = "disabled";
1647 };
1648
1649 mcasp6: mcasp@48474000 {
1650 compatible = "ti,dra7-mcasp-audio";
1651 ti,hwmods = "mcasp6";
1652 reg = <0x48474000 0x2000>,
1653 <0x4844c000 0x1000>;
1654 reg-names = "mpu","dat";
1655 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1656 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1657 interrupt-names = "tx", "rx";
1658 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1659 dma-names = "tx", "rx";
1660 clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1661 clock-names = "fck", "ahclkx";
1662 status = "disabled";
1663 };
1664
1665 mcasp7: mcasp@48478000 {
1666 compatible = "ti,dra7-mcasp-audio";
1667 ti,hwmods = "mcasp7";
1668 reg = <0x48478000 0x2000>,
1669 <0x48450000 0x1000>;
1670 reg-names = "mpu","dat";
1671 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1672 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1673 interrupt-names = "tx", "rx";
1674 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1675 dma-names = "tx", "rx";
1676 clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1677 clock-names = "fck", "ahclkx";
1678 status = "disabled";
1679 };
1680
1681 mcasp8: mcasp@4847c000 {
1682 compatible = "ti,dra7-mcasp-audio";
1683 ti,hwmods = "mcasp8";
1684 reg = <0x4847c000 0x2000>,
1685 <0x48454000 0x1000>;
1686 reg-names = "mpu","dat";
1687 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1688 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1689 interrupt-names = "tx", "rx";
1690 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1691 dma-names = "tx", "rx";
1692 clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1693 clock-names = "fck", "ahclkx";
1694 status = "disabled";
1695 };
1696
57cd681b
TR		 1697 crossbar_mpu: crossbar@4a002a48 {
1698 compatible = "ti,irq-crossbar";
1699 reg = <0x4a002a48 0x130>;
1700 interrupt-controller;
1701 interrupt-parent = <&wakeupgen>;
1702 #interrupt-cells = <3>;
1703 ti,max-irqs = <160>;
1704 ti,max-crossbar-sources = <MAX_SOURCES>;
1705 ti,reg-size = <2>;
1706 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1707 ti,irqs-skip = <10 133 139 140>;
1708 ti,irqs-safe-map = <0>;
1709 };
1710
844f8144 1711 mac: ethernet@48484000 {
7aa1a408 1712 compatible = "ti,dra7-cpsw","ti,cpsw";
57cd681b 1713 ti,hwmods = "gmac";
7aa1a408 1714 clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
57cd681b
TR		 1715 clock-names = "fck", "cpts";
1716 cpdma_channels = <8>;
1717 ale_entries = <1024>;
1718 bd_ram_size = <0x2000>;
1719 no_bd_ram = <0>;
57cd681b
TR		 1720 mac_control = <0x20>;
1721 slaves = <2>;
1722 active_slave = <0>;
7aa1a408 1723 cpts_clock_mult = <0x784CFE14>;
57cd681b 1724 cpts_clock_shift = <29>;
d7dc888d 1725 syscon = <&scm_conf>;
57cd681b
TR		 1726 reg = <0x48484000 0x1000
1727 0x48485200 0x2E00>;
1728 #address-cells = <1>;
1729 #size-cells = <1>;
7aa1a408
LV		 1730
1731 /*
1732 * Do not allow gating of cpsw clock as workaround
1733 * for errata i877. Keeping internal clock disabled
1734 * causes the device switching characteristics
1735 * to degrade over time and eventually fail to meet
1736 * the data manual delay time/skew specs.
1737 */
1738 ti,no-idle;
1739
57cd681b
TR		 1740 /*
1741 * rx_thresh_pend
1742 * rx_pend
1743 * tx_pend
1744 * misc_pend
1745 */
1746 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1747 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1748 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1749 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1750 ranges;
1751 status = "disabled";
1752
1753 davinci_mdio: mdio@48485000 {
7aa1a408 1754 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
57cd681b
TR		 1755 #address-cells = <1>;
1756 #size-cells = <0>;
1757 ti,hwmods = "davinci_mdio";
1758 bus_freq = <1000000>;
1759 reg = <0x48485000 0x100>;
1760 };
1761
1762 cpsw_emac0: slave@48480200 {
1763 /* Filled in by U-Boot */
1764 mac-address = [ 00 00 00 00 00 00 ];
1765 };
1766
1767 cpsw_emac1: slave@48480300 {
1768 /* Filled in by U-Boot */
1769 mac-address = [ 00 00 00 00 00 00 ];
1770 };
1771
1772 phy_sel: cpsw-phy-sel@4a002554 {
1773 compatible = "ti,dra7xx-cpsw-phy-sel";
1774 reg= <0x4a002554 0x4>;
1775 reg-names = "gmii-sel";
1776 };
1777 };
1778
1779 dcan1: can@481cc000 {
1780 compatible = "ti,dra7-d_can";
1781 ti,hwmods = "dcan1";
1782 reg = <0x4ae3c000 0x2000>;
1783 syscon-raminit = <&scm_conf 0x558 0>;
1784 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1785 clocks = <&dcan1_sys_clk_mux>;
1786 status = "disabled";
1787 };
1788
1789 dcan2: can@481d0000 {
1790 compatible = "ti,dra7-d_can";
1791 ti,hwmods = "dcan2";
1792 reg = <0x48480000 0x2000>;
1793 syscon-raminit = <&scm_conf 0x558 1>;
1794 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1795 clocks = <&sys_clkin1>;
1796 status = "disabled";
1797 };
1798
1799 dss: dss@58000000 {
1800 compatible = "ti,dra7-dss";
1801 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1802 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1803 status = "disabled";
1804 ti,hwmods = "dss_core";
1805 /* CTRL_CORE_DSS_PLL_CONTROL */
1806 syscon-pll-ctrl = <&scm_conf 0x538>;
1807 #address-cells = <1>;
1808 #size-cells = <1>;
1809 ranges;
1810
1811 dispc@58001000 {
1812 compatible = "ti,dra7-dispc";
1813 reg = <0x58001000 0x1000>;
1814 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1815 ti,hwmods = "dss_dispc";
1816 clocks = <&dss_dss_clk>;
1817 clock-names = "fck";
1818 /* CTRL_CORE_SMA_SW_1 */
1819 syscon-pol = <&scm_conf 0x534>;
1820 };
1821
1822 hdmi: encoder@58060000 {
1823 compatible = "ti,dra7-hdmi";
1824 reg = <0x58040000 0x200>,
1825 <0x58040200 0x80>,
1826 <0x58040300 0x80>,
1827 <0x58060000 0x19000>;
1828 reg-names = "wp", "pll", "phy", "core";
1829 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1830 status = "disabled";
1831 ti,hwmods = "dss_hdmi";
1832 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1833 clock-names = "fck", "sys_clk";
1834 };
1835 };
7aa1a408
LV		 1836
1837 epwmss0: epwmss@4843e000 {
1838 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1839 reg = <0x4843e000 0x30>;
1840 ti,hwmods = "epwmss0";
1841 #address-cells = <1>;
1842 #size-cells = <1>;
1843 status = "disabled";
1844 ranges;
1845
1846 ehrpwm0: pwm@4843e200 {
1847 compatible = "ti,dra746-ehrpwm",
1848 "ti,am3352-ehrpwm";
1849 #pwm-cells = <3>;
1850 reg = <0x4843e200 0x80>;
1851 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1852 clock-names = "tbclk", "fck";
1853 status = "disabled";
1854 };
1855
1856 ecap0: ecap@4843e100 {
1857 compatible = "ti,dra746-ecap",
1858 "ti,am3352-ecap";
1859 #pwm-cells = <3>;
1860 reg = <0x4843e100 0x80>;
1861 clocks = <&l4_root_clk_div>;
1862 clock-names = "fck";
1863 status = "disabled";
1864 };
1865 };
1866
1867 epwmss1: epwmss@48440000 {
1868 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1869 reg = <0x48440000 0x30>;
1870 ti,hwmods = "epwmss1";
1871 #address-cells = <1>;
1872 #size-cells = <1>;
1873 status = "disabled";
1874 ranges;
1875
1876 ehrpwm1: pwm@48440200 {
1877 compatible = "ti,dra746-ehrpwm",
1878 "ti,am3352-ehrpwm";
1879 #pwm-cells = <3>;
1880 reg = <0x48440200 0x80>;
1881 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1882 clock-names = "tbclk", "fck";
1883 status = "disabled";
1884 };
1885
1886 ecap1: ecap@48440100 {
1887 compatible = "ti,dra746-ecap",
1888 "ti,am3352-ecap";
1889 #pwm-cells = <3>;
1890 reg = <0x48440100 0x80>;
1891 clocks = <&l4_root_clk_div>;
1892 clock-names = "fck";
1893 status = "disabled";
1894 };
1895 };
1896
1897 epwmss2: epwmss@48442000 {
1898 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1899 reg = <0x48442000 0x30>;
1900 ti,hwmods = "epwmss2";
1901 #address-cells = <1>;
1902 #size-cells = <1>;
1903 status = "disabled";
1904 ranges;
1905
1906 ehrpwm2: pwm@48442200 {
1907 compatible = "ti,dra746-ehrpwm",
1908 "ti,am3352-ehrpwm";
1909 #pwm-cells = <3>;
1910 reg = <0x48442200 0x80>;
1911 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1912 clock-names = "tbclk", "fck";
1913 status = "disabled";
1914 };
1915
1916 ecap2: ecap@48442100 {
1917 compatible = "ti,dra746-ecap",
1918 "ti,am3352-ecap";
1919 #pwm-cells = <3>;
1920 reg = <0x48442100 0x80>;
1921 clocks = <&l4_root_clk_div>;
1922 clock-names = "fck";
1923 status = "disabled";
1924 };
1925 };
1926
1927 aes1: aes@4b500000 {
1928 compatible = "ti,omap4-aes";
1929 ti,hwmods = "aes1";
1930 reg = <0x4b500000 0xa0>;
1931 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1932 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1933 dma-names = "tx", "rx";
1934 clocks = <&l3_iclk_div>;
1935 clock-names = "fck";
1936 };
1937
1938 aes2: aes@4b700000 {
1939 compatible = "ti,omap4-aes";
1940 ti,hwmods = "aes2";
1941 reg = <0x4b700000 0xa0>;
1942 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1943 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1944 dma-names = "tx", "rx";
1945 clocks = <&l3_iclk_div>;
1946 clock-names = "fck";
1947 };
1948
1949 des: des@480a5000 {
1950 compatible = "ti,omap4-des";
1951 ti,hwmods = "des";
1952 reg = <0x480a5000 0xa0>;
1953 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1954 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
1955 dma-names = "tx", "rx";
1956 clocks = <&l3_iclk_div>;
1957 clock-names = "fck";
1958 };
1959
1960 sham: sham@53100000 {
1961 compatible = "ti,omap5-sham";
1962 ti,hwmods = "sham";
1963 reg = <0x4b101000 0x300>;
1964 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1965 dmas = <&edma_xbar 119 0>;
1966 dma-names = "rx";
1967 clocks = <&l3_iclk_div>;
1968 clock-names = "fck";
1969 };
1970
1971 rng: rng@48090000 {
1972 compatible = "ti,omap4-rng";
1973 ti,hwmods = "rng";
1974 reg = <0x48090000 0x2000>;
1975 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1976 clocks = <&l3_iclk_div>;
1977 clock-names = "fck";
1978 };
57cd681b
TR		 1979 };
1980
1981 thermal_zones: thermal-zones {
1982 #include "omap4-cpu-thermal.dtsi"
1983 #include "omap5-gpu-thermal.dtsi"
1984 #include "omap5-core-thermal.dtsi"
7aa1a408
LV		 1985 #include "dra7-dspeve-thermal.dtsi"
1986 #include "dra7-iva-thermal.dtsi"
57cd681b
TR		 1987 };
1988
1989};
1990
1991&cpu_thermal {
1992 polling-delay = <500>; /* milliseconds */
1993};
1994
1995/include/ "dra7xx-clocks.dtsi"
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