projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| d678a59d | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 1b2f4697 SA |
2 | /* |
| 3 | * Device Tree Source for AM62 SoC Family | |
| 4 | * | |
| d678a59d | 5 | * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ |
| 1b2f4697 SA |
6 | */ |
| 7 | ||
| 8 | #include <dt-bindings/gpio/gpio.h> | |
| 9 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 1b2f4697 SA |
11 | #include <dt-bindings/soc/ti,sci_pm_domain.h> |
| 12 | ||
| 7937af12 NM |
13 | #include "k3-pinctrl.h" |
| 14 | ||
| 1b2f4697 SA |
15 | / { |
| 16 | model = "Texas Instruments K3 AM625 SoC"; | |
| 17 | compatible = "ti,am625"; | |
| 18 | interrupt-parent = <&gic500>; | |
| 19 | #address-cells = <2>; | |
| 20 | #size-cells = <2>; | |
| 21 | ||
| 22 | chosen { }; | |
| 23 | ||
| 24 | firmware { | |
| 25 | optee { | |
| 26 | compatible = "linaro,optee-tz"; | |
| 27 | method = "smc"; | |
| 28 | }; | |
| 29 | ||
| 30 | psci: psci { | |
| 31 | compatible = "arm,psci-1.0"; | |
| 32 | method = "smc"; | |
| 33 | }; | |
| 34 | }; | |
| 35 | ||
| 36 | a53_timer0: timer-cl0-cpu0 { | |
| 37 | compatible = "arm,armv8-timer"; | |
| 38 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ | |
| 39 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ | |
| 40 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ | |
| 41 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ | |
| 42 | }; | |
| 43 | ||
| 44 | pmu: pmu { | |
| 45 | compatible = "arm,cortex-a53-pmu"; | |
| 46 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 47 | }; | |
| 48 | ||
| 49 | cbass_main: bus@f0000 { | |
| a0ca5f24 | 50 | bootph-all; |
| 1b2f4697 SA |
51 | compatible = "simple-bus"; |
| 52 | #address-cells = <2>; | |
| 53 | #size-cells = <2>; | |
| 54 | ||
| 55 | ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ | |
| 56 | <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ | |
| 57 | <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ | |
| 58 | <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ | |
| 59 | <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ | |
| 60 | <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ | |
| 61 | <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ | |
| 62 | <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ | |
| 63 | <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ | |
| 64 | <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ | |
| 65 | <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ | |
| 66 | <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ | |
| 67 | <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ | |
| 68 | <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ | |
| 69 | <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ | |
| 70 | <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ | |
| 8bd8a5d0 | 71 | <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ |
| 1b2f4697 SA |
72 | <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ |
| 73 | <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ | |
| 74 | <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ | |
| 75 | <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ | |
| 76 | <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ | |
| 77 | <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ | |
| 78 | <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ | |
| 79 | <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ | |
| 80 | ||
| 81 | /* MCU Domain Range */ | |
| 82 | <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, | |
| 83 | ||
| 84 | /* Wakeup Domain Range */ | |
| 7937af12 | 85 | <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ |
| 1b2f4697 SA |
86 | <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, |
| 87 | <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; | |
| 88 | ||
| 89 | cbass_mcu: bus@4000000 { | |
| a0ca5f24 | 90 | bootph-all; |
| 1b2f4697 SA |
91 | compatible = "simple-bus"; |
| 92 | #address-cells = <2>; | |
| 93 | #size-cells = <2>; | |
| 94 | ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ | |
| 95 | }; | |
| 96 | ||
| 7937af12 | 97 | cbass_wakeup: bus@b00000 { |
| a0ca5f24 | 98 | bootph-all; |
| 1b2f4697 SA |
99 | compatible = "simple-bus"; |
| 100 | #address-cells = <2>; | |
| 101 | #size-cells = <2>; | |
| 7937af12 NM |
102 | ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ |
| 103 | <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ | |
| 1b2f4697 SA |
104 | <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; |
| 105 | }; | |
| 106 | }; | |
| 7937af12 | 107 | |
| 0d33f528 NM |
108 | dss_vp1_clk: clock-divider-oldi { |
| 109 | compatible = "fixed-factor-clock"; | |
| 110 | clocks = <&k3_clks 186 0>; | |
| 111 | #clock-cells = <0>; | |
| 112 | clock-div = <7>; | |
| 113 | clock-mult = <1>; | |
| 114 | }; | |
| 115 | ||
| 7937af12 | 116 | #include "k3-am62-thermal.dtsi" |
| 1b2f4697 SA |
117 | }; |
| 118 | ||
| 119 | /* Now include the peripherals for each bus segments */ | |
| 120 | #include "k3-am62-main.dtsi" | |
| 121 | #include "k3-am62-mcu.dtsi" | |
| 122 | #include "k3-am62-wakeup.dtsi" |