[thirdparty/u-boot.git] / arch / arm / dts / k3-am62a.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for AM62A SoC Family
 *
 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>

#include "k3-pinctrl.h"

/ {
	model = "Texas Instruments K3 AM62A SoC";
	compatible = "ti,am62a7";
	interrupt-parent = <&gic500>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci: psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	a53_timer0: timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
	};

	pmu: pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	cbass_main: bus@f0000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
			 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
			 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
			 <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */
			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */

			 /* MCU Domain Range */
			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
			 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
			 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
			 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */
			 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */

			 /* Wakeup Domain Range */
			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */
			 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */

		cbass_mcu: bus@4000000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
				 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
				 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
				 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
				 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
		};

		cbass_wakeup: bus@b00000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
				 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
				 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
		};
	};

	#include "k3-am62a-thermal.dtsi"
};

/* Now include the peripherals for each bus segments */
#include "k3-am62a-main.dtsi"
#include "k3-am62a-mcu.dtsi"
#include "k3-am62a-wakeup.dtsi"
Commit	Line	Data
d678a59d	1	// SPDX-License-Identifier: GPL-2.0
25380291 BB	2	/*
	3	* Device Tree Source for AM62A SoC Family
	4	*
d678a59d	5	* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
25380291 BB	6	*/
	7
	8	#include <dt-bindings/gpio/gpio.h>
	9	#include <dt-bindings/interrupt-controller/irq.h>
	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
25380291 BB	11	#include <dt-bindings/soc/ti,sci_pm_domain.h>
25380291 BB	12
e703bfcb NM	13	#include "k3-pinctrl.h"
e703bfcb NM	14
25380291 BB	15	/ {
	16	model = "Texas Instruments K3 AM62A SoC";
	17	compatible = "ti,am62a7";
	18	interrupt-parent = <&gic500>;
	19	#address-cells = <2>;
	20	#size-cells = <2>;
	21
	22	chosen { };
	23
	24	firmware {
	25	optee {
	26	compatible = "linaro,optee-tz";
	27	method = "smc";
	28	};
	29
	30	psci: psci {
	31	compatible = "arm,psci-1.0";
	32	method = "smc";
	33	};
	34	};
	35
	36	a53_timer0: timer-cl0-cpu0 {
	37	compatible = "arm,armv8-timer";
	38	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
	39	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
	40	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
	41	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
	42	};
	43
	44	pmu: pmu {
	45	compatible = "arm,cortex-a53-pmu";
	46	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	47	};
	48
	49	cbass_main: bus@f0000 {
	50	compatible = "simple-bus";
	51	#address-cells = <2>;
	52	#size-cells = <2>;
	53
	54	ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
	55	<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
	56	<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
	57	<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
	58	<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
	59	<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
	60	<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
	61	<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
	62	<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
	63	<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
	64	<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
	65	<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
	66	<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
	67	<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
	68	<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
	69	<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
	70	<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
	71	<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
	72	<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
	73	<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
	74	<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
	75	<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
	76	<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
	77	<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
	78	<0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */
79	<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
80	<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
81
82	/* MCU Domain Range */
83	<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
84	<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
85	<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
86	<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */
87	<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */
88
89	/* Wakeup Domain Range */
90	<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
91	<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
92	<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
93	<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */
94	<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */
95
96	cbass_mcu: bus@4000000 {
97	compatible = "simple-bus";
98	#address-cells = <2>;
99	#size-cells = <2>;
100	ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
101	<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
102	<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
103	<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
104	<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
105	};
106
107	cbass_wakeup: bus@b00000 {
108	compatible = "simple-bus";
109	#address-cells = <2>;
110	#size-cells = <2>;
111	ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
112	<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
113	<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
114	<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
115	<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
116	};
117	};
e703bfcb NM	118
e703bfcb NM	119	#include "k3-am62a-thermal.dtsi"
25380291 BB	120	};
	121
	122	/* Now include the peripherals for each bus segments */
	123	#include "k3-am62a-main.dtsi"
	124	#include "k3-am62a-mcu.dtsi"
	125	#include "k3-am62a-wakeup.dtsi"