projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7bdd1554 MY |
1 | /* |
| 2 | * Device Tree Source for UniPhier PH1-LD20 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> | |
| 5 | * | |
| 6 | * SPDX-License-Identifier: GPL-2.0+ X11 | |
| 7 | */ | |
| 8 | ||
| 9 | / { | |
| 10 | compatible = "socionext,ph1-ld20"; | |
| 11 | #address-cells = <2>; | |
| 12 | #size-cells = <2>; | |
| 13 | interrupt-parent = <&gic>; | |
| 14 | ||
| 15 | cpus { | |
| 16 | #address-cells = <2>; | |
| 17 | #size-cells = <0>; | |
| 18 | ||
| 19 | cpu-map { | |
| 20 | cluster0 { | |
| 21 | core0 { | |
| 22 | cpu = <&cpu0>; | |
| 23 | }; | |
| 24 | core1 { | |
| 25 | cpu = <&cpu1>; | |
| 26 | }; | |
| 27 | }; | |
| 28 | ||
| 29 | cluster1 { | |
| 30 | core0 { | |
| 31 | cpu = <&cpu2>; | |
| 32 | }; | |
| 33 | core1 { | |
| 34 | cpu = <&cpu3>; | |
| 35 | }; | |
| 36 | }; | |
| 37 | }; | |
| 38 | ||
| 39 | cpu0: cpu@0 { | |
| 40 | device_type = "cpu"; | |
| 41 | compatible = "arm,cortex-a72", "arm,armv8"; | |
| 42 | reg = <0 0x000>; | |
| 43 | enable-method = "spin-table"; | |
| 44 | cpu-release-addr = <0 0x80000100>; | |
| 45 | }; | |
| 46 | ||
| 47 | cpu1: cpu@1 { | |
| 48 | device_type = "cpu"; | |
| 49 | compatible = "arm,cortex-a72", "arm,armv8"; | |
| 50 | reg = <0 0x001>; | |
| 51 | enable-method = "spin-table"; | |
| 52 | cpu-release-addr = <0 0x80000100>; | |
| 53 | }; | |
| 54 | ||
| 55 | cpu2: cpu@100 { | |
| 56 | device_type = "cpu"; | |
| 57 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 58 | reg = <0 0x100>; | |
| 59 | enable-method = "spin-table"; | |
| 60 | cpu-release-addr = <0 0x80000100>; | |
| 61 | }; | |
| 62 | ||
| 63 | cpu3: cpu@101 { | |
| 64 | device_type = "cpu"; | |
| 65 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 66 | reg = <0 0x101>; | |
| 67 | enable-method = "spin-table"; | |
| 68 | cpu-release-addr = <0 0x80000100>; | |
| 69 | }; | |
| 70 | }; | |
| 71 | ||
| 72 | clocks { | |
| 73 | uart_clk: uart_clk { | |
| 74 | #clock-cells = <0>; | |
| 75 | compatible = "fixed-clock"; | |
| 76 | clock-frequency = <58820000>; | |
| 77 | }; | |
| 78 | ||
| 79 | i2c_clk: i2c_clk { | |
| 80 | #clock-cells = <0>; | |
| 81 | compatible = "fixed-clock"; | |
| 82 | clock-frequency = <50000000>; | |
| 83 | }; | |
| 84 | }; | |
| 85 | ||
| 86 | timer { | |
| 87 | compatible = "arm,armv8-timer"; | |
| 88 | interrupts = <1 13 0xf01>, | |
| 89 | <1 14 0xf01>, | |
| 90 | <1 11 0xf01>, | |
| 91 | <1 10 0xf01>; | |
| 92 | }; | |
| 93 | ||
| 94 | soc { | |
| 95 | compatible = "simple-bus"; | |
| 96 | #address-cells = <1>; | |
| 97 | #size-cells = <1>; | |
| 98 | ranges = <0 0 0 0xffffffff>; | |
| 99 | ||
| 100 | serial0: serial@54006800 { | |
| 101 | compatible = "socionext,uniphier-uart"; | |
| 102 | status = "disabled"; | |
| 103 | reg = <0x54006800 0x40>; | |
| 104 | interrupts = <0 33 4>; | |
| 105 | pinctrl-names = "default"; | |
| 106 | pinctrl-0 = <&pinctrl_uart0>; | |
| 107 | clocks = <&uart_clk>; | |
| f1494981 | 108 | clock-frequency = <58820000>; |
| 7bdd1554 MY |
109 | }; |
| 110 | ||
| 111 | serial1: serial@54006900 { | |
| 112 | compatible = "socionext,uniphier-uart"; | |
| 113 | status = "disabled"; | |
| 114 | reg = <0x54006900 0x40>; | |
| 115 | interrupts = <0 35 4>; | |
| 116 | pinctrl-names = "default"; | |
| 117 | pinctrl-0 = <&pinctrl_uart1>; | |
| 118 | clocks = <&uart_clk>; | |
| f1494981 | 119 | clock-frequency = <58820000>; |
| 7bdd1554 MY |
120 | }; |
| 121 | ||
| 122 | serial2: serial@54006a00 { | |
| 123 | compatible = "socionext,uniphier-uart"; | |
| 124 | status = "disabled"; | |
| 125 | reg = <0x54006a00 0x40>; | |
| 126 | interrupts = <0 37 4>; | |
| 127 | pinctrl-names = "default"; | |
| 128 | pinctrl-0 = <&pinctrl_uart2>; | |
| 129 | clocks = <&uart_clk>; | |
| f1494981 | 130 | clock-frequency = <58820000>; |
| 7bdd1554 MY |
131 | }; |
| 132 | ||
| 133 | serial3: serial@54006b00 { | |
| 134 | compatible = "socionext,uniphier-uart"; | |
| 135 | status = "disabled"; | |
| 136 | reg = <0x54006b00 0x40>; | |
| 137 | interrupts = <0 177 4>; | |
| 138 | pinctrl-names = "default"; | |
| 139 | pinctrl-0 = <&pinctrl_uart3>; | |
| 140 | clocks = <&uart_clk>; | |
| f1494981 | 141 | clock-frequency = <58820000>; |
| 7bdd1554 MY |
142 | }; |
| 143 | ||
| 144 | i2c0: i2c@58780000 { | |
| 145 | compatible = "socionext,uniphier-fi2c"; | |
| 146 | status = "disabled"; | |
| 147 | reg = <0x58780000 0x80>; | |
| 148 | #address-cells = <1>; | |
| 149 | #size-cells = <0>; | |
| 150 | interrupts = <0 41 4>; | |
| 151 | pinctrl-names = "default"; | |
| 152 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 153 | clocks = <&i2c_clk>; | |
| 154 | clock-frequency = <100000>; | |
| 155 | }; | |
| 156 | ||
| 157 | i2c1: i2c@58781000 { | |
| 158 | compatible = "socionext,uniphier-fi2c"; | |
| 159 | status = "disabled"; | |
| 160 | reg = <0x58781000 0x80>; | |
| 161 | #address-cells = <1>; | |
| 162 | #size-cells = <0>; | |
| 163 | interrupts = <0 42 4>; | |
| 164 | pinctrl-names = "default"; | |
| 165 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 166 | clocks = <&i2c_clk>; | |
| 167 | clock-frequency = <100000>; | |
| 168 | }; | |
| 169 | ||
| 170 | i2c2: i2c@58782000 { | |
| 171 | compatible = "socionext,uniphier-fi2c"; | |
| 172 | reg = <0x58782000 0x80>; | |
| 173 | #address-cells = <1>; | |
| 174 | #size-cells = <0>; | |
| 175 | interrupts = <0 43 4>; | |
| 176 | clocks = <&i2c_clk>; | |
| 177 | clock-frequency = <400000>; | |
| 178 | }; | |
| 179 | ||
| 180 | i2c3: i2c@58783000 { | |
| 181 | compatible = "socionext,uniphier-fi2c"; | |
| 182 | status = "disabled"; | |
| 183 | reg = <0x58783000 0x80>; | |
| 184 | #address-cells = <1>; | |
| 185 | #size-cells = <0>; | |
| 186 | interrupts = <0 44 4>; | |
| 187 | pinctrl-names = "default"; | |
| 188 | pinctrl-0 = <&pinctrl_i2c3>; | |
| 189 | clocks = <&i2c_clk>; | |
| 190 | clock-frequency = <100000>; | |
| 191 | }; | |
| 192 | ||
| 193 | i2c4: i2c@58784000 { | |
| 194 | compatible = "socionext,uniphier-fi2c"; | |
| 195 | status = "disabled"; | |
| 196 | reg = <0x58784000 0x80>; | |
| 197 | #address-cells = <1>; | |
| 198 | #size-cells = <0>; | |
| 199 | interrupts = <0 45 4>; | |
| 200 | pinctrl-names = "default"; | |
| 201 | pinctrl-0 = <&pinctrl_i2c4>; | |
| 202 | clocks = <&i2c_clk>; | |
| 203 | clock-frequency = <100000>; | |
| 204 | }; | |
| 205 | ||
| 206 | i2c5: i2c@58785000 { | |
| 207 | compatible = "socionext,uniphier-fi2c"; | |
| 208 | reg = <0x58785000 0x80>; | |
| 209 | #address-cells = <1>; | |
| 210 | #size-cells = <0>; | |
| 211 | interrupts = <0 25 4>; | |
| 212 | clocks = <&i2c_clk>; | |
| 213 | clock-frequency = <400000>; | |
| 214 | }; | |
| 215 | ||
| 216 | system_bus: system-bus@58c00000 { | |
| 217 | compatible = "socionext,uniphier-system-bus"; | |
| 218 | status = "disabled"; | |
| 219 | reg = <0x58c00000 0x400>; | |
| 220 | #address-cells = <2>; | |
| 221 | #size-cells = <1>; | |
| 222 | }; | |
| 223 | ||
| 224 | smpctrl@59800000 { | |
| 225 | compatible = "socionext,uniphier-smpctrl"; | |
| 226 | reg = <0x59801000 0x400>; | |
| 227 | }; | |
| 228 | ||
| 3d970876 MY |
229 | mio: mioctrl@59810000 { |
| 230 | compatible = "socionext,ph1-ld20-mioctrl"; | |
| 231 | reg = <0x59810000 0x800>; | |
| 232 | #clock-cells = <1>; | |
| 233 | }; | |
| 234 | ||
| 235 | sd: sdhc@5a400000 { | |
| 236 | compatible = "socionext,uniphier-sdhc"; | |
| 237 | status = "disabled"; | |
| 238 | reg = <0x5a400000 0x800>; | |
| 239 | interrupts = <0 76 4>; | |
| 240 | pinctrl-names = "default"; | |
| 241 | pinctrl-0 = <&pinctrl_sd>; | |
| 242 | clocks = <&mio 0>; | |
| 243 | bus-width = <4>; | |
| 244 | }; | |
| 245 | ||
| 7bdd1554 MY |
246 | pinctrl: pinctrl@5f801000 { |
| 247 | compatible = "socionext,ph1-ld20-pinctrl", "syscon"; | |
| 248 | reg = <0x5f801000 0xe00>; | |
| 249 | }; | |
| 250 | ||
| 251 | gic: interrupt-controller@5fe00000 { | |
| 252 | compatible = "arm,gic-v3"; | |
| 253 | reg = <0x5fe00000 0x10000>, /* GICD */ | |
| 254 | <0x5fe80000 0x80000>; /* GICR */ | |
| 255 | interrupt-controller; | |
| 256 | #interrupt-cells = <3>; | |
| 257 | interrupts = <1 9 4>; | |
| 258 | }; | |
| 259 | }; | |
| 260 | }; | |
| 261 | ||
| 262 | /include/ "uniphier-pinctrl.dtsi" |