[people/ms/u-boot.git] / arch / arm / dts / zynq-microzed.dts

/*
 * Xilinx MicroZED board DTS
 *
 * Copyright (C) 2013 Xilinx, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
/dts-v1/;
#include "zynq-7000.dtsi"

/ {
	model = "Zynq MicroZED Board";
	compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";

	aliases {
		serial0 = &uart1;
		spi0 = &qspi;
	};

	memory {
		device_type = "memory";
		reg = <0 0x40000000>;
	};
};

&qspi {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&uart1 {
	u-boot,dm-pre-reloc;
	status = "okay";
};
Commit	Line	Data
9e0802bf JT	1	/*
	2	* Xilinx MicroZED board DTS
	3	*
	4	* Copyright (C) 2013 Xilinx, Inc.
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8	/dts-v1/;
	9	#include "zynq-7000.dtsi"
	10
	11	/ {
	12	model = "Zynq MicroZED Board";
	13	compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
7d34c5de	14
9f9d41ba MY	15	aliases {
9f9d41ba MY	16	serial0 = &uart1;
659cc156	17	spi0 = &qspi;
9f9d41ba MY	18	};
9f9d41ba MY	19
7d34c5de MY	20	memory {
	21	device_type = "memory";
	22	reg = <0 0x40000000>;
	23	};
9e0802bf	24	};
659cc156 JT	25
659cc156 JT	26	&qspi {
cb204a69	27	u-boot,dm-pre-reloc;
659cc156 JT	28	status = "okay";
659cc156 JT	29	};
035c6b27 SG	30
	31	&uart1 {
	32	u-boot,dm-pre-reloc;
	33	status = "okay";
	34	};