[people/ms/u-boot.git] / arch / arm / imx-common / iomux-v3.c

/*
 * Based on the iomux-v3.c from Linux kernel:
 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
 *                       <armlinux@phytec.de>
 *
 * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/sys_proto.h>

static void *base = (void *)IOMUXC_BASE_ADDR;

/*
 * configures a single pad in the iomuxer
 */
void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
{
	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
	u32 sel_input_ofs =
		(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
	u32 sel_input =
		(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
	u32 pad_ctrl_ofs =
		(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;

#if defined CONFIG_MX6SL
	/* Check whether LVE bit needs to be set */
	if (pad_ctrl & PAD_CTL_LVE) {
		pad_ctrl &= ~PAD_CTL_LVE;
		pad_ctrl |= PAD_CTL_LVE_BIT;
	}
#endif

#ifdef CONFIG_IOMUX_LPSR
	u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;

	if (lpsr == IOMUX_CONFIG_LPSR) {
		base = (void *)IOMUXC_LPSR_BASE_ADDR;
		mux_mode &= ~IOMUX_CONFIG_LPSR;
		/* set daisy chain sel_input */
		if (sel_input_ofs)
			sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
	}
#endif

	if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
		__raw_writel(mux_mode, base + mux_ctrl_ofs);

	if (sel_input_ofs)
		__raw_writel(sel_input, base + sel_input_ofs);

#ifdef CONFIG_IOMUX_SHARE_CONF_REG
	if (!(pad_ctrl & NO_PAD_CTRL))
		__raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
			base + pad_ctrl_ofs);
#else
	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
		__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
#endif

#ifdef CONFIG_IOMUX_LPSR
	if (lpsr == IOMUX_CONFIG_LPSR)
		base = (void *)IOMUXC_BASE_ADDR;
#endif

}

/* configures a list of pads within declared with IOMUX_PADS macro */
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
				      unsigned count)
{
	iomux_v3_cfg_t const *p = pad_list;
	int stride;
	int i;

#if defined(CONFIG_MX6QDL)
	stride = 2;
	if (!is_mx6dq())
		p += 1;
#else
	stride = 1;
#endif
	for (i = 0; i < count; i++) {
		imx_iomux_v3_setup_pad(*p);
		p += stride;
	}
}

void imx_iomux_set_gpr_register(int group, int start_bit,
					int num_bits, int value)
{
	int i = 0;
	u32 reg;
	reg = readl(base + group * 4);
	while (num_bits) {
		reg &= ~(1<<(start_bit + i));
		i++;
		num_bits--;
	}
	reg |= (value << start_bit);
	writel(reg, base + group * 4);
}

#ifdef CONFIG_IOMUX_SHARE_CONF_REG
void imx_iomux_gpio_set_direction(unsigned int gpio,
				unsigned int direction)
{
	u32 reg;
	/*
	 * Only on Vybrid the input/output buffer enable flags
	 * are part of the shared mux/conf register.
	 */
	reg = readl(base + (gpio << 2));

	if (direction)
		reg |= 0x2;
	else
		reg &= ~0x2;

	writel(reg, base + (gpio << 2));
}

void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
{
	*gpio_state = readl(base + (gpio << 2)) &
		((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
}
#endif
Commit	Line	Data
23608e23 JL	1	/*
	2	* Based on the iomux-v3.c from Linux kernel:
	3	* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
	4	* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
	5	* <armlinux@phytec.de>
	6	*
	7	* Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	10	*/
	11	#include <common.h>
	12	#include <asm/io.h>
	13	#include <asm/arch/imx-regs.h>
af2a35fb	14	#include <asm/imx-common/iomux-v3.h>
cf226d99	15	#include <asm/imx-common/sys_proto.h>
23608e23 JL	16
	17	static void base = (void )IOMUXC_BASE_ADDR;
	18
	19	/*
	20	* configures a single pad in the iomuxer
	21	*/
59efa051	22	void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
23608e23 JL	23	{
	24	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
	25	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
	26	u32 sel_input_ofs =
	27	(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
	28	u32 sel_input =
	29	(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
	30	u32 pad_ctrl_ofs =
	31	(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
	32	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
	33
98d2cffd FE	34	#if defined CONFIG_MX6SL
	35	/* Check whether LVE bit needs to be set */
	36	if (pad_ctrl & PAD_CTL_LVE) {
	37	pad_ctrl &= ~PAD_CTL_LVE;
	38	pad_ctrl \|= PAD_CTL_LVE_BIT;
	39	}
	40	#endif
	41
03f0e4c7 AA	42	#ifdef CONFIG_IOMUX_LPSR
	43	u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
	44
	45	if (lpsr == IOMUX_CONFIG_LPSR) {
	46	base = (void *)IOMUXC_LPSR_BASE_ADDR;
	47	mux_mode &= ~IOMUX_CONFIG_LPSR;
	48	/* set daisy chain sel_input */
	49	if (sel_input_ofs)
	50	sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
	51	}
	52	#endif
	53
cf226d99 PF	54	if (is_soc_type(MXC_SOC_MX7) \|\| mux_ctrl_ofs)
cf226d99 PF	55	__raw_writel(mux_mode, base + mux_ctrl_ofs);
23608e23 JL	56
	57	if (sel_input_ofs)
	58	__raw_writel(sel_input, base + sel_input_ofs);
	59
cfd701b5 AW	60	#ifdef CONFIG_IOMUX_SHARE_CONF_REG
	61	if (!(pad_ctrl & NO_PAD_CTRL))
	62	__raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) \| pad_ctrl,
	63	base + pad_ctrl_ofs);
	64	#else
23608e23 JL	65	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
23608e23 JL	66	__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
cfd701b5	67	#endif
03f0e4c7 AA	68
	69	#ifdef CONFIG_IOMUX_LPSR
	70	if (lpsr == IOMUX_CONFIG_LPSR)
	71	base = (void *)IOMUXC_BASE_ADDR;
	72	#endif
	73
23608e23 JL	74	}
23608e23 JL	75
5bf497e3	76	/* configures a list of pads within declared with IOMUX_PADS macro */
59efa051 SR	77	void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
59efa051 SR	78	unsigned count)
23608e23	79	{
5ae28d2d	80	iomux_v3_cfg_t const *p = pad_list;
5bf497e3	81	int stride;
23608e23	82	int i;
23608e23	83
5bf497e3 TH	84	#if defined(CONFIG_MX6QDL)
5bf497e3 TH	85	stride = 2;
27cd0da4	86	if (!is_mx6dq())
5bf497e3 TH	87	p += 1;
	88	#else
	89	stride = 1;
	90	#endif
	91	for (i = 0; i < count; i++) {
	92	imx_iomux_v3_setup_pad(*p);
	93	p += stride;
	94	}
23608e23	95	}
8fe280f3 YL	96
	97	void imx_iomux_set_gpr_register(int group, int start_bit,
	98	int num_bits, int value)
	99	{
	100	int i = 0;
	101	u32 reg;
	102	reg = readl(base + group * 4);
	103	while (num_bits) {
	104	reg &= ~(1<<(start_bit + i));
	105	i++;
	106	num_bits--;
	107	}
	108	reg \|= (value << start_bit);
	109	writel(reg, base + group * 4);
	110	}
d348a943 BD	111
	112	#ifdef CONFIG_IOMUX_SHARE_CONF_REG
	113	void imx_iomux_gpio_set_direction(unsigned int gpio,
	114	unsigned int direction)
	115	{
	116	u32 reg;
	117	/*
	118	* Only on Vybrid the input/output buffer enable flags
	119	* are part of the shared mux/conf register.
	120	*/
	121	reg = readl(base + (gpio << 2));
	122
	123	if (direction)
	124	reg \|= 0x2;
	125	else
	126	reg &= ~0x2;
	127
	128	writel(reg, base + (gpio << 2));
	129	}
	130
	131	void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
	132	{
	133	*gpio_state = readl(base + (gpio << 2)) &
	134	((0X07 << PAD_MUX_MODE_SHIFT) \| PAD_CTL_OBE_IBE_ENABLE);
	135	}
	136	#endif