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Commit | Line | Data |
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b43c17cb MP |
1 | /* |
2 | * hardware_ti814x.h | |
3 | * | |
4 | * TI814x hardware specific header | |
5 | * | |
6 | * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
b43c17cb MP |
9 | */ |
10 | ||
11 | #ifndef __AM33XX_HARDWARE_TI814X_H | |
12 | #define __AM33XX_HARDWARE_TI814X_H | |
13 | ||
8b029f22 MP |
14 | /* Module base addresses */ |
15 | ||
16 | /* UART Base Address */ | |
17 | #define UART0_BASE 0x48020000 | |
18 | ||
19 | /* Watchdog Timer */ | |
20 | #define WDT_BASE 0x481C7000 | |
21 | ||
22 | /* Control Module Base Address */ | |
23 | #define CTRL_BASE 0x48140000 | |
035d5639 | 24 | #define CTRL_DEVICE_BASE 0x48140600 |
8b029f22 MP |
25 | |
26 | /* PRCM Base Address */ | |
27 | #define PRCM_BASE 0x48180000 | |
28 | ||
29 | /* PLL Subsystem Base Address */ | |
30 | #define PLL_SUBSYS_BASE 0x481C5000 | |
31 | ||
b43c17cb MP |
32 | /* VTP Base address */ |
33 | #define VTP0_CTRL_ADDR 0x48140E0C | |
34 | ||
35 | /* DDR Base address */ | |
36 | #define DDR_PHY_CMD_ADDR 0x47C0C400 | |
37 | #define DDR_PHY_DATA_ADDR 0x47C0C4C8 | |
38 | #define DDR_DATA_REGS_NR 4 | |
39 | ||
8b029f22 MP |
40 | /* CPSW Config space */ |
41 | #define CPSW_MDIO_BASE 0x4A100800 | |
42 | ||
43 | /* RTC base address */ | |
44 | #define RTC_BASE 0x480C0000 | |
45 | ||
b43c17cb | 46 | #endif /* __AM33XX_HARDWARE_TI814X_H */ |