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6c08d5dc PW |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Marvell Semiconductor <www.marvell.com> | |
4 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
5 | * Contributor: Mahavir Jain <mjain@marvell.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
6c08d5dc PW |
8 | */ |
9 | ||
10 | #ifndef _ASM_ARCH_ARMADA100_H | |
11 | #define _ASM_ARCH_ARMADA100_H | |
12 | ||
6c08d5dc | 13 | #if defined (CONFIG_ARMADA100) |
6c08d5dc PW |
14 | |
15 | /* Common APB clock register bit definitions */ | |
16 | #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ | |
17 | #define APBC_FNCLK (1<<1) /* Functional Clock Enable */ | |
18 | #define APBC_RST (1<<2) /* Reset Generation */ | |
19 | /* Functional Clock Selection Mask */ | |
20 | #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) | |
21 | ||
aa0ecfeb AB |
22 | /* Fast Ethernet Controller Clock register definition */ |
23 | #define FE_CLK_RST 0x1 | |
24 | #define FE_CLK_ENA 0x8 | |
25 | ||
daa4b2f7 AB |
26 | /* SSP2 Clock Control */ |
27 | #define SSP2_APBCLK 0x01 | |
28 | #define SSP2_FNCLK 0x02 | |
29 | ||
732c7c24 AB |
30 | /* USB Clock/reset control bits */ |
31 | #define USB_SPH_AXICLK_EN 0x10 | |
32 | #define USB_SPH_AXI_RST 0x02 | |
33 | ||
34 | /* MPMU Clocks */ | |
35 | #define APB2_26M_EN (1 << 20) | |
36 | #define AP_26M (1 << 4) | |
37 | ||
6c08d5dc PW |
38 | /* Register Base Addresses */ |
39 | #define ARMD1_DRAM_BASE 0xB0000000 | |
79788bb1 | 40 | #define ARMD1_FEC_BASE 0xC0800000 |
6c08d5dc PW |
41 | #define ARMD1_TIMER_BASE 0xD4014000 |
42 | #define ARMD1_APBC1_BASE 0xD4015000 | |
43 | #define ARMD1_APBC2_BASE 0xD4015800 | |
44 | #define ARMD1_UART1_BASE 0xD4017000 | |
45 | #define ARMD1_UART2_BASE 0xD4018000 | |
46 | #define ARMD1_GPIO_BASE 0xD4019000 | |
47 | #define ARMD1_SSP1_BASE 0xD401B000 | |
48 | #define ARMD1_SSP2_BASE 0xD401C000 | |
49 | #define ARMD1_MFPR_BASE 0xD401E000 | |
50 | #define ARMD1_SSP3_BASE 0xD401F000 | |
51 | #define ARMD1_SSP4_BASE 0xD4020000 | |
52 | #define ARMD1_SSP5_BASE 0xD4021000 | |
53 | #define ARMD1_UART3_BASE 0xD4026000 | |
54 | #define ARMD1_MPMU_BASE 0xD4050000 | |
54cb0048 | 55 | #define ARMD1_USB_HOST_BASE 0xD4209000 |
6c08d5dc PW |
56 | #define ARMD1_APMU_BASE 0xD4282800 |
57 | #define ARMD1_CPU_BASE 0xD4282C00 | |
58 | ||
6c08d5dc PW |
59 | #endif /* CONFIG_ARMADA100 */ |
60 | #endif /* _ASM_ARCH_ARMADA100_H */ |