[people/ms/u-boot.git] / arch / arm / include / asm / arch-at91 / at91_spi.h

/*
 * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
 *
 * Copyright (C) 2005 Ivan Kokshaysky
 * Copyright (C) SAN People
 *
 * Serial Peripheral Interface (SPI) registers.
 * Based on AT91RM9200 datasheet revision E.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef AT91_SPI_H
#define AT91_SPI_H

#include <asm/arch/at91_pdc.h>

typedef struct at91_spi {
	u32		cr;		/* 0x00 Control Register */
	u32		mr;		/* 0x04 Mode Register */
	u32		rdr;		/* 0x08 Receive Data Register */
	u32		tdr;		/* 0x0C Transmit Data Register */
	u32		sr;		/* 0x10 Status Register */
	u32		ier;		/* 0x14 Interrupt Enable Register */
	u32		idr;		/* 0x18 Interrupt Disable Register */
	u32		imr;		/* 0x1C Interrupt Mask Register */
	u32		reserve1[4];
	u32		csr[4];		/* 0x30 Chip Select Register 0-3 */
	u32		reserve2[48];
	at91_pdc_t	pdc;
} at91_spi_t;

#ifdef CONFIG_ATMEL_LEGACY

#define AT91_SPI_CR			0x00		/* Control Register */
#define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
#define		AT91_SPI_SPIDIS		(1 <<  1)		/* SPI Disable */
#define		AT91_SPI_SWRST		(1 <<  7)		/* SPI Software Reset */
#define		AT91_SPI_LASTXFER	(1 << 24)		/* Last Transfer [SAM9261 only] */

#define AT91_SPI_MR			0x04		/* Mode Register */
#define		AT91_SPI_MSTR		(1    <<  0)		/* Master/Slave Mode */
#define		AT91_SPI_PS		(1    <<  1)		/* Peripheral Select */
#define			AT91_SPI_PS_FIXED	(0 << 1)
#define			AT91_SPI_PS_VARIABLE	(1 << 1)
#define		AT91_SPI_PCSDEC		(1    <<  2)		/* Chip Select Decode */
#define		AT91_SPI_DIV32		(1    <<  3)		/* Clock Selection [AT91RM9200 only] */
#define		AT91_SPI_MODFDIS	(1    <<  4)		/* Mode Fault Detection */
#define		AT91_SPI_LLB		(1    <<  7)		/* Local Loopback Enable */
#define		AT91_SPI_PCS		(0xf  << 16)		/* Peripheral Chip Select */
#define		AT91_SPI_DLYBCS		(0xff << 24)		/* Delay Between Chip Selects */

#define AT91_SPI_RDR		0x08			/* Receive Data Register */
#define		AT91_SPI_RD		(0xffff <<  0)		/* Receive Data */
#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */

#define AT91_SPI_TDR		0x0c			/* Transmit Data Register */
#define		AT91_SPI_TD		(0xffff <<  0)		/* Transmit Data */
#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
#define		AT91_SPI_LASTXFER	(1	<< 24)		/* Last Transfer [SAM9261 only] */

#define AT91_SPI_SR		0x10			/* Status Register */
#define		AT91_SPI_RDRF		(1 <<  0)		/* Receive Data Register Full */
#define		AT91_SPI_TDRE		(1 <<  1)		/* Transmit Data Register Full */
#define		AT91_SPI_MODF		(1 <<  2)		/* Mode Fault Error */
#define		AT91_SPI_OVRES		(1 <<  3)		/* Overrun Error Status */
#define		AT91_SPI_ENDRX		(1 <<  4)		/* End of RX buffer */
#define		AT91_SPI_ENDTX		(1 <<  5)		/* End of TX buffer */
#define		AT91_SPI_RXBUFF		(1 <<  6)		/* RX Buffer Full */
#define		AT91_SPI_TXBUFE		(1 <<  7)		/* TX Buffer Empty */
#define		AT91_SPI_NSSR		(1 <<  8)		/* NSS Rising [SAM9261 only] */
#define		AT91_SPI_TXEMPTY	(1 <<  9)		/* Transmission Register Empty [SAM9261 only] */
#define		AT91_SPI_SPIENS		(1 << 16)		/* SPI Enable Status */

#define AT91_SPI_IER		0x14			/* Interrupt Enable Register */
#define AT91_SPI_IDR		0x18			/* Interrupt Disable Register */
#define AT91_SPI_IMR		0x1c			/* Interrupt Mask Register */

#define AT91_SPI_CSR(n)		(0x30 + ((n) * 4))	/* Chip Select Registers 0-3 */
#define		AT91_SPI_CPOL		(1    <<  0)		/* Clock Polarity */
#define		AT91_SPI_NCPHA		(1    <<  1)		/* Clock Phase */
#define		AT91_SPI_CSAAT		(1    <<  3)		/* Chip Select Active After Transfer [SAM9261 only] */
#define		AT91_SPI_BITS		(0xf  <<  4)		/* Bits Per Transfer */
#define			AT91_SPI_BITS_8		(0 << 4)
#define			AT91_SPI_BITS_9		(1 << 4)
#define			AT91_SPI_BITS_10	(2 << 4)
#define			AT91_SPI_BITS_11	(3 << 4)
#define			AT91_SPI_BITS_12	(4 << 4)
#define			AT91_SPI_BITS_13	(5 << 4)
#define			AT91_SPI_BITS_14	(6 << 4)
#define			AT91_SPI_BITS_15	(7 << 4)
#define			AT91_SPI_BITS_16	(8 << 4)
#define		AT91_SPI_SCBR		(0xff <<  8)		/* Serial Clock Baud Rate */
#define		AT91_SPI_DLYBS		(0xff << 16)		/* Delay before SPCK */
#define		AT91_SPI_DLYBCT		(0xff << 24)		/* Delay between Consecutive Transfers */

#define AT91_SPI_RPR		0x0100			/* Receive Pointer Register */

#define AT91_SPI_RCR		0x0104			/* Receive Counter Register */

#define AT91_SPI_TPR		0x0108			/* Transmit Pointer Register */

#define AT91_SPI_TCR		0x010c			/* Transmit Counter Register */

#define AT91_SPI_RNPR		0x0110			/* Receive Next Pointer Register */

#define AT91_SPI_RNCR		0x0114			/* Receive Next Counter Register */

#define AT91_SPI_TNPR		0x0118			/* Transmit Next Pointer Register */

#define AT91_SPI_TNCR		0x011c			/* Transmit Next Counter Register */

#define AT91_SPI_PTCR		0x0120			/* PDC Transfer Control Register */
#define		AT91_SPI_RXTEN		(0x1 << 0)		/* Receiver Transfer Enable */
#define		AT91_SPI_RXTDIS		(0x1 << 1)		/* Receiver Transfer Disable */
#define		AT91_SPI_TXTEN		(0x1 << 8)		/* Transmitter Transfer Enable */
#define		AT91_SPI_TXTDIS		(0x1 << 9)		/* Transmitter Transfer Disable */

#define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */

#endif /* CONFIG_AT91_LEGACY */

#endif
Commit	Line	Data
6d1dbbbf	1	/*
9606b3c8	2	* [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
6d1dbbbf SP	3	*
	4	* Copyright (C) 2005 Ivan Kokshaysky
	5	* Copyright (C) SAN People
	6	*
	7	* Serial Peripheral Interface (SPI) registers.
	8	* Based on AT91RM9200 datasheet revision E.
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
6d1dbbbf SP	11	*/
	12
	13	#ifndef AT91_SPI_H
	14	#define AT91_SPI_H
	15
5d8e359c JS	16	#include <asm/arch/at91_pdc.h>
	17
	18	typedef struct at91_spi {
	19	u32 cr; /* 0x00 Control Register */
	20	u32 mr; /* 0x04 Mode Register */
	21	u32 rdr; /* 0x08 Receive Data Register */
	22	u32 tdr; /* 0x0C Transmit Data Register */
	23	u32 sr; /* 0x10 Status Register */
	24	u32 ier; /* 0x14 Interrupt Enable Register */
	25	u32 idr; /* 0x18 Interrupt Disable Register */
	26	u32 imr; /* 0x1C Interrupt Mask Register */
	27	u32 reserve1[4];
	28	u32 csr[4]; /* 0x30 Chip Select Register 0-3 */
	29	u32 reserve2[48];
	30	at91_pdc_t pdc;
	31	} at91_spi_t;
	32
ffa280fa	33	#ifdef CONFIG_ATMEL_LEGACY
5d8e359c	34
6d1dbbbf SP	35	#define AT91_SPI_CR 0x00 /* Control Register */
	36	#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
	37	#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
	38	#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
	39	#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
	40
	41	#define AT91_SPI_MR 0x04 /* Mode Register */
	42	#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
	43	#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
	44	#define AT91_SPI_PS_FIXED (0 << 1)
	45	#define AT91_SPI_PS_VARIABLE (1 << 1)
	46	#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
	47	#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
	48	#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
	49	#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
	50	#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
	51	#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
	52
	53	#define AT91_SPI_RDR 0x08 /* Receive Data Register */
	54	#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
	55	#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
	56
	57	#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
	58	#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
	59	#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
	60	#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
	61
	62	#define AT91_SPI_SR 0x10 /* Status Register */
	63	#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
	64	#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
	65	#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
	66	#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
	67	#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
	68	#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
	69	#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
	70	#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
	71	#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
	72	#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
	73	#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
	74
	75	#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
	76	#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
	77	#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
	78
	79	#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
	80	#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
	81	#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
	82	#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
	83	#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
	84	#define AT91_SPI_BITS_8 (0 << 4)
	85	#define AT91_SPI_BITS_9 (1 << 4)
	86	#define AT91_SPI_BITS_10 (2 << 4)
	87	#define AT91_SPI_BITS_11 (3 << 4)
	88	#define AT91_SPI_BITS_12 (4 << 4)
	89	#define AT91_SPI_BITS_13 (5 << 4)
	90	#define AT91_SPI_BITS_14 (6 << 4)
	91	#define AT91_SPI_BITS_15 (7 << 4)
	92	#define AT91_SPI_BITS_16 (8 << 4)
	93	#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
	94	#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
	95	#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
	96
177e8a5a SP	97	#define AT91_SPI_RPR 0x0100 /* Receive Pointer Register */
	98
	99	#define AT91_SPI_RCR 0x0104 /* Receive Counter Register */
	100
	101	#define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */
	102
	103	#define AT91_SPI_TCR 0x010c /* Transmit Counter Register */
	104
	105	#define AT91_SPI_RNPR 0x0110 /* Receive Next Pointer Register */
	106
	107	#define AT91_SPI_RNCR 0x0114 /* Receive Next Counter Register */
	108
	109	#define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */
	110
	111	#define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */
	112
	113	#define AT91_SPI_PTCR 0x0120 /* PDC Transfer Control Register */
	114	#define AT91_SPI_RXTEN (0x1 << 0) /* Receiver Transfer Enable */
	115	#define AT91_SPI_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */
	116	#define AT91_SPI_TXTEN (0x1 << 8) /* Transmitter Transfer Enable */
	117	#define AT91_SPI_TXTDIS (0x1 << 9) /* Transmitter Transfer Disable */
	118
	119	#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
	120
5d8e359c JS	121	#endif /* CONFIG_AT91_LEGACY */
5d8e359c JS	122
6d1dbbbf	123	#endif