projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| d99a8ff6 SP |
1 | /* |
| 2 | * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] | |
| 3 | * | |
| 4 | * Copyright (C) SAN People | |
| 5 | * | |
| 6 | * Common definitions. | |
| 7 | * Based on AT91SAM9261 datasheet revision E. (Preliminary) | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License as published by | |
| 11 | * the Free Software Foundation; either version 2 of the License, or | |
| 12 | * (at your option) any later version. | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef AT91SAM9261_H | |
| 16 | #define AT91SAM9261_H | |
| 17 | ||
| 18 | /* | |
| 19 | * Peripheral identifiers/interrupts. | |
| 20 | */ | |
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | |
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | |
| 23 | #define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ | |
| 24 | #define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ | |
| 25 | #define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ | |
| 26 | #define AT91SAM9261_ID_US0 6 /* USART 0 */ | |
| 27 | #define AT91SAM9261_ID_US1 7 /* USART 1 */ | |
| 28 | #define AT91SAM9261_ID_US2 8 /* USART 2 */ | |
| 29 | #define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ | |
| 30 | #define AT91SAM9261_ID_UDP 10 /* USB Device Port */ | |
| 31 | #define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ | |
| 32 | #define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | |
| 33 | #define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | |
| 34 | #define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | |
| 35 | #define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | |
| 36 | #define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ | |
| 37 | #define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ | |
| 38 | #define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ | |
| 39 | #define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ | |
| 40 | #define AT91SAM9261_ID_UHP 20 /* USB Host port */ | |
| 41 | #define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ | |
| 42 | #define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | |
| 43 | #define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | |
| 44 | #define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | |
| 45 | ||
| 5d8e359c JS |
46 | #define AT91_SDRAMC_BASE 0xffffea00 |
| 47 | #define AT91_SMC_BASE 0xffffec00 | |
| 48 | #define AT91_MATRIX_BASE 0xffffee00 | |
| 49 | #define AT91_PIO_BASE 0xfffff400 | |
| 50 | #define AT91_PMC_BASE 0xfffffc00 | |
| 51 | #define AT91_RSTC_BASE 0xfffffd00 | |
| 52 | #define AT91_PIT_BASE 0xfffffd30 | |
| 53 | #define AT91_WDT_BASE 0xfffffd40 | |
| 54 | ||
| 55 | #ifdef CONFIG_AT91_LEGACY | |
| d99a8ff6 SP |
56 | |
| 57 | /* | |
| 58 | * User Peripheral physical base addresses. | |
| 59 | */ | |
| 60 | #define AT91SAM9261_BASE_TCB0 0xfffa0000 | |
| 61 | #define AT91SAM9261_BASE_TC0 0xfffa0000 | |
| 62 | #define AT91SAM9261_BASE_TC1 0xfffa0040 | |
| 63 | #define AT91SAM9261_BASE_TC2 0xfffa0080 | |
| 64 | #define AT91SAM9261_BASE_UDP 0xfffa4000 | |
| 65 | #define AT91SAM9261_BASE_MCI 0xfffa8000 | |
| 66 | #define AT91SAM9261_BASE_TWI 0xfffac000 | |
| 67 | #define AT91SAM9261_BASE_US0 0xfffb0000 | |
| 68 | #define AT91SAM9261_BASE_US1 0xfffb4000 | |
| 69 | #define AT91SAM9261_BASE_US2 0xfffb8000 | |
| 70 | #define AT91SAM9261_BASE_SSC0 0xfffbc000 | |
| 71 | #define AT91SAM9261_BASE_SSC1 0xfffc0000 | |
| 72 | #define AT91SAM9261_BASE_SSC2 0xfffc4000 | |
| 73 | #define AT91SAM9261_BASE_SPI0 0xfffc8000 | |
| 74 | #define AT91SAM9261_BASE_SPI1 0xfffcc000 | |
| 75 | #define AT91_BASE_SYS 0xffffea00 | |
| 76 | ||
| d99a8ff6 SP |
77 | /* |
| 78 | * System Peripherals (offset from AT91_BASE_SYS) | |
| 79 | */ | |
| 80 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | |
| 81 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | |
| 82 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | |
| 83 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | |
| 84 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | |
| 85 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | |
| 86 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | |
| 87 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | |
| 88 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | |
| 89 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | |
| 90 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | |
| 91 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | |
| 92 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | |
| 93 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | |
| 94 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | |
| 95 | ||
| 96 | #define AT91_USART0 AT91SAM9261_BASE_US0 | |
| 97 | #define AT91_USART1 AT91SAM9261_BASE_US1 | |
| 98 | #define AT91_USART2 AT91SAM9261_BASE_US2 | |
| 99 | ||
| 5d8e359c | 100 | #endif /* CONFIG_AT91_LEGACY */ |
| d99a8ff6 SP |
101 | |
| 102 | /* | |
| 103 | * Internal Memory. | |
| 104 | */ | |
| 105 | #define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | |
| 106 | #define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ | |
| 107 | ||
| 108 | #define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ | |
| 109 | #define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | |
| 110 | ||
| 111 | #define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ | |
| 112 | #define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ | |
| 113 | ||
| b32e1890 JCPV |
114 | /* |
| 115 | * Cpu Name | |
| 116 | */ | |
| 7c966a8b | 117 | #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" |
| d99a8ff6 SP |
118 | |
| 119 | #endif |