[people/ms/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / soc.h

/*
 * Copyright 2017 NXP
 * Copyright 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_

#ifndef __ASSEMBLY__
#include <linux/types.h>
#ifdef CONFIG_FSL_LSCH2
#include <asm/arch/immap_lsch2.h>
#endif
#ifdef CONFIG_FSL_LSCH3
#include <asm/arch/immap_lsch3.h>
#endif
#endif

#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
#define gur_in32(a)       in_le32(a)
#define gur_out32(a, v)   out_le32(a, v)
#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
#define gur_in32(a)       in_be32(a)
#define gur_out32(a, v)   out_be32(a, v)
#endif

#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
#define scfg_in32(a)       in_le32(a)
#define scfg_out32(a, v)   out_le32(a, v)
#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
#define scfg_in32(a)       in_be32(a)
#define scfg_out32(a, v)   out_be32(a, v)
#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
#endif

#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
#define pex_lut_in32(a)       in_le32(a)
#define pex_lut_out32(a, v)   out_le32(a, v)
#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
#define pex_lut_in32(a)       in_be32(a)
#define pex_lut_out32(a, v)   out_be32(a, v)
#endif
#ifndef __ASSEMBLY__
struct cpu_type {
	char name[15];
	u32 soc_ver;
	u32 num_cores;
};

#define CPU_TYPE_ENTRY(n, v, nc) \
	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
#endif
#define SVR_WO_E		0xFFFFFE
#define SVR_LS1012A		0x870400
#define SVR_LS1043A		0x879200
#define SVR_LS1023A		0x879208
#define SVR_LS1046A		0x870700
#define SVR_LS1026A		0x870708
#define SVR_LS1048A		0x870320
#define SVR_LS1084A		0x870302
#define SVR_LS1088A		0x870300
#define SVR_LS1044A		0x870322
#define SVR_LS2045A		0x870120
#define SVR_LS2080A		0x870110
#define SVR_LS2085A		0x870100
#define SVR_LS2040A		0x870130
#define SVR_LS2088A		0x870900
#define SVR_LS2084A		0x870910
#define SVR_LS2048A		0x870920
#define SVR_LS2044A		0x870930
#define SVR_LS2081A		0x870918
#define SVR_LS2041A		0x870914

#define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
#define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
#define SVR_REV(svr)		(((svr) >> 0) & 0xff)
#define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
#define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
#define IS_SVR_REV(svr, maj, min) \
		((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
#define SVR_DEV(svr)		((svr) >> 8)
#define IS_SVR_DEV(svr, dev)	(((svr) >> 16) == (dev))

/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG    0xa003fffe
#define AHCI_PORT_TRANS_CFG    0x08000029
#define AHCI_PORT_AXICC_CFG	0x3fffffff

#ifndef __ASSEMBLY__
/* AHCI (sata) register map */
struct ccsr_ahci {
	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
	u32 pcfg;	/* port config */
	u32 ppcfg;	/* port phy1 config */
	u32 pp2c;	/* port phy2 config */
	u32 pp3c;	/* port phy3 config */
	u32 pp4c;	/* port phy4 config */
	u32 pp5c;	/* port phy5 config */
	u32 axicc;	/* AXI cache control */
	u32 paxic;	/* port AXI config */
	u32 axipc;	/* AXI PROT control */
	u32 ptc;	/* port Trans Config */
	u32 pts;	/* port Trans Status */
	u32 plc;	/* port link config */
	u32 plc1;	/* port link config1 */
	u32 plc2;	/* port link config2 */
	u32 pls;	/* port link status */
	u32 pls1;	/* port link status1 */
	u32 pcmdc;	/* port CMD config */
	u32 ppcs;	/* port phy control status */
	u32 pberr;	/* port 0/1 BIST error */
	u32 cmds;	/* port 0/1 CMD status error */
};

#ifdef CONFIG_FSL_LSCH3
void fsl_lsch3_early_init_f(void);
#elif defined(CONFIG_FSL_LSCH2)
void fsl_lsch2_early_init_f(void);
int setup_chip_volt(void);
/* Setup core vdd in unit mV */
int board_setup_core_volt(u32 vdd);
#endif

void cpu_name(char *name);
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
void erratum_a009635(void);
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
void erratum_a010315(void);
#endif

bool soc_has_dp_ddr(void);
bool soc_has_aiop(void);
#endif

#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
Commit	Line	Data
b991b981	1	/*
e809e747	2	* Copyright 2017 NXP
b991b981 SW	3	* Copyright 2015 Freescale Semiconductor
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
9f3183d2 MH	8	#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
	9	#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
	10
457e51cf SG	11	#ifndef __ASSEMBLY__
	12	#include <linux/types.h>
	13	#ifdef CONFIG_FSL_LSCH2
	14	#include <asm/arch/immap_lsch2.h>
	15	#endif
	16	#ifdef CONFIG_FSL_LSCH3
	17	#include <asm/arch/immap_lsch3.h>
	18	#endif
	19	#endif
	20
9f3183d2 MH	21	#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
	22	#define gur_in32(a) in_le32(a)
	23	#define gur_out32(a, v) out_le32(a, v)
	24	#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
	25	#define gur_in32(a) in_be32(a)
	26	#define gur_out32(a, v) out_be32(a, v)
	27	#endif
	28
	29	#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
	30	#define scfg_in32(a) in_le32(a)
	31	#define scfg_out32(a, v) out_le32(a, v)
9a609a88 RW	32	#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
9a609a88 RW	33	#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
9f3183d2 MH	34	#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
	35	#define scfg_in32(a) in_be32(a)
	36	#define scfg_out32(a, v) out_be32(a, v)
9a609a88 RW	37	#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
9a609a88 RW	38	#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
9f3183d2 MH	39	#endif
9f3183d2 MH	40
af523a0d MH	41	#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
	42	#define pex_lut_in32(a) in_le32(a)
	43	#define pex_lut_out32(a, v) out_le32(a, v)
	44	#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
	45	#define pex_lut_in32(a) in_be32(a)
	46	#define pex_lut_out32(a, v) out_be32(a, v)
	47	#endif
f6b96ff6	48	#ifndef __ASSEMBLY__
22629665 PK	49	struct cpu_type {
	50	char name[15];
	51	u32 soc_ver;
	52	u32 num_cores;
	53	};
	54
	55	#define CPU_TYPE_ENTRY(n, v, nc) \
	56	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
f6b96ff6	57	#endif
22629665	58	#define SVR_WO_E 0xFFFFFE
49cdce16 PK	59	#define SVR_LS1012A 0x870400
	60	#define SVR_LS1043A 0x879200
	61	#define SVR_LS1023A 0x879208
b528b937 MH	62	#define SVR_LS1046A 0x870700
b528b937 MH	63	#define SVR_LS1026A 0x870708
6d9b82d0 AK	64	#define SVR_LS1048A 0x870320
	65	#define SVR_LS1084A 0x870302
	66	#define SVR_LS1088A 0x870300
	67	#define SVR_LS1044A 0x870322
49cdce16 PK	68	#define SVR_LS2045A 0x870120
	69	#define SVR_LS2080A 0x870110
	70	#define SVR_LS2085A 0x870100
	71	#define SVR_LS2040A 0x870130
9ae836cd PJ	72	#define SVR_LS2088A 0x870900
	73	#define SVR_LS2084A 0x870910
	74	#define SVR_LS2048A 0x870920
	75	#define SVR_LS2044A 0x870930
ec8a7d77 SK	76	#define SVR_LS2081A 0x870918
ec8a7d77 SK	77	#define SVR_LS2041A 0x870914
22629665 PK	78
	79	#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
	80	#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
fa18ed76	81	#define SVR_REV(svr) (((svr) >> 0) & 0xff)
22629665 PK	82	#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
22629665 PK	83	#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
6fb522dc SD	84	#define IS_SVR_REV(svr, maj, min) \
6fb522dc SD	85	((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
a8f33034 W	86	#define SVR_DEV(svr) ((svr) >> 8)
a8f33034 W	87	#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
22629665	88
989c5f0a TY	89	/* ahci port register default value */
989c5f0a TY	90	#define AHCI_PORT_PHY_1_CFG 0xa003fffe
989c5f0a	91	#define AHCI_PORT_TRANS_CFG 0x08000029
4de6ce15	92	#define AHCI_PORT_AXICC_CFG 0x3fffffff
989c5f0a	93
f6b96ff6	94	#ifndef __ASSEMBLY__
989c5f0a TY	95	/* AHCI (sata) register map */
	96	struct ccsr_ahci {
	97	u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
	98	u32 pcfg; /* port config */
	99	u32 ppcfg; /* port phy1 config */
	100	u32 pp2c; /* port phy2 config */
	101	u32 pp3c; /* port phy3 config */
	102	u32 pp4c; /* port phy4 config */
	103	u32 pp5c; /* port phy5 config */
	104	u32 axicc; /* AXI cache control */
	105	u32 paxic; /* port AXI config */
	106	u32 axipc; /* AXI PROT control */
	107	u32 ptc; /* port Trans Config */
	108	u32 pts; /* port Trans Status */
	109	u32 plc; /* port link config */
	110	u32 plc1; /* port link config1 */
	111	u32 plc2; /* port link config2 */
	112	u32 pls; /* port link status */
	113	u32 pls1; /* port link status1 */
	114	u32 pcmdc; /* port CMD config */
	115	u32 ppcs; /* port phy control status */
	116	u32 pberr; /* port 0/1 BIST error */
	117	u32 cmds; /* port 0/1 CMD status error */
	118	};
	119
8281c58f	120	#ifdef CONFIG_FSL_LSCH3
b991b981	121	void fsl_lsch3_early_init_f(void);
8281c58f MH	122	#elif defined(CONFIG_FSL_LSCH2)
8281c58f MH	123	void fsl_lsch2_early_init_f(void);
031acdba HZ	124	int setup_chip_volt(void);
	125	/* Setup core vdd in unit mV */
	126	int board_setup_core_volt(u32 vdd);
8281c58f MH	127	#endif
8281c58f MH	128
22629665	129	void cpu_name(char *name);
b4017364 PK	130	#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
	131	void erratum_a009635(void);
	132	#endif
3c1d218a	133
b392a6d4 HZ	134	#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
	135	void erratum_a010315(void);
	136	#endif
	137
3c1d218a YS	138	bool soc_has_dp_ddr(void);
3c1d218a YS	139	bool soc_has_aiop(void);
f6b96ff6	140	#endif
457e51cf	141
9f3183d2	142	#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */