[people/ms/u-boot.git] / arch / arm / include / asm / arch-nomadik / mtu.h

/*
 * (C) Copyright 2009 Alessandro Rubini
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ASM_ARCH_MTU_H
#define __ASM_ARCH_MTU_H

/*
 * The MTU device hosts four different counters, with 4 set of
 * registers. These are register names.
 */

#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
#define MTU_RIS		0x04	/* Raw interrupt status */
#define MTU_MIS		0x08	/* Masked interrupt status */
#define MTU_ICR		0x0C	/* Interrupt clear register */

/* per-timer registers take 0..3 as argument */
#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */

/* bits for the control register */
#define MTU_CRn_ENA		0x80
#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
#define MTU_CRn_PRESCALE_MASK	0x0c
#define MTU_CRn_PRESCALE_1		0x00
#define MTU_CRn_PRESCALE_16		0x04
#define MTU_CRn_PRESCALE_256		0x08
#define MTU_CRn_32BITS		0x02
#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/

/* Other registers are usual amba/primecell registers, currently not used */
#define MTU_ITCR	0xff0
#define MTU_ITOP	0xff4

#define MTU_PERIPH_ID0	0xfe0
#define MTU_PERIPH_ID1	0xfe4
#define MTU_PERIPH_ID2	0xfe8
#define MTU_PERIPH_ID3	0xfeC

#define MTU_PCELL0	0xff0
#define MTU_PCELL1	0xff4
#define MTU_PCELL2	0xff8
#define MTU_PCELL3	0xffC

#endif /* __ASM_ARCH_MTU_H */
Commit	Line	Data
095a460b AR	1	/*
	2	* (C) Copyright 2009 Alessandro Rubini
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
095a460b AR	5	*/
	6
	7	#ifndef __ASM_ARCH_MTU_H
	8	#define __ASM_ARCH_MTU_H
	9
	10	/*
	11	* The MTU device hosts four different counters, with 4 set of
	12	* registers. These are register names.
	13	*/
	14
	15	#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
	16	#define MTU_RIS 0x04 /* Raw interrupt status */
	17	#define MTU_MIS 0x08 /* Masked interrupt status */
	18	#define MTU_ICR 0x0C /* Interrupt clear register */
	19
	20	/* per-timer registers take 0..3 as argument */
	21	#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
	22	#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
	23	#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
	24	#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
	25
	26	/* bits for the control register */
	27	#define MTU_CRn_ENA 0x80
	28	#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
	29	#define MTU_CRn_PRESCALE_MASK 0x0c
	30	#define MTU_CRn_PRESCALE_1 0x00
	31	#define MTU_CRn_PRESCALE_16 0x04
	32	#define MTU_CRn_PRESCALE_256 0x08
	33	#define MTU_CRn_32BITS 0x02
	34	#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
	35
	36	/* Other registers are usual amba/primecell registers, currently not used */
	37	#define MTU_ITCR 0xff0
	38	#define MTU_ITOP 0xff4
	39
	40	#define MTU_PERIPH_ID0 0xfe0
	41	#define MTU_PERIPH_ID1 0xfe4
	42	#define MTU_PERIPH_ID2 0xfe8
	43	#define MTU_PERIPH_ID3 0xfeC
	44
	45	#define MTU_PCELL0 0xff0
	46	#define MTU_PCELL1 0xff4
	47	#define MTU_PCELL2 0xff8
	48	#define MTU_PCELL3 0xffC
	49
	50	#endif /* __ASM_ARCH_MTU_H */