[people/ms/u-boot.git] / arch / arm / include / asm / arch-omap3 / mem.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _MEM_H_
#define _MEM_H_

#define CS0		0x0
#define CS1		0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */

#ifndef __ASSEMBLY__
enum {
	STACKED = 0,
	IP_DDR = 1,
	COMBO_DDR = 2,
	IP_SDR = 3,
};
#endif /* __ASSEMBLY__ */

#define EARLY_INIT	1

/*
 * For a full explanation of these registers and values please see
 * the Technical Reference Manual (TRM) for any of the processors in
 * this family.
 */

/* Slower full frequency range default timings for x32 operation*/
#define SDRC_SHARING	0x00000100
#define SDRC_MR_0_SDR	0x00000031

/*
 * SDRC autorefresh control values.  This register consists of autorefresh
 * enable at bits 0:1 and an autorefresh counter value in bits 8:23.  The
 * counter is a result of ( tREFI / tCK ) - 50.
 */
#define SDP_3430_SDRC_RFR_CTRL_100MHz	0x0002da01
#define SDP_3430_SDRC_RFR_CTRL_133MHz	0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
#define SDP_3430_SDRC_RFR_CTRL_165MHz	0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
#define SDP_3430_SDRC_RFR_CTRL_200MHz	0x0005e601 /* 7.8us/5ns - 50=0x5e6 */

#define DLL_OFFSET		0
#define DLL_WRITEDDRCLKX2DIS	1
#define DLL_ENADLL		1
#define DLL_LOCKDLL		0
#define DLL_DLLPHASE_72		0
#define DLL_DLLPHASE_90		1

/* rkw - need to find of 90/72 degree recommendation for speed like before */
#define SDP_SDRC_DLLAB_CTRL	((DLL_ENADLL << 3) | \
				(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))

/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
#define ACTIM_CTRLA_TRFC(v)	(((v) & 0x1F) << 27)	/* 31:27 */
#define ACTIM_CTRLA_TRC(v)	(((v) & 0x1F) << 22)	/* 26:22 */
#define ACTIM_CTRLA_TRAS(v)	(((v) & 0x0F) << 18)	/* 21:18 */
#define ACTIM_CTRLA_TRP(v)	(((v) & 0x07) << 15)	/* 17:15 */
#define ACTIM_CTRLA_TRCD(v)	(((v) & 0x07) << 12)	/* 14:12 */
#define ACTIM_CTRLA_TRRD(v)	(((v) & 0x07) << 9)	/* 11:9  */
#define ACTIM_CTRLA_TDPL(v)	(((v) & 0x07) << 6)	/*  8:6  */
#define ACTIM_CTRLA_TDAL(v)	(v & 0x1F)		/*  4:0  */

#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal)	\
		ACTIM_CTRLA_TRFC(trfc)	|	\
		ACTIM_CTRLA_TRC(trc)	|	\
		ACTIM_CTRLA_TRAS(tras)	|	\
		ACTIM_CTRLA_TRP(trp)	|	\
		ACTIM_CTRLA_TRCD(trcd)	|	\
		ACTIM_CTRLA_TRRD(trrd)	|	\
		ACTIM_CTRLA_TDPL(tdpl)	|	\
		ACTIM_CTRLA_TDAL(tdal)

/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
#define ACTIM_CTRLB_TWTR(v)	(((v) & 0x03) << 16)	/* 17:16 */
#define ACTIM_CTRLB_TCKE(v)	(((v) & 0x07) << 12)	/* 14:12 */
#define ACTIM_CTRLB_TXP(v)	(((v) & 0x07) << 8)	/* 10:8  */
#define ACTIM_CTRLB_TXSR(v)	(v & 0xFF)		/*  7:0  */

#define ACTIM_CTRLB(twtr, tcke, txp, txsr)		\
		ACTIM_CTRLB_TWTR(twtr)	|	\
		ACTIM_CTRLB_TCKE(tcke)	|	\
		ACTIM_CTRLB_TXP(txp)	|	\
		ACTIM_CTRLB_TXSR(txsr)

/*
 * Values used in the MCFG register.  Only values we use today
 * are defined and the rest can be found in the TRM.  Unless otherwise
 * noted all fields are one bit.
 */
#define V_MCFG_RAMTYPE_DDR		(0x1)
#define V_MCFG_DEEPPD_EN		(0x1 << 3)
#define V_MCFG_B32NOT16_32		(0x1 << 4)
#define V_MCFG_BANKALLOCATION_RBC	(0x2 << 6)		/* 6:7 */
#define V_MCFG_RAMSIZE(ramsize)		((((ramsize) >> 20)/2) << 8) /* 8:17 */
#define V_MCFG_ADDRMUXLEGACY_FLEX	(0x1 << 19)
#define V_MCFG_CASWIDTH(caswidth)	(((caswidth)-5) << 20)	/* 20:22 */
#define V_MCFG_CASWIDTH_10B		V_MCFG_CASWIDTH(10)
#define V_MCFG_RASWIDTH(raswidth)	(((raswidth)-11) << 24)	/* 24:26 */

/* Macro to construct MCFG */
#define MCFG(ramsize, raswidth)						\
		V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B |	\
		V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) |	\
		V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 |	\
		V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR

/* Hynix part of Overo (165MHz optimized) 6.06ns */
#define HYNIX_TDAL_165   6
#define HYNIX_TDPL_165   3
#define HYNIX_TRRD_165   2
#define HYNIX_TRCD_165   3
#define HYNIX_TRP_165    3
#define HYNIX_TRAS_165   7
#define HYNIX_TRC_165   10
#define HYNIX_TRFC_165  21
#define HYNIX_V_ACTIMA_165	\
		ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165,	\
				HYNIX_TRAS_165, HYNIX_TRP_165,	\
				HYNIX_TRCD_165, HYNIX_TRRD_165,	\
				HYNIX_TDPL_165, HYNIX_TDAL_165)

#define HYNIX_TWTR_165   1
#define HYNIX_TCKE_165   1
#define HYNIX_TXP_165    2
#define HYNIX_XSR_165    24
#define HYNIX_V_ACTIMB_165	\
		ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165,	\
				HYNIX_TXP_165, HYNIX_XSR_165)

#define HYNIX_RASWIDTH_165	13
#define HYNIX_V_MCFG_165(size)	MCFG((size), HYNIX_RASWIDTH_165)

/* Hynix part of AM/DM37xEVM (200MHz optimized) */
#define HYNIX_TDAL_200		6
#define HYNIX_TDPL_200		3
#define HYNIX_TRRD_200		2
#define HYNIX_TRCD_200		4
#define HYNIX_TRP_200		3
#define HYNIX_TRAS_200		8
#define HYNIX_TRC_200		11
#define HYNIX_TRFC_200		18
#define HYNIX_V_ACTIMA_200	\
		ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200,	\
				HYNIX_TRAS_200, HYNIX_TRP_200,	\
				HYNIX_TRCD_200, HYNIX_TRRD_200,	\
				HYNIX_TDPL_200, HYNIX_TDAL_200)

#define HYNIX_TWTR_200		2
#define HYNIX_TCKE_200		1
#define HYNIX_TXP_200		1
#define HYNIX_XSR_200		28
#define HYNIX_V_ACTIMB_200	\
		ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200,	\
				HYNIX_TXP_200, HYNIX_XSR_200)

#define HYNIX_RASWIDTH_200	14
#define HYNIX_V_MCFG_200(size)	MCFG((size), HYNIX_RASWIDTH_200)

/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
#define INFINEON_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
					/* 15/6 + 18/6 = 5.5 -> 6	*/
#define INFINEON_TDPL_165	3	/* 15/6 = 2.5 -> 3 (Twr)	*/
#define INFINEON_TRRD_165	2	/* 12/6 = 2			*/
#define INFINEON_TRCD_165	3	/* 18/6 = 3			*/
#define INFINEON_TRP_165	3	/* 18/6 = 3			*/
#define INFINEON_TRAS_165	7	/* 42/6 = 7			*/
#define INFINEON_TRC_165	10	/* 60/6 = 10			*/
#define INFINEON_TRFC_165	12	/* 72/6 = 12			*/

#define INFINEON_V_ACTIMA_165	\
		ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165,	\
				INFINEON_TRAS_165, INFINEON_TRP_165,	\
				INFINEON_TRCD_165, INFINEON_TRRD_165,	\
				INFINEON_TDPL_165, INFINEON_TDAL_165)

#define INFINEON_TWTR_165	1
#define INFINEON_TCKE_165	2
#define INFINEON_TXP_165	2
#define INFINEON_XSR_165	20	/* 120/6 = 20	*/

#define INFINEON_V_ACTIMB_165	\
		ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165,	\
				INFINEON_TXP_165, INFINEON_XSR_165)

/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
#define MICRON_TDAL_165		6	/* Twr/Tck + Trp/tck		*/
					/* 15/6 + 18/6 = 5.5 -> 6	*/
#define MICRON_TDPL_165		3	/* 15/6 = 2.5 -> 3 (Twr)	*/
#define MICRON_TRRD_165		2	/* 12/6 = 2			*/
#define MICRON_TRCD_165		3	/* 18/6 = 3			*/
#define MICRON_TRP_165		3	/* 18/6 = 3			*/
#define MICRON_TRAS_165		7	/* 42/6 = 7			*/
#define MICRON_TRC_165		10	/* 60/6 = 10			*/
#define MICRON_TRFC_165		21	/* 125/6 = 21			*/

#define MICRON_V_ACTIMA_165	\
		ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165,		\
				MICRON_TRAS_165, MICRON_TRP_165,	\
				MICRON_TRCD_165, MICRON_TRRD_165,	\
				MICRON_TDPL_165, MICRON_TDAL_165)

#define MICRON_TWTR_165		1
#define MICRON_TCKE_165		1
#define MICRON_XSR_165		23	/* 138/6 = 23		*/
#define MICRON_TXP_165		5	/* 25/6 = 4.1 => ~5	*/

#define MICRON_V_ACTIMB_165	\
		ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165,	\
				MICRON_TXP_165,	MICRON_XSR_165)

#define MICRON_RASWIDTH_165	13
#define MICRON_V_MCFG_165(size)	MCFG((size), MICRON_RASWIDTH_165)

#define MICRON_BL_165			0x2
#define MICRON_SIL_165			0x0
#define MICRON_CASL_165			0x3
#define MICRON_WBST_165			0x0
#define MICRON_V_MR_165			((MICRON_WBST_165 << 9) | \
		(MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
		(MICRON_BL_165))

/* Micron part (200MHz optimized) 5 ns */
#define MICRON_TDAL_200		6
#define MICRON_TDPL_200		3
#define MICRON_TRRD_200		2
#define MICRON_TRCD_200		3
#define MICRON_TRP_200		3
#define MICRON_TRAS_200		8
#define MICRON_TRC_200		11
#define MICRON_TRFC_200		15
#define MICRON_V_ACTIMA_200	\
		ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200,		\
				MICRON_TRAS_200, MICRON_TRP_200,	\
				MICRON_TRCD_200, MICRON_TRRD_200,	\
				MICRON_TDPL_200, MICRON_TDAL_200)

#define MICRON_TWTR_200		2
#define MICRON_TCKE_200		4
#define MICRON_TXP_200		2
#define MICRON_XSR_200		23
#define MICRON_V_ACTIMB_200	\
		ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200,	\
				MICRON_TXP_200,	MICRON_XSR_200)

#define MICRON_RASWIDTH_200	14
#define MICRON_V_MCFG_200(size)	MCFG((size), MICRON_RASWIDTH_200)

/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
#define NUMONYX_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
					/* 15/6 + 18/6 = 5.5 -> 6	*/
#define NUMONYX_TDPL_165	3	/* 15/6 = 2.5 -> 3 (Twr)	*/
#define NUMONYX_TRRD_165	2	/* 12/6 = 2			*/
#define NUMONYX_TRCD_165	4	/* 22.5/6 = 3.75 -> 4		*/
#define NUMONYX_TRP_165		3	/* 18/6 = 3			*/
#define NUMONYX_TRAS_165	7	/* 42/6 = 7			*/
#define NUMONYX_TRC_165		10	/* 60/6 = 10			*/
#define NUMONYX_TRFC_165	24	/* 140/6 = 23.3 -> 24		*/

#define NUMONYX_V_ACTIMA_165	\
		ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165,		\
				NUMONYX_TRAS_165, NUMONYX_TRP_165,	\
				NUMONYX_TRCD_165, NUMONYX_TRRD_165,	\
				NUMONYX_TDPL_165, NUMONYX_TDAL_165)

#define NUMONYX_TWTR_165	2
#define NUMONYX_TCKE_165	2
#define NUMONYX_TXP_165		3	/* 200/6 =  33.3 -> 34	*/
#define NUMONYX_XSR_165		34	/* 1.0 + 1.1 = 2.1 -> 3	*/

#define NUMONYX_V_ACTIMB_165	\
		ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165,	\
				NUMONYX_TXP_165, NUMONYX_XSR_165)

#define NUMONYX_RASWIDTH_165		15
#define NUMONYX_V_MCFG_165(size)	MCFG((size), NUMONYX_RASWIDTH_165)

/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
#define NUMONYX_TDAL_200	6	/* Twr/Tck + Trp/tck		*/
					/* 15/5 + 15/5 = 3 + 3 -> 6	*/
#define NUMONYX_TDPL_200	3	/* 15/5 = 3 -> 3 (Twr)	        */
#define NUMONYX_TRRD_200	2	/* 10/5 = 2			*/
#define NUMONYX_TRCD_200	4	/* 16.2/5 = 3.24 -> 4		*/
#define NUMONYX_TRP_200		3	/* 15/5 = 3			*/
#define NUMONYX_TRAS_200	8	/* 40/5 = 8			*/
#define NUMONYX_TRC_200		11	/* 55/5 = 11			*/
#define NUMONYX_TRFC_200        28      /* 140/5 = 28                   */

#define NUMONYX_V_ACTIMA_200	\
		ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200,		\
				NUMONYX_TRAS_200, NUMONYX_TRP_200,	\
				NUMONYX_TRCD_200, NUMONYX_TRRD_200,	\
				NUMONYX_TDPL_200, NUMONYX_TDAL_200)

#define NUMONYX_TWTR_200	2
#define NUMONYX_TCKE_200	2
#define NUMONYX_TXP_200		3
#define NUMONYX_XSR_200		40

#define NUMONYX_V_ACTIMB_200	\
		ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200,	\
				NUMONYX_TXP_200, NUMONYX_XSR_200)

#define NUMONYX_RASWIDTH_200		15
#define NUMONYX_V_MCFG_200(size)	MCFG((size), NUMONYX_RASWIDTH_200)

/*
 * GPMC settings -
 * Definitions is as per the following format
 * #define <PART>_GPMC_CONFIG<x> <value>
 * Where:
 * PART is the part name e.g. STNOR - Intel Strata Flash
 * x is GPMC config registers from 1 to 6 (there will be 6 macros)
 * Value is corresponding value
 *
 * For every valid PRCM configuration there should be only one definition of
 * the same. if values are independent of the board, this definition will be
 * present in this file if values are dependent on the board, then this should
 * go into corresponding mem-boardName.h file
 *
 * Currently valid part Names are (PART):
 * STNOR - Intel Strata Flash
 * SMNAND - Samsung NAND
 * MPDB - H4 MPDB board
 * SBNOR - Sibley NOR
 * MNAND - Micron Large page x16 NAND
 * ONNAND - Samsung One NAND
 *
 * include/configs/file.h contains the defn - for all CS we are interested
 * #define OMAP34XX_GPMC_CSx PART
 * #define OMAP34XX_GPMC_CSx_SIZE Size
 * #define OMAP34XX_GPMC_CSx_MAP Map
 * Where:
 * x - CS number
 * PART - Part Name as defined above
 * SIZE - how big is the mapping to be
 *   GPMC_SIZE_128M - 0x8
 *   GPMC_SIZE_64M  - 0xC
 *   GPMC_SIZE_32M  - 0xE
 *   GPMC_SIZE_16M  - 0xF
 * MAP  - Map this CS to which address(GPMC address space)- Absolute address
 *   >>24 before being used.
 */
#define GPMC_SIZE_128M	0x8
#define GPMC_SIZE_64M	0xC
#define GPMC_SIZE_32M	0xE
#define GPMC_SIZE_16M	0xF

#define GPMC_BASEADDR_MASK	0x3F

#define GPMC_CS_ENABLE		0x1

#define SMNAND_GPMC_CONFIG1	0x00000800
#define SMNAND_GPMC_CONFIG2	0x00141400
#define SMNAND_GPMC_CONFIG3	0x00141400
#define SMNAND_GPMC_CONFIG4	0x0F010F01
#define SMNAND_GPMC_CONFIG5	0x010C1414
#define SMNAND_GPMC_CONFIG6	0x1F0F0A80
#define SMNAND_GPMC_CONFIG7	0x00000C44

#define M_NAND_GPMC_CONFIG1	0x00001800
#define M_NAND_GPMC_CONFIG2	0x00141400
#define M_NAND_GPMC_CONFIG3	0x00141400
#define M_NAND_GPMC_CONFIG4	0x0F010F01
#define M_NAND_GPMC_CONFIG5	0x010C1414
#define M_NAND_GPMC_CONFIG6	0x1f0f0A80
#define M_NAND_GPMC_CONFIG7	0x00000C44

#define STNOR_GPMC_CONFIG1	0x3
#define STNOR_GPMC_CONFIG2	0x00151501
#define STNOR_GPMC_CONFIG3	0x00060602
#define STNOR_GPMC_CONFIG4	0x11091109
#define STNOR_GPMC_CONFIG5	0x01141F1F
#define STNOR_GPMC_CONFIG6	0x000004c4

#define SIBNOR_GPMC_CONFIG1	0x1200
#define SIBNOR_GPMC_CONFIG2	0x001f1f00
#define SIBNOR_GPMC_CONFIG3	0x00080802
#define SIBNOR_GPMC_CONFIG4	0x1C091C09
#define SIBNOR_GPMC_CONFIG5	0x01131F1F
#define SIBNOR_GPMC_CONFIG6	0x1F0F03C2

#define SDPV2_MPDB_GPMC_CONFIG1	0x00611200
#define SDPV2_MPDB_GPMC_CONFIG2	0x001F1F01
#define SDPV2_MPDB_GPMC_CONFIG3	0x00080803
#define SDPV2_MPDB_GPMC_CONFIG4	0x1D091D09
#define SDPV2_MPDB_GPMC_CONFIG5	0x041D1F1F
#define SDPV2_MPDB_GPMC_CONFIG6	0x1D0904C4

#define MPDB_GPMC_CONFIG1	0x00011000
#define MPDB_GPMC_CONFIG2	0x001f1f01
#define MPDB_GPMC_CONFIG3	0x00080803
#define MPDB_GPMC_CONFIG4	0x1c0b1c0a
#define MPDB_GPMC_CONFIG5	0x041f1F1F
#define MPDB_GPMC_CONFIG6	0x1F0F04C4

#define P2_GPMC_CONFIG1	0x0
#define P2_GPMC_CONFIG2	0x0
#define P2_GPMC_CONFIG3	0x0
#define P2_GPMC_CONFIG4	0x0
#define P2_GPMC_CONFIG5	0x0
#define P2_GPMC_CONFIG6	0x0

#define ONENAND_GPMC_CONFIG1	0x00001200
#define ONENAND_GPMC_CONFIG2	0x000F0F01
#define ONENAND_GPMC_CONFIG3	0x00030301
#define ONENAND_GPMC_CONFIG4	0x0F040F04
#define ONENAND_GPMC_CONFIG5	0x010F1010
#define ONENAND_GPMC_CONFIG6	0x1F060000

#define NET_GPMC_CONFIG1	0x00001000
#define NET_GPMC_CONFIG2	0x001e1e01
#define NET_GPMC_CONFIG3	0x00080300
#define NET_GPMC_CONFIG4	0x1c091c09
#define NET_GPMC_CONFIG5	0x04181f1f
#define NET_GPMC_CONFIG6	0x00000FCF
#define NET_GPMC_CONFIG7	0x00000f6c

/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS	8
/* max number of GPMC regs */
#define GPMC_MAX_REG	7

#define PISMO1_NOR	1
#define PISMO1_NAND	2
#define PISMO2_CS0	3
#define PISMO2_CS1	4
#define PISMO1_ONENAND	5
#define DBG_MPDB	6
#define PISMO2_NAND_CS0 7
#define PISMO2_NAND_CS1 8

/* make it readable for the gpmc_init */
#define PISMO1_NOR_BASE		FLASH_BASE
#define PISMO1_NAND_BASE	NAND_BASE
#define PISMO2_CS0_BASE		PISMO2_MAP1
#define PISMO1_ONEN_BASE	ONENAND_MAP
#define DBG_MPDB_BASE		DEBUG_BASE

#ifndef __ASSEMBLY__

/* Function prototypes */
void mem_init(void);

u32 is_mem_sdr(void);
u32 mem_ok(u32 cs);

u32 get_sdr_cs_size(u32);
u32 get_sdr_cs_offset(u32);

#endif	/* __ASSEMBLY__ */

#endif /* endif _MEM_H_ */
Commit	Line	Data
a8b64505 DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments, <www.ti.com>
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
a8b64505 DB	7	*/
	8
	9	#ifndef _MEM_H_
	10	#define _MEM_H_
	11
	12	#define CS0 0x0
	13	#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
	14
	15	#ifndef __ASSEMBLY__
97a099ea	16	enum {
a8b64505 DB	17	STACKED = 0,
	18	IP_DDR = 1,
	19	COMBO_DDR = 2,
	20	IP_SDR = 3,
97a099ea	21	};
a8b64505 DB	22	#endif /* __ASSEMBLY__ */
	23
	24	#define EARLY_INIT 1
	25
14ca3dee TR	26	/*
	27	* For a full explanation of these registers and values please see
	28	* the Technical Reference Manual (TRM) for any of the processors in
	29	* this family.
	30	*/
	31
a8b64505	32	/* Slower full frequency range default timings for x32 operation*/
169a4c80 NM	33	#define SDRC_SHARING 0x00000100
169a4c80 NM	34	#define SDRC_MR_0_SDR 0x00000031
a8b64505	35
1be1433b TR	36	/*
	37	* SDRC autorefresh control values. This register consists of autorefresh
	38	* enable at bits 0:1 and an autorefresh counter value in bits 8:23. The
	39	* counter is a result of ( tREFI / tCK ) - 50.
	40	*/
	41	#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
	42	#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
	43	#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
	44	#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
	45
a8b64505 DB	46	#define DLL_OFFSET 0
	47	#define DLL_WRITEDDRCLKX2DIS 1
	48	#define DLL_ENADLL 1
	49	#define DLL_LOCKDLL 0
	50	#define DLL_DLLPHASE_72 0
	51	#define DLL_DLLPHASE_90 1
	52
	53	/* rkw - need to find of 90/72 degree recommendation for speed like before */
	54	#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) \| \
	55	(DLL_LOCKDLL << 2) \| (DLL_DLLPHASE_90 << 1))
	56
e3596e35 SP	57	/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
	58	#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */
	59	#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */
	60	#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */
	61	#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */
	62	#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */
	63	#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */
	64	#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
	65	#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */
	66
9540c7e9 PB	67	#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \
	68	ACTIM_CTRLA_TRFC(trfc) \| \
	69	ACTIM_CTRLA_TRC(trc) \| \
	70	ACTIM_CTRLA_TRAS(tras) \| \
	71	ACTIM_CTRLA_TRP(trp) \| \
	72	ACTIM_CTRLA_TRCD(trcd) \| \
	73	ACTIM_CTRLA_TRRD(trrd) \| \
	74	ACTIM_CTRLA_TDPL(tdpl) \| \
	75	ACTIM_CTRLA_TDAL(tdal)
e3596e35 SP	76
	77	/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
	78	#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */
	79	#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */
	80	#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */
	81	#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */
	82
9540c7e9 PB	83	#define ACTIM_CTRLB(twtr, tcke, txp, txsr) \
	84	ACTIM_CTRLB_TWTR(twtr) \| \
	85	ACTIM_CTRLB_TCKE(tcke) \| \
	86	ACTIM_CTRLB_TXP(txp) \| \
	87	ACTIM_CTRLB_TXSR(txsr)
e3596e35	88
14ca3dee TR	89	/*
	90	* Values used in the MCFG register. Only values we use today
	91	* are defined and the rest can be found in the TRM. Unless otherwise
	92	* noted all fields are one bit.
	93	*/
	94	#define V_MCFG_RAMTYPE_DDR (0x1)
	95	#define V_MCFG_DEEPPD_EN (0x1 << 3)
	96	#define V_MCFG_B32NOT16_32 (0x1 << 4)
9540c7e9 PB	97	#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
9540c7e9 PB	98	#define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8) /* 8:17 */
14ca3dee	99	#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
9540c7e9 PB	100	#define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */
	101	#define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10)
	102	#define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */
14ca3dee TR	103
14ca3dee TR	104	/* Macro to construct MCFG */
9540c7e9 PB	105	#define MCFG(ramsize, raswidth) \
	106	V_MCFG_RASWIDTH(raswidth) \| V_MCFG_CASWIDTH_10B \| \
	107	V_MCFG_ADDRMUXLEGACY_FLEX \| V_MCFG_RAMSIZE(ramsize) \| \
	108	V_MCFG_BANKALLOCATION_RBC \| V_MCFG_B32NOT16_32 \| \
	109	V_MCFG_DEEPPD_EN \| V_MCFG_RAMTYPE_DDR
14ca3dee	110
137703b8 AM	111	/* Hynix part of Overo (165MHz optimized) 6.06ns */
	112	#define HYNIX_TDAL_165 6
	113	#define HYNIX_TDPL_165 3
	114	#define HYNIX_TRRD_165 2
	115	#define HYNIX_TRCD_165 3
	116	#define HYNIX_TRP_165 3
	117	#define HYNIX_TRAS_165 7
	118	#define HYNIX_TRC_165 10
	119	#define HYNIX_TRFC_165 21
	120	#define HYNIX_V_ACTIMA_165 \
	121	ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \
	122	HYNIX_TRAS_165, HYNIX_TRP_165, \
	123	HYNIX_TRCD_165, HYNIX_TRRD_165, \
	124	HYNIX_TDPL_165, HYNIX_TDAL_165)
	125
	126	#define HYNIX_TWTR_165 1
	127	#define HYNIX_TCKE_165 1
	128	#define HYNIX_TXP_165 2
	129	#define HYNIX_XSR_165 24
	130	#define HYNIX_V_ACTIMB_165 \
	131	ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \
	132	HYNIX_TXP_165, HYNIX_XSR_165)
	133
9540c7e9	134	#define HYNIX_RASWIDTH_165 13
137703b8 AM	135	#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165)
137703b8 AM	136
673283f3 TR	137	/* Hynix part of AM/DM37xEVM (200MHz optimized) */
	138	#define HYNIX_TDAL_200 6
	139	#define HYNIX_TDPL_200 3
	140	#define HYNIX_TRRD_200 2
	141	#define HYNIX_TRCD_200 4
	142	#define HYNIX_TRP_200 3
	143	#define HYNIX_TRAS_200 8
	144	#define HYNIX_TRC_200 11
	145	#define HYNIX_TRFC_200 18
	146	#define HYNIX_V_ACTIMA_200 \
	147	ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
	148	HYNIX_TRAS_200, HYNIX_TRP_200, \
	149	HYNIX_TRCD_200, HYNIX_TRRD_200, \
	150	HYNIX_TDPL_200, HYNIX_TDAL_200)
	151
	152	#define HYNIX_TWTR_200 2
	153	#define HYNIX_TCKE_200 1
	154	#define HYNIX_TXP_200 1
	155	#define HYNIX_XSR_200 28
	156	#define HYNIX_V_ACTIMB_200 \
	157	ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
	158	HYNIX_TXP_200, HYNIX_XSR_200)
	159
9540c7e9	160	#define HYNIX_RASWIDTH_200 14
673283f3 TR	161	#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
673283f3 TR	162
2c5b8756 SP	163	/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
	164	#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
	165	/* 15/6 + 18/6 = 5.5 -> 6 */
	166	#define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
	167	#define INFINEON_TRRD_165 2 /* 12/6 = 2 */
	168	#define INFINEON_TRCD_165 3 /* 18/6 = 3 */
	169	#define INFINEON_TRP_165 3 /* 18/6 = 3 */
	170	#define INFINEON_TRAS_165 7 /* 42/6 = 7 */
	171	#define INFINEON_TRC_165 10 /* 60/6 = 10 */
	172	#define INFINEON_TRFC_165 12 /* 72/6 = 12 */
e3596e35 SP	173
	174	#define INFINEON_V_ACTIMA_165 \
	175	ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
	176	INFINEON_TRAS_165, INFINEON_TRP_165, \
	177	INFINEON_TRCD_165, INFINEON_TRRD_165, \
	178	INFINEON_TDPL_165, INFINEON_TDAL_165)
a8b64505	179
30563a04 NM	180	#define INFINEON_TWTR_165 1
	181	#define INFINEON_TCKE_165 2
	182	#define INFINEON_TXP_165 2
2c5b8756	183	#define INFINEON_XSR_165 20 /* 120/6 = 20 */
e3596e35 SP	184
	185	#define INFINEON_V_ACTIMB_165 \
	186	ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
	187	INFINEON_TXP_165, INFINEON_XSR_165)
30563a04	188
2c5b8756 SP	189	/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
	190	#define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
	191	/* 15/6 + 18/6 = 5.5 -> 6 */
	192	#define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
	193	#define MICRON_TRRD_165 2 /* 12/6 = 2 */
	194	#define MICRON_TRCD_165 3 /* 18/6 = 3 */
	195	#define MICRON_TRP_165 3 /* 18/6 = 3 */
	196	#define MICRON_TRAS_165 7 /* 42/6 = 7 */
	197	#define MICRON_TRC_165 10 /* 60/6 = 10 */
	198	#define MICRON_TRFC_165 21 /* 125/6 = 21 */
e3596e35 SP	199
	200	#define MICRON_V_ACTIMA_165 \
	201	ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
	202	MICRON_TRAS_165, MICRON_TRP_165, \
	203	MICRON_TRCD_165, MICRON_TRRD_165, \
	204	MICRON_TDPL_165, MICRON_TDAL_165)
30563a04 NM	205
	206	#define MICRON_TWTR_165 1
	207	#define MICRON_TCKE_165 1
2c5b8756 SP	208	#define MICRON_XSR_165 23 /* 138/6 = 23 */
2c5b8756 SP	209	#define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
e3596e35 SP	210
	211	#define MICRON_V_ACTIMB_165 \
	212	ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
	213	MICRON_TXP_165, MICRON_XSR_165)
30563a04	214
9540c7e9	215	#define MICRON_RASWIDTH_165 13
fc41ba1e	216	#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165)
b88e4256	217
fc41ba1e TR	218	#define MICRON_BL_165 0x2
	219	#define MICRON_SIL_165 0x0
	220	#define MICRON_CASL_165 0x3
	221	#define MICRON_WBST_165 0x0
	222	#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) \| \
	223	(MICRON_CASL_165 << 4) \| (MICRON_SIL_165 << 3) \| \
	224	(MICRON_BL_165))
b88e4256	225
75c57a35 TR	226	/* Micron part (200MHz optimized) 5 ns */
	227	#define MICRON_TDAL_200 6
	228	#define MICRON_TDPL_200 3
	229	#define MICRON_TRRD_200 2
	230	#define MICRON_TRCD_200 3
	231	#define MICRON_TRP_200 3
	232	#define MICRON_TRAS_200 8
	233	#define MICRON_TRC_200 11
	234	#define MICRON_TRFC_200 15
	235	#define MICRON_V_ACTIMA_200 \
	236	ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \
	237	MICRON_TRAS_200, MICRON_TRP_200, \
	238	MICRON_TRCD_200, MICRON_TRRD_200, \
	239	MICRON_TDPL_200, MICRON_TDAL_200)
	240
	241	#define MICRON_TWTR_200 2
	242	#define MICRON_TCKE_200 4
	243	#define MICRON_TXP_200 2
	244	#define MICRON_XSR_200 23
	245	#define MICRON_V_ACTIMB_200 \
	246	ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \
	247	MICRON_TXP_200, MICRON_XSR_200)
	248
9540c7e9	249	#define MICRON_RASWIDTH_200 14
75c57a35 TR	250	#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
75c57a35 TR	251
2c5b8756 SP	252	/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
	253	#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
	254	/* 15/6 + 18/6 = 5.5 -> 6 */
	255	#define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
	256	#define NUMONYX_TRRD_165 2 /* 12/6 = 2 */
	257	#define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */
	258	#define NUMONYX_TRP_165 3 /* 18/6 = 3 */
	259	#define NUMONYX_TRAS_165 7 /* 42/6 = 7 */
	260	#define NUMONYX_TRC_165 10 /* 60/6 = 10 */
	261	#define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */
e3596e35 SP	262
	263	#define NUMONYX_V_ACTIMA_165 \
	264	ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
	265	NUMONYX_TRAS_165, NUMONYX_TRP_165, \
	266	NUMONYX_TRCD_165, NUMONYX_TRRD_165, \
	267	NUMONYX_TDPL_165, NUMONYX_TDAL_165)
84b66310	268
f883c5d8 SP	269	#define NUMONYX_TWTR_165 2
f883c5d8 SP	270	#define NUMONYX_TCKE_165 2
2c5b8756 SP	271	#define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
2c5b8756 SP	272	#define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */
e3596e35 SP	273
	274	#define NUMONYX_V_ACTIMB_165 \
	275	ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
	276	NUMONYX_TXP_165, NUMONYX_XSR_165)
84b66310	277
9540c7e9	278	#define NUMONYX_RASWIDTH_165 15
75c57a35 TR	279	#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
75c57a35 TR	280
41708a5d JMC	281	/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
	282	#define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */
	283	/* 15/5 + 15/5 = 3 + 3 -> 6 */
	284	#define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */
	285	#define NUMONYX_TRRD_200 2 /* 10/5 = 2 */
	286	#define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */
	287	#define NUMONYX_TRP_200 3 /* 15/5 = 3 */
	288	#define NUMONYX_TRAS_200 8 /* 40/5 = 8 */
	289	#define NUMONYX_TRC_200 11 /* 55/5 = 11 */
	290	#define NUMONYX_TRFC_200 28 /* 140/5 = 28 */
	291
	292	#define NUMONYX_V_ACTIMA_200 \
	293	ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \
	294	NUMONYX_TRAS_200, NUMONYX_TRP_200, \
	295	NUMONYX_TRCD_200, NUMONYX_TRRD_200, \
	296	NUMONYX_TDPL_200, NUMONYX_TDAL_200)
	297
	298	#define NUMONYX_TWTR_200 2
	299	#define NUMONYX_TCKE_200 2
	300	#define NUMONYX_TXP_200 3
	301	#define NUMONYX_XSR_200 40
	302
	303	#define NUMONYX_V_ACTIMB_200 \
	304	ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \
	305	NUMONYX_TXP_200, NUMONYX_XSR_200)
	306
	307	#define NUMONYX_RASWIDTH_200 15
	308	#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200)
	309
a8b64505 DB	310	/*
	311	* GPMC settings -
	312	* Definitions is as per the following format
	313	* #define <PART>_GPMC_CONFIG<x> <value>
	314	* Where:
	315	* PART is the part name e.g. STNOR - Intel Strata Flash
	316	* x is GPMC config registers from 1 to 6 (there will be 6 macros)
	317	* Value is corresponding value
	318	*
	319	* For every valid PRCM configuration there should be only one definition of
	320	* the same. if values are independent of the board, this definition will be
	321	* present in this file if values are dependent on the board, then this should
	322	* go into corresponding mem-boardName.h file
	323	*
	324	* Currently valid part Names are (PART):
	325	* STNOR - Intel Strata Flash
	326	* SMNAND - Samsung NAND
	327	* MPDB - H4 MPDB board
	328	* SBNOR - Sibley NOR
	329	* MNAND - Micron Large page x16 NAND
	330	* ONNAND - Samsung One NAND
	331	*
	332	* include/configs/file.h contains the defn - for all CS we are interested
	333	* #define OMAP34XX_GPMC_CSx PART
	334	* #define OMAP34XX_GPMC_CSx_SIZE Size
	335	* #define OMAP34XX_GPMC_CSx_MAP Map
	336	* Where:
	337	* x - CS number
	338	* PART - Part Name as defined above
	339	* SIZE - how big is the mapping to be
	340	* GPMC_SIZE_128M - 0x8
	341	* GPMC_SIZE_64M - 0xC
	342	* GPMC_SIZE_32M - 0xE
	343	* GPMC_SIZE_16M - 0xF
	344	* MAP - Map this CS to which address(GPMC address space)- Absolute address
	345	* >>24 before being used.
	346	*/
	347	#define GPMC_SIZE_128M 0x8
	348	#define GPMC_SIZE_64M 0xC
	349	#define GPMC_SIZE_32M 0xE
	350	#define GPMC_SIZE_16M 0xF
	351
b7eb9e78 TR	352	#define GPMC_BASEADDR_MASK 0x3F
	353
	354	#define GPMC_CS_ENABLE 0x1
	355
a8b64505 DB	356	#define SMNAND_GPMC_CONFIG1 0x00000800
	357	#define SMNAND_GPMC_CONFIG2 0x00141400
	358	#define SMNAND_GPMC_CONFIG3 0x00141400
	359	#define SMNAND_GPMC_CONFIG4 0x0F010F01
	360	#define SMNAND_GPMC_CONFIG5 0x010C1414
	361	#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
	362	#define SMNAND_GPMC_CONFIG7 0x00000C44
	363
	364	#define M_NAND_GPMC_CONFIG1 0x00001800
	365	#define M_NAND_GPMC_CONFIG2 0x00141400
	366	#define M_NAND_GPMC_CONFIG3 0x00141400
	367	#define M_NAND_GPMC_CONFIG4 0x0F010F01
	368	#define M_NAND_GPMC_CONFIG5 0x010C1414
	369	#define M_NAND_GPMC_CONFIG6 0x1f0f0A80
	370	#define M_NAND_GPMC_CONFIG7 0x00000C44
	371
	372	#define STNOR_GPMC_CONFIG1 0x3
	373	#define STNOR_GPMC_CONFIG2 0x00151501
	374	#define STNOR_GPMC_CONFIG3 0x00060602
	375	#define STNOR_GPMC_CONFIG4 0x11091109
	376	#define STNOR_GPMC_CONFIG5 0x01141F1F
	377	#define STNOR_GPMC_CONFIG6 0x000004c4
	378
	379	#define SIBNOR_GPMC_CONFIG1 0x1200
	380	#define SIBNOR_GPMC_CONFIG2 0x001f1f00
	381	#define SIBNOR_GPMC_CONFIG3 0x00080802
	382	#define SIBNOR_GPMC_CONFIG4 0x1C091C09
	383	#define SIBNOR_GPMC_CONFIG5 0x01131F1F
	384	#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
	385
	386	#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
	387	#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
	388	#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
	389	#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
	390	#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
	391	#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
	392
	393	#define MPDB_GPMC_CONFIG1 0x00011000
	394	#define MPDB_GPMC_CONFIG2 0x001f1f01
	395	#define MPDB_GPMC_CONFIG3 0x00080803
	396	#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
	397	#define MPDB_GPMC_CONFIG5 0x041f1F1F
	398	#define MPDB_GPMC_CONFIG6 0x1F0F04C4
	399
	400	#define P2_GPMC_CONFIG1 0x0
	401	#define P2_GPMC_CONFIG2 0x0
	402	#define P2_GPMC_CONFIG3 0x0
	403	#define P2_GPMC_CONFIG4 0x0
	404	#define P2_GPMC_CONFIG5 0x0
	405	#define P2_GPMC_CONFIG6 0x0
	406
	407	#define ONENAND_GPMC_CONFIG1 0x00001200
	408	#define ONENAND_GPMC_CONFIG2 0x000F0F01
	409	#define ONENAND_GPMC_CONFIG3 0x00030301
	410	#define ONENAND_GPMC_CONFIG4 0x0F040F04
	411	#define ONENAND_GPMC_CONFIG5 0x010F1010
	412	#define ONENAND_GPMC_CONFIG6 0x1F060000
	413
	414	#define NET_GPMC_CONFIG1 0x00001000
	415	#define NET_GPMC_CONFIG2 0x001e1e01
	416	#define NET_GPMC_CONFIG3 0x00080300
	417	#define NET_GPMC_CONFIG4 0x1c091c09
	418	#define NET_GPMC_CONFIG5 0x04181f1f
	419	#define NET_GPMC_CONFIG6 0x00000FCF
420	#define NET_GPMC_CONFIG7 0x00000f6c
421
422	/* max number of GPMC Chip Selects */
423	#define GPMC_MAX_CS 8
424	/* max number of GPMC regs */
425	#define GPMC_MAX_REG 7
426
427	#define PISMO1_NOR 1
428	#define PISMO1_NAND 2
429	#define PISMO2_CS0 3
430	#define PISMO2_CS1 4
431	#define PISMO1_ONENAND 5
432	#define DBG_MPDB 6
433	#define PISMO2_NAND_CS0 7
434	#define PISMO2_NAND_CS1 8
435
436	/* make it readable for the gpmc_init */
437	#define PISMO1_NOR_BASE FLASH_BASE
438	#define PISMO1_NAND_BASE NAND_BASE
439	#define PISMO2_CS0_BASE PISMO2_MAP1
440	#define PISMO1_ONEN_BASE ONENAND_MAP
441	#define DBG_MPDB_BASE DEBUG_BASE
442
cae377b5 VH	443	#ifndef __ASSEMBLY__
	444
	445	/* Function prototypes */
	446	void mem_init(void);
	447
	448	u32 is_mem_sdr(void);
	449	u32 mem_ok(u32 cs);
	450
	451	u32 get_sdr_cs_size(u32);
	452	u32 get_sdr_cs_offset(u32);
	453
	454	#endif /* __ASSEMBLY__ */
	455
a8b64505	456	#endif /* endif _MEM_H_ */