projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 07133f2e MV |
1 | /* |
| 2 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
| 3 | * | |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 07133f2e MV |
5 | */ |
| 6 | ||
| 7 | #ifndef __REGS_MMC_H__ | |
| 8 | #define __REGS_MMC_H__ | |
| 9 | ||
| 10 | #define MMC0_BASE 0x41100000 | |
| 11 | #define MMC1_BASE 0x42000000 | |
| 12 | ||
| 13 | int pxa_mmc_register(int card_index); | |
| 14 | ||
| 15 | struct pxa_mmc_regs { | |
| 16 | uint32_t strpcl; | |
| 17 | uint32_t stat; | |
| 18 | uint32_t clkrt; | |
| 19 | uint32_t spi; | |
| 20 | uint32_t cmdat; | |
| 21 | uint32_t resto; | |
| 22 | uint32_t rdto; | |
| 23 | uint32_t blklen; | |
| 24 | uint32_t nob; | |
| 25 | uint32_t prtbuf; | |
| 26 | uint32_t i_mask; | |
| 27 | uint32_t i_reg; | |
| 28 | uint32_t cmd; | |
| 29 | uint32_t argh; | |
| 30 | uint32_t argl; | |
| 31 | uint32_t res; | |
| 32 | uint32_t rxfifo; | |
| 33 | uint32_t txfifo; | |
| 34 | }; | |
| 35 | ||
| 36 | /* MMC_STRPCL */ | |
| 37 | #define MMC_STRPCL_STOP_CLK (1 << 0) | |
| 38 | #define MMC_STRPCL_START_CLK (1 << 1) | |
| 39 | ||
| 40 | /* MMC_STAT */ | |
| 41 | #define MMC_STAT_END_CMD_RES (1 << 13) | |
| 42 | #define MMC_STAT_PRG_DONE (1 << 12) | |
| 43 | #define MMC_STAT_DATA_TRAN_DONE (1 << 11) | |
| 44 | #define MMC_STAT_CLK_EN (1 << 8) | |
| 45 | #define MMC_STAT_RECV_FIFO_FULL (1 << 7) | |
| 46 | #define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) | |
| 47 | #define MMC_STAT_RES_CRC_ERROR (1 << 5) | |
| 48 | #define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) | |
| 49 | #define MMC_STAT_CRC_READ_ERROR (1 << 3) | |
| 50 | #define MMC_STAT_CRC_WRITE_ERROR (1 << 2) | |
| 51 | #define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) | |
| 52 | #define MMC_STAT_READ_TIME_OUT (1 << 0) | |
| 53 | ||
| 54 | /* MMC_CLKRT */ | |
| 55 | #define MMC_CLKRT_20MHZ 0 | |
| 56 | #define MMC_CLKRT_10MHZ 1 | |
| 57 | #define MMC_CLKRT_5MHZ 2 | |
| 58 | #define MMC_CLKRT_2_5MHZ 3 | |
| 59 | #define MMC_CLKRT_1_25MHZ 4 | |
| 60 | #define MMC_CLKRT_0_625MHZ 5 | |
| 61 | #define MMC_CLKRT_0_3125MHZ 6 | |
| 62 | ||
| 63 | /* MMC_SPI */ | |
| 64 | #define MMC_SPI_EN (1 << 0) | |
| 65 | #define MMC_SPI_CS_EN (1 << 2) | |
| 66 | #define MMC_SPI_CS_ADDRESS (1 << 3) | |
| 67 | #define MMC_SPI_CRC_ON (1 << 1) | |
| 68 | ||
| 69 | /* MMC_CMDAT */ | |
| 70 | #define MMC_CMDAT_SD_4DAT (1 << 8) | |
| 71 | #define MMC_CMDAT_MMC_DMA_EN (1 << 7) | |
| 72 | #define MMC_CMDAT_INIT (1 << 6) | |
| 73 | #define MMC_CMDAT_BUSY (1 << 5) | |
| 74 | #define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) | |
| 75 | #define MMC_CMDAT_STREAM (1 << 4) | |
| 76 | #define MMC_CMDAT_WRITE (1 << 3) | |
| 77 | #define MMC_CMDAT_DATA_EN (1 << 2) | |
| 78 | #define MMC_CMDAT_R0 0 | |
| 79 | #define MMC_CMDAT_R1 1 | |
| 80 | #define MMC_CMDAT_R2 2 | |
| 81 | #define MMC_CMDAT_R3 3 | |
| 82 | ||
| 83 | /* MMC_RESTO */ | |
| 84 | #define MMC_RES_TO_MAX_MASK 0x7f | |
| 85 | ||
| 86 | /* MMC_RDTO */ | |
| 87 | #define MMC_READ_TO_MAX_MASK 0xffff | |
| 88 | ||
| 89 | /* MMC_BLKLEN */ | |
| 90 | #define MMC_BLK_LEN_MAX_MASK 0x3ff | |
| 91 | ||
| 92 | /* MMC_PRTBUF */ | |
| 93 | #define MMC_PRTBUF_BUF_PART_FULL (1 << 0) | |
| 94 | ||
| 95 | /* MMC_I_MASK */ | |
| 96 | #define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) | |
| 97 | #define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) | |
| 98 | #define MMC_I_MASK_CLK_IS_OFF (1 << 4) | |
| 99 | #define MMC_I_MASK_STOP_CMD (1 << 3) | |
| 100 | #define MMC_I_MASK_END_CMD_RES (1 << 2) | |
| 101 | #define MMC_I_MASK_PRG_DONE (1 << 1) | |
| 102 | #define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) | |
| 103 | #define MMC_I_MASK_ALL 0x7f | |
| 104 | ||
| 105 | ||
| 106 | /* MMC_I_REG */ | |
| 107 | #define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) | |
| 108 | #define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) | |
| 109 | #define MMC_I_REG_CLK_IS_OFF (1 << 4) | |
| 110 | #define MMC_I_REG_STOP_CMD (1 << 3) | |
| 111 | #define MMC_I_REG_END_CMD_RES (1 << 2) | |
| 112 | #define MMC_I_REG_PRG_DONE (1 << 1) | |
| 113 | #define MMC_I_REG_DATA_TRAN_DONE (1 << 0) | |
| 114 | ||
| 115 | /* MMC_CMD */ | |
| 116 | #define MMC_CMD_INDEX_MAX 0x6f | |
| 117 | ||
| 118 | #define MMC_R1_IDLE_STATE 0x01 | |
| 119 | #define MMC_R1_ERASE_STATE 0x02 | |
| 120 | #define MMC_R1_ILLEGAL_CMD 0x04 | |
| 121 | #define MMC_R1_COM_CRC_ERR 0x08 | |
| 122 | #define MMC_R1_ERASE_SEQ_ERR 0x01 | |
| 123 | #define MMC_R1_ADDR_ERR 0x02 | |
| 124 | #define MMC_R1_PARAM_ERR 0x04 | |
| 125 | ||
| 126 | #define MMC_R1B_WP_ERASE_SKIP 0x0002 | |
| 127 | #define MMC_R1B_ERR 0x0004 | |
| 128 | #define MMC_R1B_CC_ERR 0x0008 | |
| 129 | #define MMC_R1B_CARD_ECC_ERR 0x0010 | |
| 130 | #define MMC_R1B_WP_VIOLATION 0x0020 | |
| 131 | #define MMC_R1B_ERASE_PARAM 0x0040 | |
| 132 | #define MMC_R1B_OOR 0x0080 | |
| 133 | #define MMC_R1B_IDLE_STATE 0x0100 | |
| 134 | #define MMC_R1B_ERASE_RESET 0x0200 | |
| 135 | #define MMC_R1B_ILLEGAL_CMD 0x0400 | |
| 136 | #define MMC_R1B_COM_CRC_ERR 0x0800 | |
| 137 | #define MMC_R1B_ERASE_SEQ_ERR 0x1000 | |
| 138 | #define MMC_R1B_ADDR_ERR 0x2000 | |
| 139 | #define MMC_R1B_PARAM_ERR 0x4000 | |
| 140 | ||
| 141 | #endif /* __REGS_MMC_H__ */ |