[people/ms/u-boot.git] / arch / arm / include / asm / arch-rockchip / clock.h

/*
 * (C) Copyright 2015 Google, Inc
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#ifndef _ASM_ARCH_CLOCK_H
#define _ASM_ARCH_CLOCK_H

/* define pll mode */
#define RKCLK_PLL_MODE_SLOW		0
#define RKCLK_PLL_MODE_NORMAL		1

enum {
	ROCKCHIP_SYSCON_NOC,
	ROCKCHIP_SYSCON_GRF,
	ROCKCHIP_SYSCON_SGRF,
	ROCKCHIP_SYSCON_PMU,
	ROCKCHIP_SYSCON_PMUGRF,
	ROCKCHIP_SYSCON_PMUSGRF,
	ROCKCHIP_SYSCON_CIC,
	ROCKCHIP_SYSCON_MSCH,
};

/* Standard Rockchip clock numbers */
enum rk_clk_id {
	CLK_OSC,
	CLK_ARM,
	CLK_DDR,
	CLK_CODEC,
	CLK_GENERAL,
	CLK_NEW,

	CLK_COUNT,
};

static inline int rk_pll_id(enum rk_clk_id clk_id)
{
	return clk_id - 1;
}

struct sysreset_reg {
	unsigned int glb_srst_fst_value;
	unsigned int glb_srst_snd_value;
};

/**
 * clk_get_divisor() - Calculate the required clock divisior
 *
 * Given an input rate and a required output_rate, calculate the Rockchip
 * divisor needed to achieve this.
 *
 * @input_rate:		Input clock rate in Hz
 * @output_rate:	Output clock rate in Hz
 * @return divisor register value to use
 */
static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
{
	uint clk_div;

	clk_div = input_rate / output_rate;
	clk_div = (clk_div + 1) & 0xfffe;

	return clk_div;
}

/**
 * rockchip_get_cru() - get a pointer to the clock/reset unit registers
 *
 * @return pointer to registers, or -ve error on error
 */
void *rockchip_get_cru(void);

/**
 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
 *
 * @return pointer to registers, or -ve error on error
 */
void *rockchip_get_pmucru(void);

struct rk3288_cru;
struct rk3288_grf;

void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);

int rockchip_get_clk(struct udevice **devp);

#endif
Commit	Line	Data
26ad30e9 SG	1	/*
	2	* (C) Copyright 2015 Google, Inc
	3	*
	4	* SPDX-License-Identifier: GPL-2.0
	5	*/
	6
	7	#ifndef _ASM_ARCH_CLOCK_H
	8	#define _ASM_ARCH_CLOCK_H
	9
	10	/* define pll mode */
	11	#define RKCLK_PLL_MODE_SLOW 0
	12	#define RKCLK_PLL_MODE_NORMAL 1
	13
	14	enum {
	15	ROCKCHIP_SYSCON_NOC,
	16	ROCKCHIP_SYSCON_GRF,
	17	ROCKCHIP_SYSCON_SGRF,
	18	ROCKCHIP_SYSCON_PMU,
c55e30eb	19	ROCKCHIP_SYSCON_PMUGRF,
2adb9812 KY	20	ROCKCHIP_SYSCON_PMUSGRF,
2adb9812 KY	21	ROCKCHIP_SYSCON_CIC,
168eef7a	22	ROCKCHIP_SYSCON_MSCH,
26ad30e9 SG	23	};
	24
	25	/* Standard Rockchip clock numbers */
	26	enum rk_clk_id {
	27	CLK_OSC,
	28	CLK_ARM,
	29	CLK_DDR,
	30	CLK_CODEC,
	31	CLK_GENERAL,
	32	CLK_NEW,
	33
	34	CLK_COUNT,
	35	};
	36
	37	static inline int rk_pll_id(enum rk_clk_id clk_id)
	38	{
	39	return clk_id - 1;
	40	}
	41
6ba54058 KY	42	struct sysreset_reg {
	43	unsigned int glb_srst_fst_value;
	44	unsigned int glb_srst_snd_value;
	45	};
	46
1b2fd5bf SG	47	/**
	48	* clk_get_divisor() - Calculate the required clock divisior
	49	*
	50	* Given an input rate and a required output_rate, calculate the Rockchip
	51	* divisor needed to achieve this.
	52	*
	53	* @input_rate: Input clock rate in Hz
	54	* @output_rate: Output clock rate in Hz
	55	* @return divisor register value to use
	56	*/
	57	static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
	58	{
	59	uint clk_div;
	60
	61	clk_div = input_rate / output_rate;
	62	clk_div = (clk_div + 1) & 0xfffe;
	63
	64	return clk_div;
	65	}
	66
26ad30e9 SG	67	/**
	68	* rockchip_get_cru() - get a pointer to the clock/reset unit registers
	69	*
	70	* @return pointer to registers, or -ve error on error
	71	*/
	72	void *rockchip_get_cru(void);
	73
5ae2fd97 KY	74	/**
	75	* rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
	76	*
	77	* @return pointer to registers, or -ve error on error
	78	*/
	79	void *rockchip_get_pmucru(void);
	80
dae594f2 SG	81	struct rk3288_cru;
	82	struct rk3288_grf;
	83
b339b5db	84	void rk3288_clk_configure_cpu(struct rk3288_cru cru, struct rk3288_grf grf);
dae594f2	85
a617c5d3 SG	86	int rockchip_get_clk(struct udevice **devp);
a617c5d3 SG	87
26ad30e9	88	#endif