[people/ms/u-boot.git] / arch / arm / include / asm / arch-spear / spr_misc.h

/*
 * (C) Copyright 2009
 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _SPR_MISC_H
#define _SPR_MISC_H

struct misc_regs {
	u32 auto_cfg_reg;	/* 0x0 */
	u32 armdbg_ctr_reg;	/* 0x4 */
	u32 pll1_cntl;		/* 0x8 */
	u32 pll1_frq;		/* 0xc */
	u32 pll1_mod;		/* 0x10 */
	u32 pll2_cntl;		/* 0x14 */
	u32 pll2_frq;		/* 0x18 */
	u32 pll2_mod;		/* 0x1C */
	u32 pll_ctr_reg;	/* 0x20 */
	u32 amba_clk_cfg;	/* 0x24 */
	u32 periph_clk_cfg;	/* 0x28 */
	u32 periph1_clken;	/* 0x2C */
	u32 soc_core_id;	/* 0x30 */
	u32 ras_clken;		/* 0x34 */
	u32 periph1_rst;	/* 0x38 */
	u32 periph2_rst;	/* 0x3C */
	u32 ras_rst;		/* 0x40 */
	u32 prsc1_clk_cfg;	/* 0x44 */
	u32 prsc2_clk_cfg;	/* 0x48 */
	u32 prsc3_clk_cfg;	/* 0x4C */
	u32 amem_cfg_ctrl;	/* 0x50 */
	u32 expi_clk_cfg;	/* 0x54 */
	u32 reserved_1;		/* 0x58 */
	u32 clcd_synth_clk;	/* 0x5C */
	u32 irda_synth_clk;	/* 0x60 */
	u32 uart_synth_clk;	/* 0x64 */
	u32 gmac_synth_clk;	/* 0x68 */
	u32 ras_synth1_clk;	/* 0x6C */
	u32 ras_synth2_clk;	/* 0x70 */
	u32 ras_synth3_clk;	/* 0x74 */
	u32 ras_synth4_clk;	/* 0x78 */
	u32 arb_icm_ml1;	/* 0x7C */
	u32 arb_icm_ml2;	/* 0x80 */
	u32 arb_icm_ml3;	/* 0x84 */
	u32 arb_icm_ml4;	/* 0x88 */
	u32 arb_icm_ml5;	/* 0x8C */
	u32 arb_icm_ml6;	/* 0x90 */
	u32 arb_icm_ml7;	/* 0x94 */
	u32 arb_icm_ml8;	/* 0x98 */
	u32 arb_icm_ml9;	/* 0x9C */
	u32 dma_src_sel;	/* 0xA0 */
	u32 uphy_ctr_reg;	/* 0xA4 */
	u32 gmac_ctr_reg;	/* 0xA8 */
	u32 port_bridge_ctrl;	/* 0xAC */
	u32 reserved_2[4];	/* 0xB0--0xBC */
	u32 prc1_ilck_ctrl_reg;	/* 0xC0 */
	u32 prc2_ilck_ctrl_reg;	/* 0xC4 */
	u32 prc3_ilck_ctrl_reg;	/* 0xC8 */
	u32 prc4_ilck_ctrl_reg;	/* 0xCC */
	u32 prc1_intr_ctrl_reg;	/* 0xD0 */
	u32 prc2_intr_ctrl_reg;	/* 0xD4 */
	u32 prc3_intr_ctrl_reg;	/* 0xD8 */
	u32 prc4_intr_ctrl_reg;	/* 0xDC */
	u32 powerdown_cfg_reg;	/* 0xE0 */
	u32 ddr_1v8_compensation;	/* 0xE4  */
	u32 ddr_2v5_compensation;	/* 0xE8 */
	u32 core_3v3_compensation;	/* 0xEC */
	u32 ddr_pad;		/* 0xF0 */
	u32 bist1_ctr_reg;	/* 0xF4 */
	u32 bist2_ctr_reg;	/* 0xF8 */
	u32 bist3_ctr_reg;	/* 0xFC */
	u32 bist4_ctr_reg;	/* 0x100 */
	u32 bist5_ctr_reg;	/* 0x104 */
	u32 bist1_rslt_reg;	/* 0x108 */
	u32 bist2_rslt_reg;	/* 0x10C */
	u32 bist3_rslt_reg;	/* 0x110 */
	u32 bist4_rslt_reg;	/* 0x114 */
	u32 bist5_rslt_reg;	/* 0x118 */
	u32 syst_error_reg;	/* 0x11C */
	u32 reserved_3[0x1FB8];	/* 0x120--0x7FFC */
	u32 ras_gpp1_in;	/* 0x8000 */
	u32 ras_gpp2_in;	/* 0x8004 */
	u32 ras_gpp1_out;	/* 0x8008 */
	u32 ras_gpp2_out;	/* 0x800C */
};

/* SYNTH_CLK value*/
#define SYNTH23			0x00020003

/* PLLx_FRQ value */
#if defined(CONFIG_SPEAR3XX)
#define FREQ_332		0xA600010C
#define FREQ_266		0x8500010C
#elif defined(CONFIG_SPEAR600)
#define FREQ_332		0xA600010F
#define FREQ_266		0x8500010F
#endif

/* PLL_CTR_REG   */
#define MEM_CLK_SEL_MSK		0x70000000
#define MEM_CLK_HCLK		0x00000000
#define MEM_CLK_2HCLK		0x10000000
#define MEM_CLK_PLL2		0x30000000

#define EXPI_CLK_CFG_LOW_COMPR	0x2000
#define EXPI_CLK_CFG_CLK_EN	0x0400
#define EXPI_CLK_CFG_RST	0x0200
#define EXPI_CLK_SYNT_EN	0x0010
#define EXPI_CLK_CFG_SEL_PLL2	0x0004
#define EXPI_CLK_CFG_INT_CLK_EN	0x0001

#define PLL2_CNTL_6UA		0x1c00
#define PLL2_CNTL_SAMPLE	0x0008
#define PLL2_CNTL_ENABLE	0x0004
#define PLL2_CNTL_RESETN	0x0002
#define PLL2_CNTL_LOCK		0x0001

/* AUTO_CFG_REG value */
#define MISC_SOCCFGMSK                  0x0000003F
#define MISC_SOCCFG30                   0x0000000C
#define MISC_SOCCFG31                   0x0000000D
#define MISC_NANDDIS			0x00020000

/* PERIPH_CLK_CFG value */
#define MISC_GPT3SYNTH			0x00000400
#define MISC_GPT4SYNTH			0x00000800
#define CONFIG_SPEAR_UART48M		0
#define CONFIG_SPEAR_UARTCLKMSK		(0x1 << 4)

/* PRSC_CLK_CFG value */
/*
 * Fout = Fin / (2^(N+1) * (M + 1))
 */
#define MISC_PRSC_N_1			0x00001000
#define MISC_PRSC_M_9			0x00000009
#define MISC_PRSC_N_4			0x00004000
#define MISC_PRSC_M_399			0x0000018F
#define MISC_PRSC_N_6			0x00006000
#define MISC_PRSC_M_2593		0x00000A21
#define MISC_PRSC_M_124			0x0000007C
#define MISC_PRSC_CFG			(MISC_PRSC_N_1 | MISC_PRSC_M_9)

/* PERIPH1_CLKEN, PERIPH1_RST value */
#define MISC_USBDENB			0x01000000
#define MISC_ETHENB			0x00800000
#define MISC_SMIENB			0x00200000
#define MISC_GPT3ENB			0x00010000
#define MISC_GPIO4ENB			0x00002000
#define MISC_GPT2ENB			0x00000800
#define MISC_FSMCENB			0x00000200
#define MISC_I2CENB			0x00000080
#define MISC_SSP2ENB			0x00000070
#define MISC_UART0ENB			0x00000008

/*   PERIPH_CLK_CFG   */
#define  XTALTIMEEN		0x00000001
#define  PLLTIMEEN		0x00000002
#define  CLCDCLK_SYNTH		0x00000000
#define  CLCDCLK_48MHZ		0x00000004
#define  CLCDCLK_EXT		0x00000008
#define  UARTCLK_MASK		(0x1 << 4)
#define  UARTCLK_48MHZ		0x00000000
#define  UARTCLK_SYNTH		0x00000010
#define  IRDACLK_48MHZ		0x00000000
#define  IRDACLK_SYNTH		0x00000020
#define  IRDACLK_EXT		0x00000040
#define  RTC_DISABLE		0x00000080
#define  GPT1CLK_48MHZ		0x00000000
#define  GPT1CLK_SYNTH		0x00000100
#define  GPT2CLK_48MHZ		0x00000000
#define  GPT2CLK_SYNTH		0x00000200
#define  GPT3CLK_48MHZ		0x00000000
#define  GPT3CLK_SYNTH		0x00000400
#define  GPT4CLK_48MHZ		0x00000000
#define  GPT4CLK_SYNTH		0x00000800
#define  GPT5CLK_48MHZ		0x00000000
#define  GPT5CLK_SYNTH		0x00001000
#define  GPT1_FREEZE		0x00002000
#define  GPT2_FREEZE		0x00004000
#define  GPT3_FREEZE		0x00008000
#define  GPT4_FREEZE		0x00010000
#define  GPT5_FREEZE		0x00020000

/*  PERIPH1_CLKEN bits  */
#define PERIPH_ARM1_WE		0x00000001
#define PERIPH_ARM1		0x00000002
#define PERIPH_ARM2		0x00000004
#define PERIPH_UART1		0x00000008
#define PERIPH_UART2		0x00000010
#define PERIPH_SSP1		0x00000020
#define PERIPH_SSP2		0x00000040
#define PERIPH_I2C		0x00000080
#define PERIPH_JPEG		0x00000100
#define PERIPH_FSMC		0x00000200
#define PERIPH_FIRDA		0x00000400
#define PERIPH_GPT4		0x00000800
#define PERIPH_GPT5		0x00001000
#define PERIPH_GPIO4		0x00002000
#define PERIPH_SSP3		0x00004000
#define PERIPH_ADC		0x00008000
#define PERIPH_GPT3		0x00010000
#define PERIPH_RTC		0x00020000
#define PERIPH_GPIO3		0x00040000
#define PERIPH_DMA		0x00080000
#define PERIPH_ROM		0x00100000
#define PERIPH_SMI		0x00200000
#define PERIPH_CLCD		0x00400000
#define PERIPH_GMAC		0x00800000
#define PERIPH_USBD		0x01000000
#define PERIPH_USBH1		0x02000000
#define PERIPH_USBH2		0x04000000
#define PERIPH_MPMC		0x08000000
#define PERIPH_RAMW		0x10000000
#define PERIPH_MPMC_EN		0x20000000
#define PERIPH_MPMC_WE		0x40000000
#define PERIPH_MPMCMSK		0x60000000

#define PERIPH_CLK_ALL		0x0FFFFFF8
#define PERIPH_RST_ALL		0x00000004

/* DDR_PAD values */
#define DDR_PAD_CNF_MSK		0x0000ffff
#define DDR_PAD_SW_CONF		0x00060000
#define DDR_PAD_SSTL_SEL	0x00000001
#define DDR_PAD_DRAM_TYPE	0x00008000

/* DDR_COMP values */
#define DDR_COMP_ACCURATE	0x00000010

/* SoC revision stuff */
#define SOC_PRI_SHFT		16
#define SOC_SEC_SHFT		8

/* Revision definitions */
#define SOC_SPEAR_NA		0

/*
 * The definitons have started from
 * 101 for SPEAr6xx
 * 201 for SPEAr3xx
 * 301 for SPEAr13xx
 */
#define SOC_SPEAR600_AA		101
#define SOC_SPEAR600_AB		102
#define SOC_SPEAR600_BA		103
#define SOC_SPEAR600_BB		104
#define SOC_SPEAR600_BC		105
#define SOC_SPEAR600_BD		106

#define SOC_SPEAR300		201
#define SOC_SPEAR310		202
#define SOC_SPEAR320		203

extern int get_socrev(void);

#endif
Commit	Line	Data
81c0ebf6 VK	1	/*
	2	* (C) Copyright 2009
	3	* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
81c0ebf6 VK	6	*/
	7
	8	#ifndef _SPR_MISC_H
	9	#define _SPR_MISC_H
	10
	11	struct misc_regs {
	12	u32 auto_cfg_reg; /* 0x0 */
	13	u32 armdbg_ctr_reg; /* 0x4 */
	14	u32 pll1_cntl; /* 0x8 */
	15	u32 pll1_frq; /* 0xc */
	16	u32 pll1_mod; /* 0x10 */
	17	u32 pll2_cntl; /* 0x14 */
	18	u32 pll2_frq; /* 0x18 */
	19	u32 pll2_mod; /* 0x1C */
	20	u32 pll_ctr_reg; /* 0x20 */
	21	u32 amba_clk_cfg; /* 0x24 */
	22	u32 periph_clk_cfg; /* 0x28 */
	23	u32 periph1_clken; /* 0x2C */
f28e5c94	24	u32 soc_core_id; /* 0x30 */
81c0ebf6 VK	25	u32 ras_clken; /* 0x34 */
	26	u32 periph1_rst; /* 0x38 */
	27	u32 periph2_rst; /* 0x3C */
	28	u32 ras_rst; /* 0x40 */
	29	u32 prsc1_clk_cfg; /* 0x44 */
	30	u32 prsc2_clk_cfg; /* 0x48 */
	31	u32 prsc3_clk_cfg; /* 0x4C */
	32	u32 amem_cfg_ctrl; /* 0x50 */
4ae8bc43	33	u32 expi_clk_cfg; /* 0x54 */
81c0ebf6 VK	34	u32 reserved_1; /* 0x58 */
	35	u32 clcd_synth_clk; /* 0x5C */
	36	u32 irda_synth_clk; /* 0x60 */
	37	u32 uart_synth_clk; /* 0x64 */
	38	u32 gmac_synth_clk; /* 0x68 */
	39	u32 ras_synth1_clk; /* 0x6C */
	40	u32 ras_synth2_clk; /* 0x70 */
	41	u32 ras_synth3_clk; /* 0x74 */
	42	u32 ras_synth4_clk; /* 0x78 */
	43	u32 arb_icm_ml1; /* 0x7C */
	44	u32 arb_icm_ml2; /* 0x80 */
	45	u32 arb_icm_ml3; /* 0x84 */
	46	u32 arb_icm_ml4; /* 0x88 */
	47	u32 arb_icm_ml5; /* 0x8C */
	48	u32 arb_icm_ml6; /* 0x90 */
	49	u32 arb_icm_ml7; /* 0x94 */
	50	u32 arb_icm_ml8; /* 0x98 */
	51	u32 arb_icm_ml9; /* 0x9C */
	52	u32 dma_src_sel; /* 0xA0 */
	53	u32 uphy_ctr_reg; /* 0xA4 */
	54	u32 gmac_ctr_reg; /* 0xA8 */
	55	u32 port_bridge_ctrl; /* 0xAC */
	56	u32 reserved_2[4]; /* 0xB0--0xBC */
	57	u32 prc1_ilck_ctrl_reg; /* 0xC0 */
	58	u32 prc2_ilck_ctrl_reg; /* 0xC4 */
	59	u32 prc3_ilck_ctrl_reg; /* 0xC8 */
	60	u32 prc4_ilck_ctrl_reg; /* 0xCC */
	61	u32 prc1_intr_ctrl_reg; /* 0xD0 */
	62	u32 prc2_intr_ctrl_reg; /* 0xD4 */
	63	u32 prc3_intr_ctrl_reg; /* 0xD8 */
	64	u32 prc4_intr_ctrl_reg; /* 0xDC */
	65	u32 powerdown_cfg_reg; /* 0xE0 */
	66	u32 ddr_1v8_compensation; /* 0xE4 */
	67	u32 ddr_2v5_compensation; /* 0xE8 */
	68	u32 core_3v3_compensation; /* 0xEC */
	69	u32 ddr_pad; /* 0xF0 */
	70	u32 bist1_ctr_reg; /* 0xF4 */
	71	u32 bist2_ctr_reg; /* 0xF8 */
	72	u32 bist3_ctr_reg; /* 0xFC */
	73	u32 bist4_ctr_reg; /* 0x100 */
	74	u32 bist5_ctr_reg; /* 0x104 */
	75	u32 bist1_rslt_reg; /* 0x108 */
	76	u32 bist2_rslt_reg; /* 0x10C */
	77	u32 bist3_rslt_reg; /* 0x110 */
	78	u32 bist4_rslt_reg; /* 0x114 */
	79	u32 bist5_rslt_reg; /* 0x118 */
	80	u32 syst_error_reg; /* 0x11C */
	81	u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */
	82	u32 ras_gpp1_in; /* 0x8000 */
	83	u32 ras_gpp2_in; /* 0x8004 */
	84	u32 ras_gpp1_out; /* 0x8008 */
	85	u32 ras_gpp2_out; /* 0x800C */
	86	};
	87
4ae8bc43 SR	88	/* SYNTH_CLK value*/
	89	#define SYNTH23 0x00020003
	90
	91	/* PLLx_FRQ value */
	92	#if defined(CONFIG_SPEAR3XX)
	93	#define FREQ_332 0xA600010C
	94	#define FREQ_266 0x8500010C
	95	#elif defined(CONFIG_SPEAR600)
	96	#define FREQ_332 0xA600010F
	97	#define FREQ_266 0x8500010F
	98	#endif
	99
	100	/* PLL_CTR_REG */
	101	#define MEM_CLK_SEL_MSK 0x70000000
	102	#define MEM_CLK_HCLK 0x00000000
	103	#define MEM_CLK_2HCLK 0x10000000
	104	#define MEM_CLK_PLL2 0x30000000
	105
	106	#define EXPI_CLK_CFG_LOW_COMPR 0x2000
	107	#define EXPI_CLK_CFG_CLK_EN 0x0400
	108	#define EXPI_CLK_CFG_RST 0x0200
	109	#define EXPI_CLK_SYNT_EN 0x0010
	110	#define EXPI_CLK_CFG_SEL_PLL2 0x0004
	111	#define EXPI_CLK_CFG_INT_CLK_EN 0x0001
	112
	113	#define PLL2_CNTL_6UA 0x1c00
	114	#define PLL2_CNTL_SAMPLE 0x0008
	115	#define PLL2_CNTL_ENABLE 0x0004
	116	#define PLL2_CNTL_RESETN 0x0002
	117	#define PLL2_CNTL_LOCK 0x0001
	118
81c0ebf6 VK	119	/* AUTO_CFG_REG value */
	120	#define MISC_SOCCFGMSK 0x0000003F
	121	#define MISC_SOCCFG30 0x0000000C
	122	#define MISC_SOCCFG31 0x0000000D
	123	#define MISC_NANDDIS 0x00020000
	124
	125	/* PERIPH_CLK_CFG value */
	126	#define MISC_GPT3SYNTH 0x00000400
	127	#define MISC_GPT4SYNTH 0x00000800
7c885a0e SH	128	#define CONFIG_SPEAR_UART48M 0
7c885a0e SH	129	#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4)
81c0ebf6 VK	130
	131	/* PRSC_CLK_CFG value */
	132	/*
	133	* Fout = Fin / (2^(N+1) * (M + 1))
	134	*/
	135	#define MISC_PRSC_N_1 0x00001000
	136	#define MISC_PRSC_M_9 0x00000009
	137	#define MISC_PRSC_N_4 0x00004000
	138	#define MISC_PRSC_M_399 0x0000018F
	139	#define MISC_PRSC_N_6 0x00006000
	140	#define MISC_PRSC_M_2593 0x00000A21
	141	#define MISC_PRSC_M_124 0x0000007C
	142	#define MISC_PRSC_CFG (MISC_PRSC_N_1 \| MISC_PRSC_M_9)
	143
	144	/* PERIPH1_CLKEN, PERIPH1_RST value */
	145	#define MISC_USBDENB 0x01000000
962d026b VK	146	#define MISC_ETHENB 0x00800000
	147	#define MISC_SMIENB 0x00200000
	148	#define MISC_GPT3ENB 0x00010000
4ae8bc43	149	#define MISC_GPIO4ENB 0x00002000
962d026b VK	150	#define MISC_GPT2ENB 0x00000800
	151	#define MISC_FSMCENB 0x00000200
	152	#define MISC_I2CENB 0x00000080
4ae8bc43	153	#define MISC_SSP2ENB 0x00000070
962d026b	154	#define MISC_UART0ENB 0x00000008
81c0ebf6	155
4ae8bc43 SR	156	/* PERIPH_CLK_CFG */
	157	#define XTALTIMEEN 0x00000001
	158	#define PLLTIMEEN 0x00000002
	159	#define CLCDCLK_SYNTH 0x00000000
	160	#define CLCDCLK_48MHZ 0x00000004
	161	#define CLCDCLK_EXT 0x00000008
	162	#define UARTCLK_MASK (0x1 << 4)
	163	#define UARTCLK_48MHZ 0x00000000
	164	#define UARTCLK_SYNTH 0x00000010
	165	#define IRDACLK_48MHZ 0x00000000
	166	#define IRDACLK_SYNTH 0x00000020
	167	#define IRDACLK_EXT 0x00000040
	168	#define RTC_DISABLE 0x00000080
	169	#define GPT1CLK_48MHZ 0x00000000
	170	#define GPT1CLK_SYNTH 0x00000100
	171	#define GPT2CLK_48MHZ 0x00000000
	172	#define GPT2CLK_SYNTH 0x00000200
	173	#define GPT3CLK_48MHZ 0x00000000
	174	#define GPT3CLK_SYNTH 0x00000400
	175	#define GPT4CLK_48MHZ 0x00000000
	176	#define GPT4CLK_SYNTH 0x00000800
	177	#define GPT5CLK_48MHZ 0x00000000
	178	#define GPT5CLK_SYNTH 0x00001000
	179	#define GPT1_FREEZE 0x00002000
	180	#define GPT2_FREEZE 0x00004000
	181	#define GPT3_FREEZE 0x00008000
	182	#define GPT4_FREEZE 0x00010000
	183	#define GPT5_FREEZE 0x00020000
	184
	185	/* PERIPH1_CLKEN bits */
	186	#define PERIPH_ARM1_WE 0x00000001
	187	#define PERIPH_ARM1 0x00000002
	188	#define PERIPH_ARM2 0x00000004
	189	#define PERIPH_UART1 0x00000008
	190	#define PERIPH_UART2 0x00000010
	191	#define PERIPH_SSP1 0x00000020
	192	#define PERIPH_SSP2 0x00000040
	193	#define PERIPH_I2C 0x00000080
	194	#define PERIPH_JPEG 0x00000100
	195	#define PERIPH_FSMC 0x00000200
	196	#define PERIPH_FIRDA 0x00000400
	197	#define PERIPH_GPT4 0x00000800
	198	#define PERIPH_GPT5 0x00001000
	199	#define PERIPH_GPIO4 0x00002000
	200	#define PERIPH_SSP3 0x00004000
	201	#define PERIPH_ADC 0x00008000
	202	#define PERIPH_GPT3 0x00010000
	203	#define PERIPH_RTC 0x00020000
	204	#define PERIPH_GPIO3 0x00040000
	205	#define PERIPH_DMA 0x00080000
	206	#define PERIPH_ROM 0x00100000
	207	#define PERIPH_SMI 0x00200000
	208	#define PERIPH_CLCD 0x00400000
	209	#define PERIPH_GMAC 0x00800000
	210	#define PERIPH_USBD 0x01000000
	211	#define PERIPH_USBH1 0x02000000
	212	#define PERIPH_USBH2 0x04000000
	213	#define PERIPH_MPMC 0x08000000
	214	#define PERIPH_RAMW 0x10000000
	215	#define PERIPH_MPMC_EN 0x20000000
	216	#define PERIPH_MPMC_WE 0x40000000
	217	#define PERIPH_MPMCMSK 0x60000000
	218
	219	#define PERIPH_CLK_ALL 0x0FFFFFF8
220	#define PERIPH_RST_ALL 0x00000004
221
222	/* DDR_PAD values */
223	#define DDR_PAD_CNF_MSK 0x0000ffff
224	#define DDR_PAD_SW_CONF 0x00060000
225	#define DDR_PAD_SSTL_SEL 0x00000001
226	#define DDR_PAD_DRAM_TYPE 0x00008000
227
228	/* DDR_COMP values */
229	#define DDR_COMP_ACCURATE 0x00000010
230
231	/* SoC revision stuff */
232	#define SOC_PRI_SHFT 16
233	#define SOC_SEC_SHFT 8
234
235	/* Revision definitions */
236	#define SOC_SPEAR_NA 0
237
238	/*
239	* The definitons have started from
240	* 101 for SPEAr6xx
241	* 201 for SPEAr3xx
242	* 301 for SPEAr13xx
243	*/
244	#define SOC_SPEAR600_AA 101
245	#define SOC_SPEAR600_AB 102
246	#define SOC_SPEAR600_BA 103
247	#define SOC_SPEAR600_BB 104
248	#define SOC_SPEAR600_BC 105
249	#define SOC_SPEAR600_BD 106
250
251	#define SOC_SPEAR300 201
252	#define SOC_SPEAR310 202
253	#define SOC_SPEAR320 203
254
255	extern int get_socrev(void);
256
81c0ebf6	257	#endif