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e66c49fa VM |
1 | /* |
2 | * (C) Copyright 2016 | |
3 | * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef _STM32_GPT_H | |
9 | #define _STM32_GPT_H | |
10 | ||
11 | #include <asm/arch/stm32.h> | |
12 | ||
13 | struct gpt_regs { | |
14 | u32 cr1; | |
15 | u32 cr2; | |
16 | u32 smcr; | |
17 | u32 dier; | |
18 | u32 sr; | |
19 | u32 egr; | |
20 | u32 ccmr1; | |
21 | u32 ccmr2; | |
22 | u32 ccer; | |
23 | u32 cnt; | |
24 | u32 psc; | |
25 | u32 arr; | |
26 | u32 reserved; | |
27 | u32 ccr1; | |
28 | u32 ccr2; | |
29 | u32 ccr3; | |
30 | u32 ccr4; | |
31 | u32 reserved1; | |
32 | u32 dcr; | |
33 | u32 dmar; | |
34 | u32 tim2_5_or; | |
35 | }; | |
36 | ||
37 | struct gpt_regs *const gpt1_regs_ptr = | |
38 | (struct gpt_regs *)TIM2_BASE; | |
39 | ||
40 | /* Timer control1 register */ | |
bad5188b MK |
41 | #define GPT_CR1_CEN BIT(0) |
42 | #define GPT_MODE_AUTO_RELOAD BIT(7) | |
e66c49fa VM |
43 | |
44 | /* Auto reload register for free running config */ | |
45 | #define GPT_FREE_RUNNING 0xFFFFFFFF | |
46 | ||
47 | /* Timer, HZ specific defines */ | |
48 | #define CONFIG_STM32_HZ 1000 | |
49 | ||
50 | /* Timer Event Generation registers */ | |
bad5188b | 51 | #define TIM_EGR_UG BIT(0) |
e66c49fa VM |
52 | |
53 | #endif |